Xilinx MicroBlaze Reference Manual page 34

Chapter 2: MicroBlaze Architecture
Floating Point Status Register (FSR)
The Floating Point Status Register contains status bits for the floating point unit. It can be read with
an MFS, and written with an MTS instruction. When read or written, the register is specified by
setting Sa = 0x0007. The bits in this register are sticky − floating point instructions can only set bits
in the register, and the only way to clear the register is by using the MTS instruction.
illustrates the FSR register and
Table 2-14: Floating Point Status Register (FSR)
0:26
27
28
29
30
31
Exception Data Register (EDR)
The Exception Data Register stores data read on a stream link (FSL or AXI) that caused a stream
exception.
The contents of this register is undefined for all other exceptions. When read with the MFS
instruction, the EDR is specified by setting Sa = 0x000D.
Table 2-15
Note:
is set to 1.
0
Table 2-15: Exception Data Register (EDR)
0:31
34
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↑
RESERVED
Figure 2-8: FSR
Bits Name
Reserved
IO Invalid operation
DZ Divide-by-zero
OF Overflow
UF Underflow
DO Denormalized operand error
provides bit descriptions and reset values.
The register is only implemented if C_FSL_LINKS is greater than 0 and C_FSL_EXCEPTION
Figure 2-9: EDR
Bits Name
EDR Exception Data Register
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Table 2-14 provides bit descriptions and reset values.
Description
Figure 2-9
↑
EDR
Description
MicroBlaze Processor Reference Guide
Figure 2-8
27 28 29 30 31
↑ ↑ ↑ ↑ ↑
IO DZ OF UF DO
Reset Value
undefined
0
0
0
0
0
illustrates the EDR register and
31
Reset Value
0x00000000
UG081 (v14.7)