Xilinx MicroBlaze Reference Manual page 28

Chapter 2: MicroBlaze Architecture
Table 2-9: Machine Status Register (MSR) (Continued)
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Bits Name
EE Exception Enable
0 = Hardware exceptions disabled
1 = Hardware exceptions enabled
Only available if configured with exception support
(C_*_EXCEPTION or C_USE_MMU > 0)
Read/Write
DCE Data Cache Enable
0 = Data Cache disabled
1 = Data Cache enabled
Only available if configured to use data cache
(C_USE_DCACHE = 1)
Read/Write
DZO Division by Zero or Division Overflow
0 = No division by zero or division overflow has occurred
1 = Division by zero or division overflow has occurred
Only available if configured to use hardware divider
(C_USE_DIV = 1)
Read/Write
ICE Instruction Cache Enable
0 = Instruction Cache disabled
1 = Instruction Cache enabled
Only available if configured to use instruction cache
(C_USE_ICACHE = 1)
Read/Write
FSL Stream (FSL or AXI) Error
0 = get or getd had no error
1 = get or getd control type mismatch
This bit is sticky, i.e. it is set by a get or getd instruction
when a control bit mismatch occurs. To clear it an mts or
msrclr instruction must be used.
Only available if configured to use stream links
(C_FSL_LINKS > 0)
Read/Write
BIP Break in Progress
0 = No Break in Progress
1 = Break in Progress
Break Sources can be software break instruction or hardware
break from Ext_Brk or Ext_NM_Brk pin.
Read/Write
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Description
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MicroBlaze Processor Reference Guide
Reset Value
0
0
0
0
0
0
UG081 (v14.7)