Xilinx MicroBlaze Reference Manual page 100

Chapter 3: MicroBlaze Signal Interface Description
Table 3-1: Summary of MicroBlaze Core I/O (Continued)
M_AXI_DC_BID
M_AXI_DC_BVALID
M_AXI_DC_BREADY
M_AXI_DC_BUSER
M_AXI_DC_WACK
M_AXI_DC_ARID
M_AXI_DC_ARADDR
M_AXI_DC_ARLEN
M_AXI_DC_ARSIZE
M_AXI_DC_ARBURST
M_AXI_DC_ARLOCK
M_AXI_DC_ARCACHE
M_AXI_DC_ARPROT
M_AXI_DC_ARQOS
M_AXI_DC_ARVALID
M_AXI_DC_ARREADY
M_AXI_DC_ARUSER
M_AXI_DC_ARDOMAIN
M_AXI_DC_ARSNOOP
M_AXI_DC_ARBAR
M_AXI_DC_RID
M_AXI_DC_RDATA
M_AXI_DC_RRESP
M_AXI_DC_RLAST
M_AXI_DC_RVALID
M_AXI_DC_RREADY
M_AXI_DC_RUSER
M_AXI_DC_RACK
M_AXI_DC_ACVALID
M_AXI_DC_ACADDR
M_AXI_DC_ACSNOOP
M_AXI_DC_ACPROT
100
Send Feedback
Signal Interface
M_AXI_DC
M_AXI_DC
M_AXI_DC
M_AXI_DC
M_ACE_DC
M_AXI_DC
M_AXI_DC
M_AXI_DC
M_AXI_DC
M_AXI_DC
M_AXI_DC
M_AXI_DC
M_AXI_DC
M_AXI_DC
M_AXI_DC
M_AXI_DC
M_AXI_DC
M_ACE_DC
M_ACE_DC
M_ACE_DC
M_AXI_DC
M_AXI_DC
M_AXI_DC
M_AXI_DC
M_AXI_DC
M_AXI_DC
M_AXI_DC
M_ACE_DC
M_ACE_DC
M_ACE_DC
M_ACE_DC
M_ACE_DC
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I/O Description
I Slave Response ID
I Slave Write response valid
O Master Response ready
I Slave Write response user signals
O Slave Write acknowledge
O Master Read address ID
O Master Read address
O Master Burst length
O Master Burst size
O Master Burst type
O Master Lock type
O Master Cache type
O Master Protection type
O Master Quality of Service
O Master Read address valid
I Slave Read address ready
O Master Read address user signals
O Master Read address domain
O Master Read address snoop
O Master Read address barrier
I Slave Read ID tag
I Slave Read data
I Slave Read response
I Slave Read last
I Slave Read valid
O Master Read ready
I Slave Read user signals
O Master Read acknowledge
I Slave Snoop address valid
I Slave Snoop address
I Slave Snoop address snoop
I Slave Snoop address protection type
MicroBlaze Processor Reference Guide
UG081 (v14.7)