Xilinx MicroBlaze Reference Manual page 117

Back-to-Back Read Operation
Clk
Addr
Byte_Enable
Data_Write
AS
Read_Strobe
Write_Strobe
Data_Read
Ready
Wait
CE
UE
Back-to-Back Mixed Write/Read Operation
Clk
Addr
Byte_Enable
Data_Write
AS
Read_Strobe
Write_Strobe
Data_Read
Ready
Wait
CE
UE
MicroBlaze Processor Reference Guide
UG081 (v14.7)
A0 A1
D0
Don't Care
Figure 3-7: LMB Back-to-Back Read Operation
A0
BE0
D0
Figure 3-8: Back-to-Back Mixed Write/Read Operation, 0 Wait States
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Local Memory Bus (LMB) Interface Description
A2
D1
Don't Care
A1 A2
BE2
D2
D1
Don't Care
A3 A4
D2 D3 D4
Don't Care
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