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10.2.2.3.2 Protocol.
Figure 10-8 shows the protocol for the cpDBcc instructions.
The MC68030 transfers the condition selector to the coprocessor by writing
the word following the operation word to the condition CIR. The main pro-
cessor then reads the response CIR to determine its next action. The copro-
cessorcan use a response primitive to request any services necessary to
evaluate the condition. If the coprocessor returns the true condition indicator,
the main processor executes the next instruction in the instruction stream.
If the coprocessor returns the false condition indicator, the main processor
decrements the low-order word of the register specified by bits [0-2] of the
F-line operation word. If this register contains minus one (-1) after being
decremented, the main processor executes the next instruction in the in-
struction stream. If the register does not contain minus one ( -1) after being
decremented, the main processor branches to the destination address to
continue instruction execution.
The MC68030 adds the displacement to the scanPC (refer to 10.4.1 ScanPC)
to determine the address of the next instruction. The scanPC must point to
the 16-bit displacement in the instruction stream when the destination ad-
dress is calculated.
10.2.2.4 TRAP ON COPROCESSOR CONDITION.
The trap on coprocessor condi-
tion instruction allows the programmer to initiate exception processing based
on conditions related to the coprocessor operation.
10.2.2.4.1 Format.
Figure 10-13 shows the format of the trap on coprocessor con-
dition instruction, denoted by the cpTRAPcc mnemonic.
15
14
13
12
11
4
1 1 1
I
1
I
1
I
CplD
1 0 1
n
I
1
I
1
I
11
1
I
OPMODE
mESERVEDj
I
CONDITION SELECTOR
OPTIONAL COPROCESSOR-DEFINED EXTENSION WORDS
OPTIONAL WORD
OR LONG-WORD OPERAND
Figure 10-13. Trap On Coprocessor Condition (cpTRAPcc)
10-18
MC68030 USER'S MANUAL
MOTOROLA
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