Motorola MC68030 User Manual page 264

7-102
negated and signal T remains asserted. With acknowledge A asserted, the
arbiter remains in state 4 until A is negated or request R is again asserted.
When A is negated, the arbiter returns to the original state, state 0, and
negates signal T. This sequence of states follows the normal sequence of
signals for relinquishing the bus to an external bus master. Other states apply
to other possible sequences of combinations of Rand A. As shown by the
path from state 0 to state 4, BGACK alone can be used to place the processor's
external bus buffers in the high-impedance state, providing single-wire ar-
bitration capability.
The read-modify-write sequence is normally indivisible to support sema-
phore operations and multiprocessor synchronization. During this indivisible
sequence, the MC68030 asserts the RMC signal and causes the bus arbitration
state machine to ignore bus requests (assertions of BR) that occur after the
first read cycle of the read-modify-write sequence by not issuing bus grants
(asserting BG).
In some cases, however, it may be necessary to force the MC68030 to release
the bus during an read-modify-write sequence. One way for an alternate bus
master to force the MC68030 to release the bus applies only to the first read
cycle of an read-modify-write sequence. The MC68030 allows normal.bus
arbitration during this read cycle; a normal relinquish and retry operation
(asserting BERR, HALT, and BR at the same time) is used. Note that this
method applies only to the first read cycle of the read-modify-write sequence,
but this method preserves the integrity of the read-modify-write sequence
without imposing any constraint on the alternate bus master.
A second method is single-wire arbitration, the timing of which is shown in
Figure 7-62. An alternate master forces the MC68030 to release the bus by
asserting BGACK 'and waits for AS to negate before taking the bus. It applies
to all bus cycles of a read-modify-write sequence, but can cause system
integrity problems if used improperly. The alternate bus master must guar-
antee the integrity of the read-modify-write sequence by not altering the
contents of memory locations accessed by the read-modify-write sequence.
Note that for the method to operate properly, AS must be observed to be
negated (high) on two consecutive clock edges before the alternate bus mas-
ter takes the bus. Waiting for this condition ensures that any current or
pending bus activity has completed or has been pre-empted.
MC68030 USER'S MANUAL
MOTOROLA