Motorola MC68030 User Manual page 296

S.2.1 Special Status Word (SSW)
8-28
The internal SSW (see Figure 8-9) is one of several registers saved as part
of the bus fault exception stack frame. Both the short bus cycle fault format
and the long bus cycle fault format include this word at offset $A. The bus
cycle fault stack frame formats are described in detail at the end of this
section.
15 14 13 12 11
10 7 6 4
FC FB RC RB X
x x
I
OF RM
I
RW
I
SIZE
FC
FB
RC
RB
OF
RM
RW
SIZE
FC2-FCO
- Fault on stage C of the instruction pipe
- Fault on stage B of the instruction pipe
- Rerun flag for stage C of the instruction pipe*
- Rerun flag for stage B of the instruction pipe*
- Fault/rerun flag for data cycle*
- Read-modify-write on data cycle
- Read/write for data cycle - 1
=
read, 0
=
write
- Size code for data cycle
- Address space for data cycle
*1
=
Rerun Faulted bus Cycle, or run pending prefetch
0=00 not rerun bus sycle
X
=
For internal use only
\
Figure 8-9. Special Status Word (SSW)
x
I
FC2-FCO
The SSW information indicates whether the fault was caused by an access
to the instruction stream, data stream, or both. The high-order half of the
SSW contains two status bits each for the Band C stages of the instruction
pipe. The fault bits (FB and FC) indicate that the processor attempted to use
a stage (B or C) and found it to be marked invalid due to a bus error on the
prefetch for that stage. The fault bits can be used by a bus error handler to
determine the cause(s) of a bus error exception. The rerun flag bits (RB and
RC) are set to indicate that a fault occurred during a prefetch for the corre-
sponding stage. A rerun bit is always set when the corresponding fault bit
is set. The rerun bits indicate that the word in a stage of the instruction pipe
is invalid, and the state of the bits can be used by a handler to repair the
values in the pipe after an address error or a bus error, if necessary. If a rerun
bit is set when the processor executes an RTE instruction, the processor may
execute a bus cycle to prefetch the instruction word for the corresponding
stage of the pipe (if it is required). If the rerun and fault bits are set for a
stage of the pipe, the RTE instruction automatically reruns the prefetch cycle
for that stage. The address space for the bus cycle is the program space for
the privilege level indicated in the copy of the status register on the stack. If
a rerun bit is cleared, the words on the stack for the corresponding stages
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