Motorola MC68030 User Manual page 143

lONG WORD
SELECT
r -__
~
__________
-JI_G __________
~I~
I
III
I In
F F F A ••• A A A A A A A A A A A A A A A A A A A A A A A A
C C C 3 ••• 2 2 2 2 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 ACCESS ADDRESS
210 1 ••• 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
II I I I
I
I
TAG V V V V
1 OF 16
SELECT - .
· · · ·
·
·
· · · ·
· · · ·
·
TAG
REPLACE
t
I
VALID
I
I
COMPARATOR
I
I
LINE HIT
II I
·
·
· ·
· ·
I
t
~
I
J
-
· ·
·
·
· ·
t t
ENTRY HIT
-t
T
DATA FROM INSTRUCTON
CACHE DATA BUS
DATA TO INSTRUCTION
CACHE HOlOiNG REGISTER
CACHE CONTROL lOGIC
CACHE SIZE
=
64 (lONG WORDS I
LINE SIZE = 4 (LONG WORDSI
SET SIZE
=
1
Figure 6-2. On-Chip Instruction Cache Organization
When enabled, the instruction cache is used to store instruction prefetches
(instruction words and extension words) as they are requested by the CPU.
Instruction prefetches are normally requested from sequential memoryad-
dresses except when a change of program flow occurs (e.g., a branch taken)
or when an instruction is executed that can modify the status register, in
which cases the instruction pipe is automatically flushed and refilled. The
output signal REFILL indicates this condition. For more information on the
operation of this signal, refer to SECTION 12 APPLICATIONS INFORMATION.
In the instruction cache, each of the 16 lines has a tag consisting of the 24
most significant logical address bits, the FC2 function code bit (used to dis-
tinguish between user and supervisor accesses), and the four valid bits (one
MOTOROLA
MC68030 USER'S MANUAL
6-5