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11.6.10 Binary-Coded Decimal and Extended Instructions
The binary-coded decimal and extended instructicm table indicates the number
of clock periods needed for the processor to perform the specified operation
using the given addressing modes. No additional tables are needed to calculate
total effective execution time for these instructions. For instruction-cache case
and for no-cache case, the total number of clock cycles is outside the
parentheses. The number of read, prefetch, and write cycles is given inside
the parentheses as (r/p/w). The read, prefetch, and write cycles are included
in the total clock cycle number.
All timing data assumes two-clock reads and writes.
Instruction
Head
Tail
I-Cache Case
No-Cache Case
ABCD
Dn,Dn
0
0
4(01010)
4(0/1/0)
ABCD
- (An), - (An)
2
1
13(210/1)
14(2/1/1)
SBCD
Dn,Dn
0
0
4(01010)
4(0/1/0)
SBCD
-(Anl,-(An)
2
1
13(2/0/1)
14(2/1/1)
ADDX
Dn,Dn
2
0
2(01010)
2(0/1/0)
ADDX
-(Anl.-(An)
2
1
9(2/0/1)
10(211/1)
SUBX
Dn,Dn
2
0
2(01010)
2(0/1/0)
SUBX
- (An), - (An)
2
1
9(2/0/1)
10(2/111 )
CMPM
(An)+,(An)+
0
0
8(2/010)
8(2/1/0)
PACK
Dn,Dn,#(data)
6
0
6(01010)
6(0/1/0)
PACK
- (An), - (Anl.#(data)
2
1
11(11011)
11 (111/1)
UNPK
Dn,Dn,#(data)
8
0
8(01010)
8(0/1/0)
UNPK
- (An), - (An),#(data)
2
1
11(1/0/1 )
11(1/1/1 )
MOTOROLA
MC68030 USER'S MANUAL
11-43
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