Motorola MC68030 User Manual page 531

Only control-alterable addressing modes are allowed for MMU instructions
on the MC68030.
A feature new to the MC68030 MMU (and not on the MC68851) is the trans-
parent translation of two logical address blocks with the transparent trans-
lation registers. See SECTION 9 MEMORY MANAGEMENT UNIT.
12.2
FLOATING-POINT UNITS
Floating-point support for the MC68030 is provided by the MC68881 floating-
point coprocessor and the MC68882 enhanced floating-point coprocessor.
Both devices offer a full implementation of the IEEE Standard for Binary
Floating-Point Arithmetic (754). The MC68882 is a pin and software-compatible
upgrade of the MC68881, with an optimized MPU interface that provides over
1.5 times the performance of the MC68881 at the same clock frequency.
Both coprocessors provide a logical extension to the integer data processing
capabilities of the main processor. They contain a very high performance
floating-point arithmetic unit and a set of floating-point data registers that
are utilized in a manner that is analagous to the use of the integer data
registers of the processor. The MC68881/MC68882 instruction set is a natural
extension of all earlier members of the M68000 Family and supports all of
the addressing modes and data types of the host MC68030. The programmer
perceives the MC68030/coprocessor execution model as if both devices are
implemented on one chip. In addition to supporting the full IEEE standard,
the MC68881 and MC68882 provide a full set of trigonometric and transcen-
dental functions, on-chip constants, and a full 80-bit extended-precision-real
data format.
The interface of the MC68030 to the MC68881 or the MC68882 is easily tailored
to system cost/performance needs. The MC68030 and the MC68881/MC68882
communicate via standard asynchronous M68000 bus cycles. All data trans-
fers are performed by the main processor at the request of the MC68881/
MC68882; thus memory management, bus errors, address errors, and bus
arbitration function as if the MC68881/MC68882 instructions are executed by
the main processor. The floating-point unit and the processor may operate
at different clock speeds, and up to seven floating-point coprocessors may
reside in an MC68030 system simultaneously.
Figure 12-2 illustrates the coprocessor interface connection of an MC68881/
MC68882 to an MC68030 (uses entire 32-bit data bus). The MC68881/MC68882
is configured to operate with a 32-bit data bus when both the
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MC68030 USER'S MANUAL 12-5