Motorola MC68030 User Manual page 465

SECTION 11
INSTRUCTION EXECUTION TIMING
This section describes the instruction execution and operations (table
searches, etc.) of the MC68030 in terms of external clock cycles. It provides
accurate execution and operation timing guidelines but not exact timings for
every possible circumstance. This approach is used since exact execution
time for an instruction or operation is highly dependent on memory speeds
and other variables. The timing numbers presented in this section allow the
assembly language programmer or compiler writer to predict actual cache-
case and average no-cache-case timings needed to evaluate the performance
of the MC68030. Additionally, the timings for exception processing, context
switching, and interrupt processing are included so that designers of multi-
tasking or real-time systems can predict task switch overhead, maximum
interrupt latency, and similar timing parameters.
In this section, instruction and operation times are shown in clock cycles to
eliminate clock frequency dependencies.
11.1 PERFORMANCE TRADEOFFS
The MC68030 maximizes average performance at the expense of worst case
performance. The time spent executing one instruction can vary from zero
to over 100 clocks. Factors affecting the execution time are the preceding
and following instructions, the instruction stream alignment, residency of
operands and instruction words in the caches, residency of address trans-
lations in the address translation cache, and operand alignment.
To increase the average performance of the MC68030, certain tradeoffs were
made to increase best case performance and to decrease the occurrence of
worst case behavior. For example, burst filling increases performance by
prefetching data for later accesses, but it commits the external bus controller
and a cache for a longer period.
The MC68030 can overlap data writes with instruction cache reads, data cache
reads, and/or microsequencer execution. Instruction cache reads can be over-
lapped with data cache fills and/or microsequencer activity. Similarly, data
cache reads can be overlapped with instruction cache fills and/or micro-
MOTOROLA MC68030 USER'S MANUAL 11-1
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