Motorola MC68030 User Manual page 418

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10.3.2 Control CIR
The main processor writes to the 2-bit control CIR to acknowledge copro-
cessor-requested exception processing or to abort the execution of a copro-
cessor instruction. The offset from the base address of the CIR set for the
control CIR is $02. The control CIR occupies the two least significant bits of
the word at that offset. The ·14 most significant bits ofthe word are undefined.
Figure 10-19 shoyvs the format of this register.
15 1 0
(UNDEFINED, RESERVED)
XA
I
AB
I
Figure 10-19. Control CIR Format
When the MC68030
rec~ives
one of the thr'ee take exception coprocessor
response primitives, it acknowledges the primitive by writing the exception
acknowledge mask (102) to the control CIR, which sets the exception ac-
knowledge (XA) bit. The MC68030 writes the abort mask (012), which sets
the abort (AS) bit, to the control CIR to abort any coprocessor instruction in
progress. (The most significant 14 bits of both masks are undefined.) The
MC68030 aborts a coprocessor instruction when it detects one of the follow-
ing exception conditions: .
• An F-line emulator exception condition after reading a response primitive
• A privilege violation exception as it performs a supervisor check in re-
sponse to a supervisor check primitive
• A format error exc'eption when it receives an invalid format word or a
valid format word that contains an invalid length
10.3.3 Save CIR
10-30
The coprocessor uses the 16-bit save CIR to communicate status and state
frame format information to the main processor while executing a cpSAVE
instruction. The main processor reads the save CIR to initiate execution of
the cpSAVE instruction by the coprocessor. The offset from the base address
of the CIR set for the save CIR is $04. Refer to 10.2.3.2 COPROCESSOR FOR·
MAT WORDS.
MC68030 USER'S MANUAL
MOTOROLA