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10.2.2.1.1 Format.
Figure 10-9 shows the format of the branch on coprocessor
condition instruction that provides a word-length displacement. Figure
10-10 shows the format of the instruction that includes a long-word displace-
ment.
10-14
15
14
13
12
11
1 1 1 1 1 1 11
CplD
1
0
1 1 1
0
1
CONDITION SELECTOR
OPTIONAL COPROCESSOR-DEFINED EXTENSION WORDS
DISPLACEMENT
Figure 10-9. Branch on Coprocessor Condition Instruction (cpBcc.W)
15
14
13
12
11
9
o
1 1 1 1 1 1 1 1
CplD
1
0
1 1 1 1 1
CONDITION SELECTOR
OPTIONAL COPROCESSOR-DEFINED EXTENSION WORDS
DISPLACEMENT - HIGH
DISPLACEMENT - LOW
Figure 10-10. Branch On Coprocessor Condition Instruction (cpBcc.L)
The first word of the branch on coprocessor condition instruction is the
F-line operation word. Bits [15: 12]
=
1111 and bits [11 :9] contain the identi-
fication code of the coprocessor that is to evaluate the condition. The value
in bits [8:6] identifies either the word or the long-word displacement format
of the branch instruction, which is specified by the cpBcc.W or cpBcc.L mne-
monic, respectively.
Bits [0-5] of the F-line operation word contain the coprocessor condition
selector field. The MC68030 writes the entire operation word to the condition
CIR to initiate execution of the branch instruction by the coprocessor. The
coprocessor uses bits [0-5] to determine which condition to evaluate.
If the coprocessor requires additional information to evaluate the condition,
the branch instruction format can include this information in extension words.
Following the F-line operation word, the number of extension words is de-
termined by the coprocessor design. The final word(s) of the cpBcc instruction
format contains the displacement used by the main processor to calculate
the destination address when the branch is taken.
MC68030 USER'S MANUAL
MOTOROLA
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