Motorola MC68030 User Manual page 306

III
9-4
63
32
CPU ROOT
POINTER
31
63 32
SUPERVISOR ROOT
POINTER
31
31
TRANSLATION CONTROL
31
____________________________________
~I
TRANSPARENT TRANSLATION 0
31
TRANSPARENT TRANSLATION 1
15
MMU STATUS (MMUSR)
Figure 9-2. MMU Programming Model
AODRESS
TRANSLATION
CONTROL
REGISTERS
}
STATUS
INFORMATION
REGISTER
The ATC in the MMU is a fully associative cache that stores 22 logical-to-
physical address translations and associated page information. It compares
the logical address and function code internally supplied by the processor
with all tag entries in the ATC. When the access address and function code
matches atag in the ATC (a hit occurs) and no access violation is detected,
the ATC outputs the corresponding physical address to the bus controller,
which continues the external bus cycle. Function codes are routed to the bus
controller unmodified.
Each ATC entry contains a logical address, a physical address, and status
bits. Among the status bits are the write protect and cache inhibit bits.
When the ATC does not contain the translation for a logical address (a miss
occurs) and an external bus cycle is required, the MMU aborts the access
and causes the processor to initiate bus cycles that search the translation
tables in memory for the correct translation. If the table search completes
without any errors, theMMU stores the translation in the ATC and provides
the physical address for the access, allowing the bus controller to retry the
original bus cycle.
MC68030 USER'S MANUAL MOtOROLA