Motorola MC68030 User Manual page 265

~----SEE NOTE ----~
elK
AS
- - - - t - - '
ADDRESS
NOTE: The alternate bus master must sample AS high on two consecutive rising edges of the clock (after BGACK is recognized
low) before taking the bus.
Figure 7-62. Single-Wire Bus Arbitration Timing Diagram
A timing diagram of the bus arbitration sequence during a processor bus
cycle is shown in Figure 7-60. The bus arbitration sequence while the bus is
inactive (i.e., executing internal operations such as a multiply instruction) is
shown in Figure 7-63.
7.8 RESET OPERATION
RESET is a bidirectional signal with which an external device resets the
system or the processor resets external devices. When power is applied to
the system, external circuitry should assert RESET for a minimum of 520
clocks after
Vee
is within tolerance. Figure 7-64 is a timing diagram of the
powerup reset operation, showing the relationships between RESET,
Vee,
and bus signals. The clock signal is required to be stable by the time
Vee
reaches the minimum operating specification. During the reset period, the
entire bus three-states (except for non-three-statable signals, which are dri-
ven to their inactive state). Once RESET negates, all control signals are driven
to their inactive state, the data bus is in read mode, and the address bus is
driven. After this, the first bus cycle for reset exception processing begins.
MOTOROLA MC68030 USER'S MANUAL 7-103