Motorola MC68030 User Manual page 319

By appropriately configuring a transparent translation register, flexible trans-
parent mapping can be specified. For instance, to transparently translate user
program space with a TTx register, the RWM bit of the register is set to 1,
the FC BASE is set to $2, and the FC MASK is set to $0. To transparently
translate supervisor data read accesses of addresses $OOOOOOOO-$OFFFFFFF,
the LOGICAL BASE ADDRESS field is set to SOX, the LOGICAL ADDRESS
MASK is set to $OF, the
R/W
bit is set to 1, the RWM bit is set to 0, the FC
BASE is set to $5, and the FC MASK field is set to $0. Since only read cycles
are specified by the TTx register for this example, write accesses for this
address range can be translated with the translation tables and write pro-
tection can be implemented as required.
Each TTx register can specify that the contents of logical addresses in its
block should not be stored in either an internal or external cache. The cache
inhibit out signal (ClOUT) is asserted when an address matches the address
specified by a TTx register and the cache inhibit bit in that TTx register is
set. ClOUT is used by the on-chip instruction and data caches to inhibit
caching of data associated with this address. The signal is available to ex-
ternal caches for the same purpose.
For an access, if either of these registers match, the access is transparently
translated. If both registers match, the CI bits are ORed together to generate
the ClOUT signal.
Transparent translation can also be implemented by the translation tables
of the translation trees if the physical addresses of pages are set equal to
the logical addresses.
9.4 ADDRESS TRANSLATION CACHE
The ATC is a 22-entry fully associative (content addressable) cache that con-
tains address translations in a form similar to the corresponding page de-
scriptors in memory to provide fast address translation of a recently used
logical address.
The MC68030 is organized such that the translation time of the ATC is always
completely overlapped by other operations; thus, no performance penalty is
associated with ATC searches. The address translation occurs in parallel with
on-chip instruction and data cache accesses before an external bus cycle
begins.
MOTOROLA
MC68030 USER'S MANUAL 9-17