Table of Contents
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TABLE OF CONTENTS (Continued)
Paragraph
Number
Title
.Page
Number
11.6
11.6.1
11.6.2
11.6.3
11.6.4
11.6.5
11.6.6
11.6.7
11.6.8
11.6.9
11.6.10
11.6.11
11.6.12
11.6.13
11.6.14
11.6.15
11.6.16
11.6.17
11.6.18
11.7
11.7.1
11.7.2
11.8
11.9
Instruction Timing Tables .......... : ............................................. 11-24
Fetch Effective Address (fea) ... ; .......................................... 11-26
Fetch Immediate Effective Address (fiea) ............................. 11-28
Calculate Effective Address (cea) ........................................ 11-30
Calculate Immediate Effective Address Mode (ciea). ............. 11-32
Jump Effective Address ..................................................... 11-35
MOVE Instruction .............................................................. 11-37
Special-Purpose MOVE Instruction ...................................... 11-39
Arithmetical/Logical Instructions ......................................... 11-40
Immediate Arithmetical/Logical Instructions ......................... 11-42
Binary-Coded Decimal and Extended Instructions ................. 11-43
Single Operand Instructions ............................................... 11-44
Shift/Rotate Instructions .................................................... 11-45
. Bit Manipulation Instructions ............................................. 11-46
Bit Field Manipulation Instructions .... : ................................. 11-47
Conditional Branch Instructions ........... · ............................... 11-48
Control Instructions ........................................................... 11·:-49
Exception-Related Instructions and Operations .................... 11-50
Save and Restore Operations ............................................. 11-51
Address Translation Tree Search Timing ................................... 11-51
MMU Effective Address Calculation .................................... 11-58
MMU Instruction Timing .................................................... 11-60
Interrupt Latency .................................................................... 11-61
Bus Arbitration Latency ............................................................ 11-62
Section 12
Applications Information
12.1
Adapting the MC68030 to MC68020 Designs .............................. 12-1
12.1.1
Signal Routing .................................................................. 12-2
12.1.2
Hardware Differences ........................................................ 12-3
12.1.3
Software Differences ......................................................... 12-4
12.2
Floating-Point Units ................................................................. 12-5
12.3
Byte Select Logic for the MC68030 ........................................... 12-9
12.4
Memory Interface ................................................................... 12-11
12.4.1
Access Time Calculations .................................................. 12-14
12.4.2
Burst Mode Cycles ............................................................ 12-17
12.5
Static RAM Memory Banks ...................................................... 12-18
12.5.1
A Two Clock Synchronous Memory Bank Using SRAMs ....... 12-18
xiv
MC68030 USER'S
MANUAL
MOTOROLA
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