Motorola MC68030 User Manual page 240

7-78
To properly control termination of a bus cycle for a retry or a bus error
condition, DSACKx, BERR, and HALT can be asserted and negated with the
rising edge of the MC68030 clock. This assures that when two signals are
asserted simultaneously, the required setup time (#47A) and hold time (#47B)
for both of them is met for the same falling edge of the processor clock.
(Refer to MC68030EC/D, MC68030 Electrical Specifications for timing require-
ments.) This or some equivalent precaution should be designed into the
external circuitry that provides these signals.
The acceptable bus cycle terminations for asynchronous cycles are sum-
marized in relation to DSACKx assertion as follows (case numbers refer to
Table 7-8):
Normal Termination:
DSACKx is asserted; BERR and HALT remain negated (case 1).
Halt Termination:
HALT is asserted at same time or before DSACKx, and BERR remains
negated (case 2).
Bus Error Termination:
BERR is asserted in lieu of, at the same time, or before DSACKx (case
3) or after DSACKx (case 4), and
HALf
remains negated; BERR is
negated at the same time or after DSACKx.
Retry Termination:
HALf
and BERR are asserted in lieu of, at the same time, or before
DSACKx (case 5) or after DSACKx (case 6); BERR is negated at the
same time or after DSACKx; HALT may be negated at the same time
or after BERR.
MC68030 USER'S MANUAL
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