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11.6.1 Fetch Effective Address (fea)
11-26
The fetch effective address table indicates the number of clock periods needed
for the processor to calculate and fetch the specified effective address. The
effective addresses are divided by their formats (refer to 2.5 Effective Address
Encoding Summary). For instruction-cache case and for no-cache case, the
total number of clock cycles is outside the parentheses. The number of read,
prefetch, and write cycles is given inside the parentheses as (r/p/w). The read,
pre-fetch, and write cycles are included in the total clock cycle number.
All timing data assumes two-clock reads and writes.
Address Mode
SINGLE EFFECTIVE ADDRESS INSTRUCTION FORMAT
%
Dn
-
-
0(01010)
0(01010)
%
An
-
-
0(0/0/0)
0(01010)
(An)
1
1
3(1/010)
3(1/010)
(An)+
0
1
3(1/010)
3(1/010)
-(An)
2
2
4(1/010)
4(1/010)
(d16.An) or (d16,PC)
2
2
4(1/010)
4(1/1/0)
(xxx).w
2
2
4(1/010)
4(1/1/0)
(xxx).L
1
0
4(1/010)
5(1/1/0)
#(data).B
2
0
2(0/0/0)
2(0/1/0)
#(data).w
2
0
2(0/0/0)
2(0/1/0)
#(data).L
4
0
4(0/0/0)
4(0/1/0)
BRIEF FORMAT EXTENSION WORD
I
(da.An,Xn) or (da,PC,Xn)
4
2
6(1/0/0)
6(1/1/0)
MC68030 USER'S MANUAL
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