Motorola MC68030 User Manual page 534

•
PAl1618
ClK
AS
FC2
FCI
FCD
A19
AlB
A17
A16
GND
PAL 16lB
10 ns
VCC
NC
NC
NC
NC
A13
A14
ClKD
CS
A15
Figure
12-3.
Chip-Select Generation PAL
FPCP CS GENERATION CIRCUITRY FOR 25 MHz OPERATION
MOTOROLA INC., AUSTIN, TEXAS
ClK AS FC2 FC1 FCO A19 A18 A17 A16 GND
VCC
A15
ICS
IClKD A14 A13 NC NC NC NC
CS
=
FC2 * FC1 * FCO
;cpu space
=
$7
*
IA19
*
IA18 * A17
*
IA16
;coprocessor access
=
$2
*
IA15
*
IA14 * A13
;coprocessor id
=
$1
* IClK
;qualified by MPU clock low
+
FC2 * FC1 * FCO
;cpu space
=
$7
*
IA19
*
IA18
* A17
*
IA16
;coprocessor access
=
$2
*
IA15
*
IA14 * A13 ;coprocessor id
=
$1
*
lAS
;qualified by address strobe low
+
FC2 * FC1 * FCO
*
IA19
*
IA18 * A17
*
IA16
;coprocessor access
=
$2
*
IA15
*
IA14 * A13
;coprocessor id
=
$1
*/ClKD
;qualified by ClKD (delayed ClK)
ClKD
=
ClK
Description: There are three terms to the CS generation. The first term denotes the earliest time
CS can be asserted. The second term is used to assert CS until the end of the FPCP access. The
third term is to ensure that no race condition 'occurs in case of a late AS.
Figure
12-4.
PAL Equations
12-8
MC68030 USER'S MANUAL
MOTOROLA