Motorola MC68030 User Manual page 150

-
6-12
$00 $04 $08 SOC
TAG VO-V3
I
bO
I
b I
I
b21 b31
I I II I I I I I I I I I I I
CYCLE SIZE ADDRESS COMMENT
BYTE
$03
E8
- INCLUDES THE REQUESTED OPERAND AND THE PREVIOUS BYTE
WORD $00
EB
- THE REMAINING WORD FOR THE LONG WORD CACHE ENTRY
Figure 6-6. Single Entry Mode Operation - 16-Bit Port
With a 32-bit port, the same operation is shown in Figure 6-7. Only one read
cycle is required. All four bytes (including the requested byte) are latched
during the cycle.
$00 $04 $08 SOC
TAG VO-V3
I
bO
I
bl
I
b21 b31
I I I I
I
I I I I
I
I I I I
I
CYCLE SIZE ADDRESS COMMENT
BYTE $03
I
bO
I
bl
I
b2
B
- THE ENTIRE LONG WORO MUST BE VALID
Figure 6-7. Single Entry Mode Operation - 32-Bit Port
If a requested access is misaligned and spans two cache entries, the bus
controller attempts to fill both associated long-word cache entries. An ex-
ample ofthis is an operand request for a long word on an odd-word boundary.
The MC68030 first fetches the initial byte(s) of the operand (residing in the
first long word) and then requests the remaining bytes to fill that cache entry
(if the port size is less than 32 bits) before it requests the remainder of the
operand and corresponding long word to fill the second cache entry. If the
port size is 32 bits, the processor performs two accesses, one for each cache
entry.
MC68030 USER'S MANUAL MOTOROLA