Motorola MC68030 User Manual page 258

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EXTERNAL WRITE
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WRITE TO D. CACHE
MOVE.L DO.IAOI
D. CACHE READ
MOVE.L IAOI.D1
NOP PREVENTS EXECUTION OF SUBSEQUENT
INSTRUCTIONS UNTIL MOVE.L DO.IAOI
WRITE CYCLE COMPLETES
Figure 7-58. Bus Synchronization Example
7.7 BUS ARBITRATION
7-96
The bus design of..the MC68030 provides for a' single bus master at anyone
time: either the processor or an external device. One or more of the external
devices on the bus can have the capability of becoming bus master. Bus
arbitration is the protocol by which an external device becomes bus master;
the bus controller in the MC68030 manages the bus arbitration signals so
that the processor has the lowest priority. External devices that need to obtain
the bus must assert the bus arbitration signals in the sequences described
in the following paragraphs. Systems having several devices that can become
bus master require external circuitry to assign priorities to the device so that,
when two or more
ext~rnal
devices attempt to become bus master at the
same time, the one having the highest priority becomes bus master first. The
sequence of the protocol is:
1. An external device asserts the bus request signal.
2. The processor asserts the bus grant signal to indicate that the bus will
become available at the end of the current bus cycle.
3. The external device asserts the bus grant acknowledge signal to indicate
that it has assumed bus mastership.
BR may be issued any time during a .. bus cycle or between cycles. BG is
asserted in response to BR; it is usually asserted as soon as BR has been
synchronized and recognized, except when the MC68030 has made an in-
ternal decision to execute a bus cycle. Then, the assertion of BG is deferred
until the bus cycle has begun. Additiona.lly, BG is not asserted until the end
of a read-modify-write operation (when RMC is negated) in response to a BR
MC68030 USER'S MANUAL
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