Motorola MC68030 User Manual page 152

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6-14
The next example, shown in Figure 6-9, is a read of a misaligned long-word
operand from devices that return 16-bit DSACKx encodings. The processor
accepts the first portion of the operand, the word from address $06, and
requests a word from address $04 to fill the cache entry. Next, the processor
reads the word at address $08, the second portion of the operand, and stores
it in the cache also. Finally, the processor accesses the word at $OA to fill
the second long-word cache entry.
$00 $04 $08 $OC
TAG VO·V3
I I I I I I I
b41 bsl b61 b71
I
~81
bsl bA
I
bB
I I I I I I
CYCLE SIZE ADDRESS
COMMENT
1 LONG WORD $06
WORD
$04
WORD $08
WORD $OA
EB
OJ
- FIRST WORD OF OPERAND LATCHED
~
- TO FILL THE CACHE ENTRY AT $04
EB
- SECOND WORD OF OPERAND
~
- TO FILL ENTRY AT $08
Figure 6-9. Single Entry Mode Operation -
Misaligned Long Word and 16-Bit Port
Two read cycles are required for a misaligned long-word operand transfer
from devices that return 32-bit DSACKx encodings. As shown in Figure 6-10,
the first read cycle requests the long word at address $06 and latches the
long word at address $04. The second read cycle requests and latches the
long word corresponding to the second cache entry at address $08. Two read
cycles are also required if STERM is used to indicate a 32-bit port instead of
the 32-bit DSACKx encoding.
MC68030 USER'S MANUAL
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