Motorola MC68030 User Manual page 224

7-62
PROCESSOR
EXTERNAL DEVICE
ADDRESS DEVICE
1) ASSERT ECS/DCS FOR ONE-HALF CLOCK
2) SET R/W TO READ
3) DRIVE ADDRESS ON AO-A31
4) DRIVE FUNCTION CODE ON FCO-FC2
5) DRIVE SIZE (SIZO-SIZI) (FOUR BYTES)
6) CACHE INHIBIT OUT (ClOUT) BECOMES VALID
7) ASSERT ADDRESS STROBE (As)
8) ASSERT CACHE BURST REOUEST (CBREQ)
9) ASSERT DATA STROBE
(DS)
10) ASSERT DATA BUFFER ENABLE (DBEN)
- .
PRESENT DATA
04-
I) DECODE ADDRESS
2) PLACE DATA ON DO-D31
3) ASSERT SYNCHRONOUS TERMINATION (STERM)
ACQUIRE DATA
..--
4) ASSERT CACHE BURST ACKNOWLEDGE (CBACK)
I) SAMPLE CACHE INHIBIT IN (CIIN)
AND CACHE BURST ACKNOWLEDGE (CBACK)
2) LATCH DATA ------+
TERMINATE CYCLE
I) REMOVE DATA FROM DO-D31
2) NEGATE STERM (IF NECESSARY)
3) NEGATE CBACK (IF NECESSARY)
WHEN 4 LONG WORDS TRANSFERRED
I I
UNTIl 4 LONG WORDS TRANSFERRED
END OF BURST
I) NEGATE
AS
AND
OS
2) NEGATE DBEN
+
START NEXT CYCLE
Figure 7-37. Burst Operation Flowchart - Four Long Words Transferred
State 2
The selected device uses R/W, 5IZ0-5IZ1, AO-A 1, and ClOUT to place the
data on the data bus. (The first cycle must supply the long word at the
corresponding long-word boundary.) All of the byte sections (024-031,
016-023, 08-015, and 00-07) of the data bus must be driven since the
burst operation latches 32 bits on every cycle. During 52, the processor
drives OBEN active to enable external data buffers. In systems that use
two-clock synchronous bus cycles, the timing of OBEN may prevent its
use. At the beginning of 52, the processor tests the level of 5TERM. If
5TERM is recognized, the processor latches the incoming data at the end
of 52. For the burst operation to proceed, CBACK must be asserted when
5TERM is recognized. If the data for the current cycle is not to be cached,
CIIN must be asserted at the same time as 5TERM. The assertion of CIIN
also has the effect of aborting the burst operation.
MC68030 USER'S MANUAL
MOTOROLA