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3.2.9 System Control Instructions
3-12
Privileged instructions, trapping instructions, and instructions that use or
modify the condition code register (CCR) provide system control operations.
Table 3-9 summarizes these instructions. The TRAPcc instruction uses the
same conditional tests as the corresponding program control instructions.
All of these instructions cause the processor to flush the instruction pipe.
Table 3-9. System Control Operations
Instruction
Operand Syntax
Operand Size
Operation
Privileged
ANDI
#<data>,SR
16
immediate data A SR • SR
EORI
#<data>,SR
16
immediate data EB SR • SR
MOVE
<ea>,SR
16
source. SR
SR,<ea>
16
SR • destination
MOVE
USP,An
32
USP. An
An,USP
32
An
it
USP
MOVEC
RC,Rn
32
Rc. Rn
Rn,Rc
32
Rn • Rc
MOVES
Rn,<ea>
8,16,32
Rn • destination using DFC
<ea>,Rn
source using SFC • Rn
ORI
#<data>,SR
16
immediate data V SR • SR
RESET
none
none
assert RESET line
RTE
none
none
(SP). SR; SP+2. SP; (SP). PC; SP+4. SP;
Restore stack according to format
STOP
#<data>
16
immediate data. SR; STOP
Trap Generating
BKPT
#<data>
none
run breakpoint cycle, then trap as illegal instruction
CHK
<ea>,Dn
16,32
if Dn<O or Dn>(ea), then CHK exception
CHK2
<ea>,Rn
8,16,32
if Rn<lower bound or Rn>upper bound, the CHK
exception
ILLEGAL
none
none
SSP - 2. SSP; Vector Offset. (SSP);
SSP -4. SSP; PC. (SSP);
SSP -2. SSP; SR. (SSP);
Illegal Instruction Vector Address. PC
TRAP
#<data>
none
SSP - 2 • SSP; Format and Vector Offset. (SSP)
SSP -4. SSP; PC. (SSP); SSP -2. SSP;
SR. (SSP); Vector Address. PC
TRAPcc
none
none
if cc true, then TRAP exception
#<data>
16,32
TRAPV
none
none
if V then take overflow TRAP exception
Condition Code Register
ANDI
#<data>,CCR
8
immediate data A CCR • CCR
EORI
#<data>,CCR
8
immediate data EB CCR • CCR
MOVE
<ea>,CCR
16
source. CCR
CCR,<ea>
16
CCR • destination
ORI
#<data>,CCR
8
immediate data V CCR • CCR
MC68030 USER'S MANUAL
MOTOROLA
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