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III
11.6.13 Bit Manipulation Instructions
11-46
The bit manipulation instruction table indicates the number of clock periods
needed for the processor to perform the specified bit operation on the given
addressing mode. Footnotes indicate when it is necessary to account for the
appropriate effective address time. For instruction-cache case and for no-
cache case, the total number of clock cycles is outside the parentheses. The
number of read, prefetch, and write cycles is given inside the parentheses
as (r/p/w). The read, prefetch, and write cycles are included in the total clock
cycle number.
All timing data assumes two-clock reads and writes.
Instruction
Head
Tail
I-Cache Case
No-Cache Case
BTST
#(data),Dn
4
0
4(01010)
4(0/1/0)
BTST
On,On
4
0
4(01010)
4(0/1/0)
#
BTST
#(data),Mem
0
0
4(01010)
4(0/1/0)
*
BTST
On,Mem
0
0
4(01010)
4(0/1/0)
BCHG
#(data),Dn
6
0
6(01010)
6(0/1/0)
BCHG
On,On
6
0
6(01010)
6(0/1/0)
#
BCHG
#(data),Mem
0
0
6(010/1)
6(0/1/1)
*
BCHG
On,Mem
0
0
6(010/1)
6(01111 )
BClR
#(data),On
6
0
6(01010)
6(0/1/0)
BClR
On,On
6
0
6(01010)
6(0/1/0)
#
BClR
#(data),Mem
0
0
6(010/1)
6(0/1/1)
*
BClR
On,Mem
0
0
6(010/1)
6(0/1/1)
BSET
#(data),On
6
0
6(01010)
6(01110)
BSET
On,On
6
0
6(01010)
6(0/1/0)
#
BSET
#(data),Mem
0
0
6(010/1)
6(0/1/1)
*
BSET
On,Mem
0
0
6(010/1)
6(01111 )
*Add Fetch Effective Address Time
#Add Fetch Immediate Effective Address Time
MC68030 USER'S MANUAL
MOTOROLA
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