Motorola MC68030 User Manual page 283

The peripheral device uses the active-low interrupt priority level signals
(lPLO-IPL2) to signal an interrupt condition to the processor and to specify
the priority of that condition. The three signals encode a value of zero through
seven (IPLO is the least significant bit). High levels on all three signals cor-
respond to no interrupt requested (level 0) and low levels on IPLO-IPL2 cor-
respond to interrupt request level
7.
Values
1-7
specify one of seven levels
of prioritized interrupts; level seven has the highest priority. External circuitry
can chain or otherwise merge signals from devices at each level, allowing
an unlimited number of devices to interrupt the processor.
The IPLO-IPL2 interrupt signals must maintain the interrupt request level until
the MC68030 acknowledges the interrupt to guarantee that the interrupt is
recognized. The MC68030 continuously samples the IPLO-IPL2 signals on
consecutive falling edges of the processor clock to synchronize and debounce
these signals. An interrupt request that is the same for two consecutive falling
clock edges is considered a valid input. Although the protocol requires that
the request remain until the processor runs an interrupt acknowledge cycle
for that interrupt value, an interrupt request that is held for as short a period
as two clock cycles could be recognized.
The status register of the MC68030 contains an interrupt priority mask (12,
11, 10, bits 10-8). The value in the interrupt mask is the highest priority level
that the processor ignores. When an interrupt request has a priority higher
than the value in the mask, the processor makes the request a pending
interrupt. Figure 8-2 is a flowchart of the procedure for making an interrupt
pending.
MOTOROLA
OTHERWISE
(COMPARE INTERRUPT LEVEL
WITH STATUS REGISTER MASKl
Figure 8-2. Interrupt Pending Procedure
MC68030 USER'S MANUAL 8-15