Motorola MC68030 User Manual page 560

12-34
r------------------------.
FC2 - - " " , - _
FC1 - - - I
FCO
-----r----
I
I
I
I
I
I
ClOUT
- - - - - - - - - 1
R/W
--------~
n--.,..I__.--
STERM
I
CACHE HIT
(ACTIVE HIGH)
PR
Q
CLK
' I T
I
I
I
I
I
I
I
I
I
I
0
1
L ______________________ :.J
AS
- - - . . - - - - - - f
CACHE HIT
(ACTIVE HIGH)
- - - - - - - - - - - - - - 0
r---------,
(0
L ________
~
Figure 12-18. Example Early Termination Control Circuit
cycles with ClOUT asserted, and all cycles that missed in the cache on the
previous cycle and were not accesses to noncachable locations. The flip-flop
in (C) latches the termination condition of the current bus cycle at the rising
edge of AS, and this status is used during the next cycle. Other conditions
to suppress early termination may be included as required by a particular
system, but propagation delays must be carefully considered in order that
the output of (C) be valid before the rising edge of state S1 (see Equation
12-3 of Table 12-2).
The late termination circuit is formed by the gates (D) and (E). If the current
cyCle is accessing a cachable location, as determined by the output of (C),
and a cache hit has not occurred (D), then the BERR and HALT signals are
driven low (E).
Note that the logic depicted in Figure 12-18 is designed to support a cache
operating with no wait states. A provision for generating wait states may be
included by placing additional timing stages between (C) and the MC68030
to delay propagation of this output by the required number of clock periods.
MC68030 USER'S MANUAL MOTOROLA