Motorola MC68030 User Manual page 156

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6-18
The MC68030 does not assert CBREO during the first portion of a misaligned
access if the remainder of the access does not correspond to the same cache
line. Figure 6-13 shows an example in which the first portion of a misaligned
access is at address $OF. With a 32-bit port, the first access corresponds to
the cache entry at address SOC, which is filled using a single-entry load
operation. The second access, at address $10 corresponding to the second
ca'che line, requests a burst fill and the processor asserts CBREO. During this
burst operation, long words $10, $14, $18, and $1 C are all filled in that order.
$00 $04
$08 $OC
TAG VO·V3
I I I I I I I I I I I I I I I I I
bC
I
bD
I
bE
G
$10
$14
$18
I I
FIRST LONG WORD CACHED •
NO BURST REQUEST
$1C
TAG VO·V3
I I I I I I I I I I I I I I I
SECOND CYCLE·
BURST REQUESTED
THE REMAINING CACHE ENTRIES FOR SECONO BLOCK ARE BURSTED
Figure 6-13. Deferred Burst Filling Example
The processor does not assert CBREO if any ofthe following conditions exist:
• The appropriate cache is not enabled
• Burst filling for the cache is not enabled
• The cache freeze bit for the appropriate cache is set
• The current operation is the read portion of a read-modify-write oper-
ation
• The MMU has inhibited caching for the current page
• The cycle is for the first access of an operand that spans two cache lines
(crosses a modulo 16 boundary)
Additionally, the assertion of CIIN and BERR and the premature negation of
CBACK affect burst operation as described in the following paragraphs.
MC68030 USER'S MANUAL
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