Motorola MC68030 User Manual page 286

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8-18
iPls
SYNCHRONIZED
COMPARE REOUEST
WITH MASK IN SR
ASSERT IPEND
Figure 8-4. Assertion of IPEND
The state of the IPEND signal is internally checked by the processor once per
instruction, independently of bus operation. In addition, it is checked during
the second instruction prefetch associated with exception processing. Figure
8-5 is a flowchart of the interrupt recognition and associated exception pro-
cessing sequence.
To predict the instruction boundary during which a pending interrupt is pro-
cessed, the timing relationship between the assertion of IPEND for that in-
terrupt and the assertion of STATUS must be examined. Figure 8-6 shows
two examples of interrupt recognition. The first assertion of STATUS after
IPEND is denoted as STATO. The next assertion of STATUS is denoted as
STAT1.lf STATO begins on the falling edge of the clock immediately following
the clock edge that caused IPEND to assert (as shown in example 1), STAT1
is at least two clocks long, and, when there are no other pending exceptions,
the interrupt is acknowledged at the boundary defined by STAT1. If IPEND
is asserted with more setup time to STATO, the interrupt may be acknowl-
edged at the boundary defined by STATO (as shown in example 2). In that
case, STATO is asserted for two clocks, signaling this condition.
If no higher priority interrupt has been synchronized, the IPEND signal is
negated during state 0 (SO) of an interrupt acknowledge cycle (refer to 7.4.1.1
INTERRUPT ACKNOWLEDGE CYCLE - TERMINATED NORMALLY), and the
IPLx signals for the interrupt being acknowledged can be negated at this
time.
MC68030 USER'S MANUAL
MOTOROLA