Motorola MC68030 User Manual page 596

a
Timing (Continued)
Write Cycle, Wait States, ClOUT Asserted, 7-53
Table Search, 11-39
Write, Long-Word, 7-12
Write, Word, 7-14
Timing Table,
Arithmetic/Logical Instruction, 11-40
Immediate, 11-42
Binary Coded Decimal Instruction, 11-43
Bit Field Instruction, 11-47
Bit Manipulation Instruction, 11-46
Calculate Effective Address, 11-30
Calculate Immediate Effective Address, 11-32
Conditional Branch Instruction, 11-48
Control Instruction, 11-49
Exception Related
Instruction, 11-50
Operation, 11-50
Extended Instruction, 11-43
Fetch Effective Address, 11-26
Fetch Immediate Effective Address, 11-28
Jump Effective Address, 11-35
MMU
Effective Address, 11-58
Instruction, 11-60
MOVE Instruction, 11-37
Special Pu rpose, 11-39
Restore Operation, 11-51
Save Operation, 11-51
Shift/Rotate Instruction, 11-45
Single Operand Instruction, 11-44
Table Search, 11-51
Trace Exception, 8-12,10-70
Signals, 12-38
Tradeoffs, Performance,11-1
Transfer,
Long Word to Long Word, Misaligned Cachable,
7-20
Long Word to Word, 7-11
Misaligned
Cachable Word to Long Word, 7-17
Cachable Word to Word, 7-20
Long Word to Long Word, 7-20
Long Word to Word, 7-17
Word to Word, 7-17
Word to Word, Timing, 7-18
Word to Byte, 7-13
Transfer Main Processor Control Register Primitive,
10-50
Transfer Multiple Coprocessor Registers Primitive,
10-52
Transfer Multiple Main Processor Registers
Primitive, 10-52
Transfer Operation Word Primitive, 10-40
Transfer Single Main Processor Register Primitive,
10-50
Transfer Size Signals, 5-4, 7-4, 7-8, 7-9-7-14, 7-22ff
Transfer Status Register and Scan PC Primitive,
10-55
Transfer to/from Top of Stack Primitive, 10-49
Translation, Address, 9-13
Translation Control Register, 1-9, 2-5, "9-8, 9-54
Translation Table Descriptors, 9-10, 9-20
Translation Table Tree, 9-5,9-7,9-8,9-12,9-30,
9-47,9-48,9-65
Translation Tree, Supervisor, 9-48
Protection Example, 9-50
Transparent Translation Registers, 1-9, 2-5, 9-16,
9-55
Tree, Translation Table, 9-5, 9-7,9-8,9-12,9-30,
9-47,9-48,9-65
TTO, 1-9,2-5,9-16,9-57
TT1, 1-9, 2-5, 9-16, 9-57
Two Clock Synchronous Static RAM, 12-18-12-20
Types,
Address Space, 4-3
Data, 1-10
-U-
Unimplemented Instruction Exception, 8-9
Unit,
Execution, 6-16
Memory Management, 1-15, 7-3, 7-36, 7-43, 9-1;
11-5,12-4
Units, Floating Point, 12-5
Unused Descriptor Bits, 9-71
User Privilege Level, 4-2, 4-4
User Program Stack, 2-38
-v-
Valid Format Word, 10-24
Vallocate Routine, 9-78
VBR, 1-8, 2-5
VCC Pin Assignments, 12-46
Vector
Base Register, 1-8,2-5
Numbers, Exception, 8-1
Vectors, Exception, 4-6
Virtual Machine, 1-12
Virtual Memory, 1-12,9-77
WA Bit, 6-21
Wait States, 11-18
Window,
-w-
Asynchronous Sample, 7-3
Word, Special Status, 8-28
Word Read Cycle, Asynchronous, 32-Bit Port,
Timing, 7-33
Word to Byte Transfer, 7-13
Word to Long-Word Transfer, Misaligned, 7-17
Word to Word Transfer, Misaligned Cachable, 7-20
INDEX-12
MC68030 USER'S MANUAL
MOTOROLA