Motorola MC68030 User Manual page 243

Case
No.
1
2
3
4
5
6
LEGEND:
N -
A -
NA-
X
S
Table 7-9. STERM, BERR, and HALT Assertion Results
Asserted on Rising
Control Edge of State
Result
Signal
N N+2
STERM A
-
Normal cycle terminate and continue.
BERR NA
-
HALT NA
-
STERM NA A
Normal cycle terminate and halt. Continue when HALT
BERR
NA
NA negated.
HALT
A/S
S
STERM NA A Terminate and take bus error exception, possibly
BERR AlS S deferred.
HALT NA NA
STERM A
-
Terminate and take bus error exception, possibly
BERR
A
-
deferred.
HALT NA
-
STERM NA A Terminate and retry when HALT negated.
BERR A S
HALT AlS S
STERM A
-
Terminate and retry when HALT negated .
BERR A
-
HALT A
-
The number of current even bus state (e.g., S2, S4, etc.)
Signal is asserted in this bus state
Signal is not asserted in this state
Don't care
Signal was asserted in previous state and remains asserted in this state
State N
+
2 not part of bus cycle
EXAMPLE A:
MOTOROLA
A system uses a watchdog timer to terminate accesses to an unpopulated
address space. The timer asserts BERR after timeout (case 3),
MC68030 USER'S MANUAL
7-81
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