Motorola MC68030 User Manual page 537

Table 12-1. Data Bus Activity for Byte, Word, and Long-Word Ports
Data Bus Active Sections
Transfer
SlZ1 SIZO A1 AO
Byte (B) - Word (W) - Long-Word (L) Ports
Size
031-024 023-016 015-08
07-00
0 1 0 0 BWL
- -
-
Byte
0
1
0
1
B
WL
-
-
0 1 1 0 BW
-
L
-
0 1 1 1
B W
-
L
1 0 0 0 BWL
WL
- -
Word
1 0 0 1 B WL L
-
1 0 1 0 BW W L L
1 0 1 1 B W
-
L
1 1 0 0 BWL WL L
-
Three Byte
1 1
0
1
B
WL L L
1 1 1 0 BW W L L
1 1 1 1 B W
-
L
0 0 0 0
BWL WL L L
Long Word
0 0 0 1 B WL L
L
0 0
1
0 BW
W L L
0 0 1 1 B W
-
L
The PAL equations and circuits presented here are not intended to be the
optimal implementation for every system. Depending on the CPU's clock
frequency, memory access times, and system architecture, different circuits
may be required.
12.4 MEMORY INTERFACE
The MC68030 is capable of running three types of external bus cycles as
determined by the cycle termination and handshake signals (refer to SECTION
7 BUS OPERATION). These three types of bus cycles are:
1. Asynchronous cycles, terminated by the DSACKx signals, have a min-
imum duration of three processor clock periods in which up to four
bytes are transferred.
2. Synchronous cycles, terminated by the STERM signal, have a minimum
duration of two processor clock periods in which up to four bytes are
transferred.
3. Burst operation cycles, terminated by the STERM and CBACK signals,
have a duration of as little as five processor clock periods in which up
to four long words (16 bytes) are transferred.
MOTOROLA MC68030 USER'S MANUAL
12-11
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