Motorola MC68030 User Manual page 267

ClK
PLUS 5 _ _
-----------L==~==:~
VOLTS -
J
Vcc
~
1= >520
ClOCKS~
--,
1<4ClOCKS-.J _
Ir--------
RESET
I
~
r--
4 CLOCKS
---1
BUS CYCLES
XXXXXXXXXXXXXXXXXXXXXXXXXXXX~ I
ALL CONTROL SIGNALS
~c
I
ENTIRE BUS NEGATEO, DATA BUS IN ISP
HIGH IMPEDANCE READ MODE, ADDRESS READ
BUS DRIVEN STARTS
XXXxx
BUS STATE UNKNOWN
Figure 7-64. Initial Reset Operation Timing
Resetting the processor causes any bus cycle in progress to terminate as if
DSACKx, BERR, or STERM had been asserted. In addition, the processor
initializes registers appropriately for a reset exception. Exception processing
for a reset operation is described in 8.1.1 Reset Exception.
When a reset instruction is executed, the processor drives the RESET signal
for 512 clock cycles. In this case, the processor resets the external devices
of the system, and the internal registers of the processor are unaffected. The
external devices connected to the RESET signal are reset at the completion
of the reset instruction. An external RESET signal that is asserted to the
processor during execution of a reset instruction must extend beyond the
reset period of the instruction by at least eight clock cycles to reset the
processor. Figure 7-65 shows the timing information for the reset instruction.
MOTOROLA
MC68030 USER'S MANUAL
7-105