Motorola MC68030 User Manual page 546

12-20
when the appropriate byte (or bytes) is being written to as indicated by the
SIZO, SIZ1 ,AO, and A 1 signals. The four signals, UUCS, UMCS, LMCS, and
LLCS, control data bits 024-031, 016-023, OS-015, and 00-07, respectively.
AS is used to qualify the byte select signals to avoid spurious writes to
memory before the address is valid. Ouring read operations, the read chip
select (ROCS) signal, qualified with AS, controls the data buffers only (since
the .memory is already enabled with its
E
input grounded). The last signal
generated by the PAL is the TERM signal. As its equation shows, TERM
consists of two events: one for read cycles and the other for write cycles.
For read cycles; TERM is an address decode signal that is asserted whenever
the address corresponds to the encoded memory-mapped bank of SRAM.
For write operations, a delayed form of AS (OAS) is used to qualify the same
address decode, which lengthens write operations to three clock cycles. The
DAS signal generation is delayed from the clock edge by running the clock
signal through two 74F32 OR gates before connecting to the 74F74 D-type
flip-flop. This guarantees that the maximum propagation delay to generate
the TERM signal does not violate the synchronous input hold time of the
MC6S030. By increasing write operation to three clock cycles, the MC6S030
can easily meet the specified data setup time to the SRAMs before the ne-
gation of the write strobes (W). TERM is then connected to the system's
STERM consolidation circuity. The consolidation circuitry should have no
more than 15 ns of propagation delay. Ifthe system has no other synchronous
memory or ports, TERM may be connected directly to STERM.
UUCS=/AO * IAl B IRW */A1S*/A17*/A1B*A30*
UMCS=AO * IAl * IRW * IA1S*/A17*/A1B*A30*
+/Al * ISllO * IRW * IA1S*/A17*/A1B*A30*
+/Al *Slll * IRW * IA1S*/A17*/A1B*A30*
LMCS=/AO *Al * IRW * IAl 6*/A 17*/A 1 B*A30*
+/Al * ISllO * ISlll * IRW * IA1S*/A17*/A1B*A30*
+/Al * SilO * Sill * IRW * IA1S*/A17*/A1B*A30*
+/Al * AD * ISllO * IRW * IA1S*/A17*/A1B*A30*
LLCS=AO * Al IRW * IA1S*/A17*/A1B*A30*
+AO * SilO *Slll * IRW * IA16*/A17*/A1B*A30*
+/SllO * ISlll * IRW * IA1S*/A17*/A1B*A30*
+Al * Sill * IRW * IA16*/A17*/A1B*A30*
RDCS=/A1S*/A17*/A1B*A30*RW
+/A15 * IA17 * IA1B*A30* IRW*DAS
;directly addressed, any size
; directly addressed, any size
;word aligned, size byte or three byte
;word aligned, size is word or long word
;directly addressed, any size
;word aligned, size is long word
;word aligned, size is three byte
;word aligned, size is word or long word
;directly addressed, any size
;odd alignment, three byte size
;size is long word, any address
;word aligned, word or three byte size
;immediate STERM with proper address
;write cycles take three clocks
DESCRIPTION: Byte select signals. The byte select signals are asserted only during write operations when the particular byte is
being written. The synchronous bank of memory is always enabled, and writes are controlled by
W
on the memory.
RDCS is for buffer control and only asserts for read operations. TERM is the cycle termination signals to the MCSB030.
Figure 12-10. Example PAL Equations for Two-Clock Memory Bank
MC68030 USER'S MANUAL MOTOROLA