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a
Signal (Continued)
AVEC, 5-8, 7-6, 7-29, 7-71ff
BERR, 5-9, 6-19, 7-6, 7-27ff, 8-7, 8-22, 8-26
BG, 5-9, 7-43, 7-96ff
BGACK, 5-9, 7-97ff
BR, 5-8, 7-43, 7-60, 7-96ff
Bus Error, 5-9, 6-11, 7-6, 7-27ff, 8-7, 8-22, 8-26
Bus Grant, 5-9, 7-43, 7-96ff
Bus Grant Acknowledge, 5-9, 7-97ff
Bus Request, 5-8, 7-43, 7-60, 7-96ff
Cache Burst Acknowledge, 5-7, 6-16, 7-6, 7-30ff
Cache Burst Request, 5-7,6-16-6-20, 7-6, 7-30,
7-48ff
Cache Disable, 5-10, 6-3
Cache Inhibit Input, 5-7, 6-3, 6-9-6-19, 7-3, 7-30ff
Cache Inhibit Output, 5-7, 6-3, 6-9, 7-30ff, 9-1,
9-13
CBACK, 5-7, 6-16-6-19, 7-6, 7-30ff,
CBREQ, 5-7, 6-16-6-19, 7-6, 7-30, 7-48
CDIS, 5-10, 6-3
CIIN, 5-7, 6-3, 6-9-6-11, 6-15,7-3, 7-26ff
ClOUT, 5-7, 6-3, 6-9, 7-30ff, 9-1, 9-17
ClK, 5-11, 7-54
Clock, 5-11, 7-54
Coprocessor, Chip Select,
Data Buffer Enable, 5-6, 7-5, 7-51ff
Data Strobe, 5-6, 7-5, 7-27ff,
DBEN, 5-6, 7-5, 7-31
DS, 5-6, 7-5, 7-27ff
DSACKO, 5-6, 6-11, 6-14, 7-5, 7-6, 7-26ff
DSACK1, 5-6, 6-11, 6-14, 7-5, 7-6, 7-26ff
ECS, 5-5, 7-4, 7-26ff
External Cycle Start, 5-5, 7-4, 7-26ff
Halt, 5-9, 7-6, 7-27ff
HALT, 5-9, 7-6, 7-27ff
Internal Microsequencer Status, 5-10, 7-94, 8-3,
8-17,8-26
Interrupt Pending, 5-8, 8-17, 8-18
IPEND, 5-8, 8-17, 8-18
MMU Disable, 5-4, 9-1, 9-2, 9-11
MMUDIS, 5-10, 9-2, 9-11
OCS, 5-5, 7-4, 7-31ff
Operand Cycle Start, 5-5, 7-4, 7-31ff
Pi~line
Refill, 5-10, 6-5
RIW, 5-5, 7-4, 7-36ff
Read-Modify-Write, 5-5, 7-4, 7-36ff
Read/Write, 5-5, 7-4, 7-36ff
REFill, 5-10, 6-5
Reset, 5-9, 7-97ff, 9-15, 9-61, 12-31
RESET, 5-9, 7-97ff, 9-15, 9-61, 12-31
RMC, 5-5, 7-4, 7-36ff, 12-3
SilO, 5-4, 7-4, 7-8, 7-9, 7-14, 7-22ff
Sill, 5-4, 7-4, 7-8, 7-9, 7-14, 7-22ff
STATUS, 5-10, 7-94, 8-4,8-7,8-8
STERM, 5-6, 6-14, 6-16, 7-3, 7-6, 7-26ff
Synchronous Termination, 5-6, 6-16, 7-3, 7-6,
7-26ff,
Signal Assertion Results, Asynchronous Cycle,
7-78,7-79
Signal Groups, 5-1
Signal Index, 5-2
Signal Routing, Adapter Board, 12-1
Signal Summary, 5-12
Signals,
AO-A 1, 7-8, 7-9, 7-22ff
AO-A31, 5-4, 7-4, 7-31ff
Bus Control, 7-3
Bus Transfer, 7-1
Data Bus Write Enable, 7-23
Data Transfer and Size Acknowledge, 5-6, 6-11,
6-14, 7-5, 7-6, 7-26ff
DO-D31, 5-4, 7-5, 7-30
FCO-FC2, 5-4, 6-6, 7-4, 7-31ff
Function Code, 5-4, 6-6, 7-4, 7-31ff
Instruction Boundary, 12-37
Interrupt Exception, 12-38
Interr!!2!Jriority level, 5-8, 7-69ff, 8-13
IPlO-IPl2, 5-8, 7-69ff, 8-13
MC68851,12-5
Other Exception, 12-38
Processor Halted, 12-39
Trace Exception, 12-38
Transfer Size, 5-4, 7-4, 7-8, 7-9, 7-22ff
Single Entry Cache Filling, 6-10
Single Operand Instruction Timing Table, 11-44
Size Restrictions, Table Index, 9-10
Size Signal Encoding, 7-8
Sizing, Dynamic Bus, 7-6, 7-19, 7-24
SilO Signal, 5-4, 7-4, 7-8, 7-9-7-14, 7-22ff
Sill Signal, 5-4, 7-4, 7-8, 7-9-7-14, 7-22ff
Software Bus Fault Recovery, 8-27
Space, CPU, 7-68, 7-70, 10-5ff
Special Status Word, 8-28
Spurious Interrupt Cycle, 7-74
SR, 1-8,2-4,6-5,8-10,8-13,8-15
SRP, 1-5, 1-9,2-4,9-13,9-52,9-54,9-65
Stack,
System, 2-36
User Program, 2-38
Stack Frame,
Exception, 4-7, 8-32
Mid-Instruction, 10-59
Post-Instruction, 10-60
Pre-Instruction, 10-57
State,
Diagram, Bus Arbitration, 7-101
Exception Processing, 4-1
Halted, 4-1
Normal Processing, 4-1
State Frames, Coprocessor, 10-21
States, Wait, 11-18
Static RAM, 12-18-12-24
Burst Mode, 12-20-12-22
Pipelined Burst Mode, 12-22-12-24
Two Clock Synchronous, 12-18-12-19
Status Register, 1-8,2-4,6-5,8-10,8-13,8-16
Status Word, Special, 8-28
STATUS Signal, 5-10, 7-94, 8-4, 8-7, 8-8
INDEX-10
MC68030 USER'S MANUAL
MOTOROLA
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