Motorola MC68030 User Manual page 209

State 6
The processor asserts ECS and OCS in S6 to indicate that another external
cycle is beginning. The processor drives
R/W
low for a write cycle. ClOUT
also becomes valid, indicating the state of the MMU CI bit in the address
translation descriptor or in a relevant TTx register. Oepending on the write
operation to be performed, the address lines may change during S6.
State 7
In S7, the processor asserts AS, indicating that the address on the address
bus is valid. The processor also asserts OBEN, which can be used to enable
data buffers during S7. In addition, the ECS (and OCS, if asserted) signal
is negated during S7.
State 8
Ouring S8, the processor places the data to be written onto DO-031.
State 9
The processor asserts OS during S9 indicating that the data is stable on
the data bus. As long as at least one of the OSACKx signals is recognized
by the end of S8 (meeting the asynchronous input setup time requirement),
the cycle terminates one clock later. If OSACKx is not recognized by the
start of S9, the processor inserts wait states instead of proceeding to S10
and S11. To ensure that wait states are inserted, both OSACKO and OSACK1
must remain negated throughout the asynchronous input setup and hold
times around the end of S8. If wait states are added, the processor con-
tinues to sample OSACKx signals on the falling edges of the clock until
one is recognized.
The selected device uses
R/W,
OS, SIZO-SIZ1, and AO-A 1 to latch data from
the appropriate section(s) of the data bus (024-031, 016-023, 08-015,
and 00-07). SIZO-SIZ1 and
AO~A
1 select the data bus sections. If it has
not already done so, the device asserts OSACKx when it has successfully
stored the data.
State 10
The processor issues no new control signals during S10.
MOTOROLA MC68030 USER'S MANUAL 7-47