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11.6.14 Bit Field Manipulation Instructions
The bit field manipulation instruction table indicates the number of clock
periods needed for the processor to perform the specified bit field operation
using the given addressing mode. Footnotes indicate when it is necessary
to account for the appropriate effective address time. For instruction-cache
case and for no-cache case, the total number of clock cycles is outside the
parentheses. The number of read, prefetch, and write cycles is given inside
the parentheses as (r/p/w). The read, prefetch, and write cycles are included
in the total clock cycle number.
All timing data assumes two-clock reads and writes.
Instruction
Head
Tail
I-Cache Case
No-Cache Case
BFTST
On
8
0
8(01010)
8(0/1/0)
*
BFTST
Mem «5 Bytes)
6
0
10(110/0)
10(1/1/0)
*
BFTST
Mem (5 Bytes)
6
0
14(2/010)
14(2/1/0)
BFCHG
On
14
0
14(010/0)
14(0/1/0)
*
BFCHG
Mem «5 Bytes)
6
0
14(1/011 )
14(1/111 )
*
BFCHG
Mem (5 Bytes)
6
0
22(2/0/2)
22(2/1/2)
BFCLR
On
14
0
14(010/0)
14(0/1/0)
*
BFCLR
Mem «5 Bytes)
6
0
14(1/0/1)
14(1/1/1 )
*
BFCLR
Mem (5 Bytes)
6
0
22(2/0/2)
22(2/1/2)
BFSET
On
14
0
14(010/0)
14(0/1/0)
*
BFSET
Mem «5 Bytes)
6
0
14(1/0/1)
14(1/1/1)
*
BFSET
Mem (5 Bytes)
6
0
22(2/0/2)
22(2/1/2)
BFEXTS
On
10
0
10(010/0)
10(0/1/0)
*
BFEXTS
Mem «5 Bytes)
6
0
12(1/010)
12(1/1/0)
*
BFEXTS
Mem (5 Bytes)
6
0
18(2/010)
18(2/1/0)
BFEXTU
On
10
0
10(010/0)
10(0/1/0)
*
BFEXTU
Mem «5 Bytes)
6
0
12(1/010)
12(1/1/0)
*
BFEXTU
Mem (5 Bytes)
6
0
18(2/010)
18(2/1/0)
BFINS
On
12
0
12(010/0)
12(0/1/0)
*
BFINS
Mem «5 Bytes)
6
0
12(1/0/1)
12(11111 )
*
BFINS
Mem (5 Bytes)
6
0
18(2/0/2)
18(2/112)
BFFFO
On
20
0
20(01010)
20(01110)
*
BFFFO
Mem «5 Bytes)
6
0
22(11010)
22(1/1/0)
*
BFFFO
Mem (5 Bytes)
6
0
28(2/010)
28(2/1/0)
*Add Calculate Immediate Effective Address Time
NOTE:
A bit field of 32 bits may span 5 bytes that require two operand cycles to access or may span 4 bytes
that require only one operand cycle to access.
MOTOROLA
MC68030 USER'S MANUAL
11-47
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