Motorola MC68030 User Manual page 501

11.6.6 MOVE Instruction
The MOVE instruction timing table indicates the number of clock periods
needed for the processor to calculate the destination effective address and
perform the MOVE or MOVEA instruction, including the first level of indi-
rection on memory indirect addressing modes. The fetch effective address
table is needed on most MOVE operations (source, destination dependent).
The destination effective addresses are divided by their formats (refer to 2.5
Effective Address Encoding Summary). For instruction-cache case and for
no-cache case, the total number of clock cycles is outside the parentheses.
The number of read, prefetch, and write cycles is given inside the parentheses
as (r/p/w). The read, prefetch, and write cycles are included in the total clock
cycle number.
All timing data assumes two-clock reads and writes.
MOVE Source.Destination
SINGLE EFFECTIVE ADDRESS INSTRUCTION FORMAT
MOVE Rn. Dn 2 0 2(01010) 2(0/1/0)
MOVE Rn. An 2
0
2(01010) 2(0/1/0)
* MOVE EA.An 0 0 2(01010) 2(0/1/0)
*
MOVE EA.Dn
0 0
2(01010) 2(0/1/0)
MOVE Rn.(An)
0
1 3(010/1) 4(0/1/1)
*
MOVE SOURCE. (An) 2
0
4(010/1) 5(0/1/1)
MOVE Rn.(An) +
0 1 3(010/1) 4(0/1/1)
*
MOVE SOURCE. (An)
+
2
0
4(010/1) 5(0/1/1)
MOVE Rn.-(An)
0 2 4(010/1) 4(0/1/1)
*
MOVE SOURCE. - (An) 2
0
4(010/1) 5(0/1/1)
*
MOVE EA. (d16.An) 2
0
4(010/1)
5(0/1/1)
*
MOVE EA,XXX.W 2
0
4(010/1)
5(0/1/1)
*
MOVE EA.XXX.L 0 0 6(010/1) 7(0/2/1)
BRIEF FORMAT EXTENSION WORD
1*
MOVE EA, (de.An,Xn) 4
o
6(010/1) 7(0/1/1)
MOTOROLA MC68030 USER'S MANUAL
11-37
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