Motorola MC68030 User Manual page 247

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WRITE WITH BUS ERROR ASSERTED PROCESSING STACK WRITE
Figure 7-50. Late Bus Error with DSACKx
A bus error occurring during a burst fill operation is a special case. If a bus
error occurs during the first cycle of a burst, the data is ignored, the entire
cache line is marked invalid, and the burst operation is aborted. If the cycle
is for an instruction fetch, a bus error exception is made pending. This bus
error is processed only if the execution unit attempts to use either of the two
MOTOROLA MC68030 USER'S MANUAL 7-85