Motorola MC68030 User Manual page 371

entries maps a 16-Mbyte region of the virtual address space. The primary
advantage of a two-level table for large "number-crunching" system is the
operating system designer's ability to make a tradeoff between page size
and table size. The system designer may choose a smaller page size to fit
the block sizes on available liD devices, yet keep the tables manageable.
However, the designer must also consider the performance penalty associ-
ated with smaller page sizes. Systems with smaller page sizes have a higher
frequency of page faults requiring more table search time and paging liD.
With the flexibility of the MC68030 MMU, the designer has enough choices
to optimize table structure design and page size.
Three-level translation tables are useful when the operating system makes
heavy use of shared memory spaces andlor shared page tables. Sophisticated
systems often share translation tables or program and data areas defined at
the page table level. When a table entry can point to a translation table also
used by a different task, sharing memory areas becomes efficient. The direct
access to user address space by the supervisor is an example of sharing
memory.
Some artificial intelligence systems require very large virtual address spaces
with only small fragments of memory allocated among these widely differing
addresses. This fragmentation is due to the complex and recursive actions
the system performs on lists of data. These actions require the system to
constantly allocate and free sophisticated pointers and linked lists in the
memory map. The fragmentation suggests a small page size to utilize mem-
orymost efficiently. However, small pages in a large virtual memory map
require relatively large translation tables. For example, to map 4 Gbytes of
virtual address space with 256-byte pages, the page tables alone require 64
Mbytes. With a three- or four-level table structure, the number of actual
translation table entries can be drastically reduced. The designer can use
invalid descriptors to represent blocks of unused addresses and the limit
fields in valid descriptors to minimize the sizes of pointer and page tables.
In
addi~ion,
paging of the address tables themselves reduces memory re-
quirements.
9.9.3.2 INITIAL SHIFT COUNT. The initial shift field (IS) of the translation control
register (TC) can decrease the size of translation tables. When the required
virtual address space can be addressed with fewer than 32 bits, the IS field
reduces the size of the virtual address space by discarding the appropriate
number of the most significant logical address bits. This technique inhibits
MOTOROLA
MC68030 USER'S
MANUAL 9-69
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