Figure 5.5B Timebase Timer Operation - Fujitsu F2MC-8L MB89620 Series Hardware Manual

n Timebase Timer Operation
The state of following operations are shown in figure 5.5b.
• A power-on reset occurs.
• Changes to sleep mode during operation of the interval timer function.
• Changes to stop mode.
• A counter clear request occurs.
The timebase timer is cleared by changing to stop mode, and stops operation. The timebase
timer counts the oscillation stabilization delay time after wake-up from stop mode.
Oscillation stabilization
delay overflow
For the case when the interval time selection bits in the timebase timer control register (TBTC: TBC1, TBC0) are set to "11" (2
MB89620 series
Counter value
FFFFF
H
0000
H
CPU operation starts
Power-on reset
(optional)
TBOF bit
TBIE bit
SLP bit
(STBC register)
STP bit
(STBC register)
: Indicates the oscillation stabilization delay time.

Figure 5.5b Timebase Timer Operation

Cleared by changing
to stop mode.
Interval cycle
(TBTC: TBC1, TBC0 = "11 ")
H
Cleared by the interrupt
processing routine.
Sleep mode
Wake-up from Sleep mode by IRQA
Wake-up from Stop mode by an external interrupt
CHAPTER 5 TIMEBASE TIMER
Counter clear
(TBTC: TBR = "0")
Stop mode
21 /F ).
C
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