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Xilinx ChipScope Pro User Manual

Xilinx ChipScope Pro User Manual

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ChipScope Pro
Software and Cores
User Guide
User Guide []
UG029 (v14.3) October 16, 2012
UG029 (v14.3) October 16, 2012 []
This document applies to the following software versions: ISE Design Suite 14.3 through 14.6
This document applies to the following software versions: ISE Design Suite 14.3 through 14.6
This document applies to the following software versions: ISE Design Suite 14.3 through 14.6
This document applies to the following software versions: ISE Design Suite 14.3 through 14.6

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  • Page 1 í ChipScope Pro Software and Cores User Guide [] User Guide UG029 (v14.3) October 16, 2012 [] UG029 (v14.3) October 16, 2012 This document applies to the following software versions: ISE Design Suite 14.3 through 14.6 This document applies to the following software versions: ISE Design Suite 14.3 through 14.6 This document applies to the following software versions: ISE Design Suite 14.3 through 14.6...
  • Page 2 Limited Warranties which can be viewed at http://www.xilinx.com/warranty.htm; IP cores may be subject to warranty and support terms contained in a license issued to you by Xilinx. Xilinx products are not designed or intended to be fail-safe or for use in any application requiring fail-safe performance;...
  • Page 3 ..............31 Using the Xilinx CORE Generator Tool with ChipScope Pro Cores .
  • Page 4 ......223 Appendix B: References ChipScope Pro Software and Cores User Guide www.xilinx.com UG029 (v14.3) October 16, 2012...
  • Page 5 ISE Design Suite Product Table [See Reference 16, p. 225]. ChipScope Pro Tools Description The following table gives a brief description of the various ChipScope Pro tools and cores. Table 1-1: ChipScope Pro Tools Description Tool Description Provides core generation capability for the ICON (integrated...
  • Page 6 Notes: 1. Tcl stands for Tool Command Language. The CSE/Tcl interface requires the Tcl shell program (called xtclsh) that is included in the ChipScope Pro and ISE tool installations or in the ActiveTcl 8.4 shell available from ActiveState [See Reference 24, p.
  • Page 7 • Digilent USB-to-JTAG cables • ByteTools Catapult EJ-1 Ethernet-to-JTAG cable The ChipScope Pro Analyzer tool and cores contain many features that you can use to verify your logic (Table 1-2). User-selectable data channels range from 1 to 4,096 and the sample buffer sizes range from 256 to 131,072 samples.
  • Page 8 X-Ref Target - Figure 1-2 Figure 1-2: ChipScope Pro Tools Design Flow Using ChipScope Pro Cores in the PlanAhead Tool You can add the ChipScope Pro cores to your design using the PlanAhead tool using one of two methods: •...
  • Page 9 The cores (ICON, ILA, IBA, VIO, and ATC2) can also be used in the EDK and System Generator for DSP tool flows for embedded processor and DSP designs, respectively. For information on how to use the ChipScope Pro cores, see the EDK Platform Studio [See Reference 15, p.
  • Page 10 Each trigger port can be connected to up to 16 match units. This Multiple Match Units per feature enables multiple comparisons to be performed on the Trigger Port trigger port signals. www.xilinx.com ChipScope Pro Software and Cores User Guide UG029 (v14.3) October 16, 2012...
  • Page 11 Compares up to 1bit per slice in LUT4-based devices. − Compares up to 4 bits per slice in LUT6-based devices. All match units connected to a given trigger port are the same type. ChipScope Pro Software and Cores User Guide www.xilinx.com UG029 (v14.3) October 16, 2012...
  • Page 12 FPGAs (and the variants of these families). b. LUT6-based device families include Zynq™ -7000 AP SoCs and, Virtex-5, Virtex-6, Spartan-6, Artix™- 7, Kintex-7, and Virtex-7 FPGAs (and the variants of these families). www.xilinx.com ChipScope Pro Software and Cores User Guide UG029 (v14.3) October 16, 2012...
  • Page 13 TRIG2 Match Unit M4 Data Storage (Range) Qualification Data Condition Capture Memory Match Unit M5 TRIG3 Ext. Trigger (Basic w/edges) ila_pro_connection_example_070704 Figure 1-3: ILA Core Connection Example ChipScope Pro Software and Cores User Guide www.xilinx.com UG029 (v14.3) October 16, 2012...
  • Page 14 The ILA core implements a trigger output port called TRIG_OUT. The TRIG_OUT port is the output of the trigger condition that is set up at runtime using the ChipScope Pro Analyzer tool. The shape (level or pulse) and sense (active-High or active-Low) of the trigger output can also be controlled at run-time.
  • Page 15 The data sample in the sample window that coincides with a trigger event is tagged with a trigger mark. This trigger mark tells the ChipScope Pro Analyzer tool the position of the trigger within the window. This trigger mark consumes one extra bit per sample in the sample buffer.
  • Page 16 A pulse train is a 16-clock cycle sequence of 1's and 0's that drive out of the core on successive design clock cycles. The pulse train sequence is defined in the ChipScope Pro Analyzer tool and is executed only one time after it is loaded into the core. www.xilinx.com ChipScope Pro Software and Cores User Guide UG029 (v14.3) October 16, 2012...
  • Page 17 Agilent logic analyzer is also used to control the run-time selection of the active data port by communicating with the ATC2 core via a JTAG port connection (as shown in Figure 1-4). ChipScope Pro Software and Cores User Guide www.xilinx.com UG029 (v14.3) October 16, 2012...
  • Page 18 The design flow for generating IBERT core designs for Virtex-7, Kintex-7, Virtex-6, and Spartan-6 devices are very similar except the Xilinx CORE Generator tool is used. The main difference is that the design directory and device information is specified in the Xilinx CORE Generator project.
  • Page 19 − PMA control, including differential swing, and emphasis. − Ability to change line rates at generate time. − Ability to set reference clock sources at generate time. ChipScope Pro Software and Cores User Guide www.xilinx.com UG029 (v14.3) October 16, 2012...
  • Page 20 The contents of the registers that control the GTX transceiver's Ports Write ports can be changed at runtime. The dynamic status information for the entire core can be read Status out of the core at runtime. www.xilinx.com ChipScope Pro Software and Cores User Guide UG029 (v14.3) October 16, 2012...
  • Page 21 The contents of the registers that control the GTX transceiver's Ports Write ports can be changed at runtime. The dynamic status information for the entire core can be read Status out of the core at runtime. ChipScope Pro Software and Cores User Guide www.xilinx.com UG029 (v14.3) October 16, 2012...
  • Page 22 The contents of the registers that control the GTH transceiver ports can be changed at runtime. Status The dynamic status information for the entire core can be read out of the core at runtime. www.xilinx.com ChipScope Pro Software and Cores User Guide UG029 (v14.3) October 16, 2012...
  • Page 23 Ports Write transceiver ports can be changed at runtime. The dynamic status information for the entire core can be Status read out of the core at runtime. ChipScope Pro Software and Cores User Guide www.xilinx.com UG029 (v14.3) October 16, 2012...
  • Page 24 The contents of the registers that control the GTX transceiver's ports can be changed at runtime. Status The dynamic status information for the entire core can be read out of the core at runtime. www.xilinx.com ChipScope Pro Software and Cores User Guide UG029 (v14.3) October 16, 2012...
  • Page 25 The contents of the registers that control the GTH transceiver's ports can be changed at runtime. Status The dynamic status information for the entire core can be read out of the core at runtime. ChipScope Pro Software and Cores User Guide www.xilinx.com UG029 (v14.3) October 16, 2012...
  • Page 26 The contents of the registers that control the GTP transceiver's ports can be changed at runtime. Status The dynamic status information for the entire core can be read out of the core at runtime. www.xilinx.com ChipScope Pro Software and Cores User Guide UG029 (v14.3) October 16, 2012...
  • Page 27 The contents of the registers that control the GTZ transceiver's ports can be changed at runtime. Status The dynamic status information for the entire core can be read out of the core at runtime. ChipScope Pro Software and Cores User Guide www.xilinx.com UG029 (v14.3) October 16, 2012...
  • Page 28 ChipScope Pro and ISE tool installations. Note: The version (including update revision) of the ChipScope Pro tools must match the version (including update revision) of the ISE tools that is used to implement the design that contains the ChipScope Pro cores.
  • Page 29 • For more information, see ByteTools Web page Ethernet-to-JTAG Cable [See Reference 27, p. 226] Notes: 1. The Parallel Cable IV and Platform Cable USB cables are available for purchase from the Xilinx Online Online Store > Programming Cables Store [See Reference 20, p. 225] (choose ChipScope Pro Software and Cores User Guide www.xilinx.com...
  • Page 30 Parallel Cable IV cable Software Installation and Licensing The ChipScope Pro Analyzer tool can be installed both as a standalone ISE Lab Tools product (for example, in a lab environment where only the ChipScope Pro Analyzer tool is needed) or along with the rest of the ISE Design Suite tools.
  • Page 31 Using the Xilinx CORE Generator Tool with ChipScope Pro Cores Before you can select the ChipScope Pro cores for generation, you must first set up a project in the CORE Generator tool. After setting up your project with the appropriate settings, you can find the ChipScope Pro cores in the CORE Generator tool by first clicking on the View by Function tab in the upper left panel, then by expanding the Debug &...
  • Page 32 IP tab, and search under Embedded Processing > Debug and Trace. • DS774 "LogiCORE IP ChipScope Pro IBERT for Virtex-5 GTX FPGA Transceivers." • DS732 "LogiCORE IP ChipScope Pro IBERT for Virtex-6 GTX FPGA Transceivers." • DS775 "LogiCORE IP ChipScope Pro IBERT for Virtex-6 GTH FPGA Transceivers."...
  • Page 33 This section is provided for users of the Windows or Linux versions of ChipScope Pro and ISE tools. The ChipScope Pro Core Inserter .cdc file can be added as a new source file to the Project Navigator source file list. In addition to this, the Project Navigator tool recognizes and invokes the ChipScope Pro Core Inserter tool during the appropriate steps in the implementation flow.
  • Page 34 Chapter 3: Using the ChipScope Pro Core Inserter ChipScope Definition and Connection Source File To use the ChipScope Pro Core Inserter tool to insert cores into a design processed by Project Navigator: Add the definition and connection file (.cdc) to the project and associate it with the appropriate design module.
  • Page 35 Using the ChipScope Pro Core Inserter with Command Line Implementation Command Line Flow Overview The ChipScope Pro Core Inserter supports a basic command line for batch core insertion. As shown in Figure 3-1, the ChipScope Pro Core Inserter command line flow consists of...
  • Page 36 Figure 3-1: Command Line Core Inserter Flow Create CDC Project Step The Create CDC Project step of the command line ChipScope Pro Core Inserter flow is used to create an empty skeleton CDC project file, as shown in Figure 3-2.
  • Page 37 Using the ChipScope Pro Core Inserter with Command Line Implementation Edit CDC Project Step The Edit CDC Project step of the command line ChipScope Pro Core Inserter flow is used to bring up the ChipScope Pro Core Inserter GUI to edit an existing CDC project (see Figure 3-3).
  • Page 38 Analyzer to import signal names. When the ChipScope Pro Core Inserter is first opened, all the relevant fields are completely blank. Using the command File > New also results in this condition.
  • Page 39 Note: When the ChipScope Pro Core Inserter is invoked from the Project Navigator tool, the Input Design Netlist, Output Design Netlist, Output Directory and Device Family fields are automatically filled in. In this case, these fields can only be changed by the Project Navigator tool and cannot be modified directly in the ChipScope Pro Core Inserter.
  • Page 40 When this step is completed, click Next. Core Utilization The Core Utilization panel on the left side of the ChipScope Pro Core Inserter tool main window displays an estimated count of the look-up table (LUT), flip-flop (FF), and block RAM (BRAM) resources that are consumed by the ChipScope cores that are being inserted into the design netlist.
  • Page 41 ‘=’, ‘<>’, LUT4-based: 2 Extended address or data signals where a R, F, B, ‘>’, ‘>=’, w/edges magnitude and transition LUT6-based: 8 ‘<‘, ‘<=’ detection are important. ChipScope Pro Software and Cores User Guide www.xilinx.com UG029 (v14.3) October 16, 2012...
  • Page 42 Chapter 3: Using the ChipScope Pro Core Inserter Table 3-1: ILA Trigger Match Unit Types (Cont’d) Match Type Bits Per Slice Description Values Function ‘=’, ‘<>’, ‘>’, ‘>=’, Can be used for comparing LUT4-based: 1 ‘<‘, ‘<=’, Range 0, 1, X address or data signals where a ‘in range’,...
  • Page 43 ChipScope Pro Core Inserter tool. It can only be enabled by using the CORE Generator™ tool. Choosing ILA Core Capture Parameters The second tab in the ChipScope Pro Core Inserter is used to set up the capture parameters of the ILA core. Selecting the Data Depth The maximum number of data sample words that the ILA core can store in the sample buffer is called the data depth.
  • Page 44 Chapter 3: Using the ChipScope Pro Core Inserter Entering the Data Width The width of each data sample word stored by the ILA core is called the data width. If the data and trigger words are independent from each other, then the maximum allowable data width depends on the target device type and data depth.
  • Page 45 Signal Bank Count setting is used to denote the number of data input ports or signal banks the multiplexer will implement. The valid Signal Bank Count values are 1, 2, 4, 8, 16, 32, or 64. ChipScope Pro Software and Cores User Guide www.xilinx.com UG029 (v14.3) October 16, 2012...
  • Page 46 Chapter 3: Using the ChipScope Pro Core Inserter TDM Rate The time division multiplexing (TDM) rate is used to increase the amount of data transmitted over each data pin by as much as 200 percent. The ATC2 core does not use on-chip memory resources to store the captured trace data.
  • Page 47 Hold down the Shift key and use the left mouse button to select contiguous nets. Use a combination of the Ctrl key and left mouse button to select non-contiguous nets. You can ChipScope Pro Software and Cores User Guide www.xilinx.com...
  • Page 48 Generation Complete message in the Messages pane indicates successful insertion of ChipScope cores. If you are using the ChipScope Pro Core Inserter as part of the Project Navigator mode, a dialog box appears asking if you want to return to Project Navigator. If Yes, the ChipScope Pro Core Inserter settings are saved and you are returned to the Project Navigator tool.
  • Page 49 EDIF netlist, instead of the top level. These port nets are shown in gray in the Select Net dialog box. The ChipScope Pro Core Inserter can also be set up to display nets that are illegal for connection in the Select Net dialog box. When this preference option is enabled, any illegal nets are shown in red in the Select Net dialog box.
  • Page 50 Chapter 3: Using the ChipScope Pro Core Inserter www.xilinx.com ChipScope Pro Software and Cores User Guide UG029 (v14.3) October 16, 2012...
  • Page 51 The ChipScope Pro Analyzer tool is made up of two distinct applications: the server and the client. The ChipScope Pro Analyzer server is a command line application that connects to...
  • Page 52 The ChipScope Pro Analyzer server is started on 64-bit Windows machines by executing <XILINX_ISE_INSTALL>\bin\nt64\cse_server.exe <command line options> • The ChipScope Pro Analyzer server is started on 32-bit Linux machines by executing <XILINX_ISE_INSTALL>/bin/lin/cse_server <command line options> • The ChipScope Pro Analyzer server is started on 64-bit Linux machines by executing <XILINX_ISE_INSTALL>/bin/lin64/cse_server <command line options>...
  • Page 53 The Copy to Bus operation is the same as Move to Bus except the signals remain as individual signals in the list. ChipScope Pro Software and Cores User Guide www.xilinx.com UG029 (v14.3) October 16, 2012...
  • Page 54 Chapter 4: Using the ChipScope Pro Analyzer Reverse Bus Ordering To reverse the order of the bits in a bus (that is, to make the LSB the MSB), right-click the bus and select Reverse Bus Order. The signal browser and all data views that contain that bus are immediately updated and the bus values recalculated.
  • Page 55 Type and Activity Persistence (VIO only) VIO signals have two additional properties: Type and Activity Persistence. See “VIO Bus/Signal Activity Persistence,” page 77 for explanations of these properties. ChipScope Pro Software and Cores User Guide www.xilinx.com UG029 (v14.3) October 16, 2012...
  • Page 56 To open an existing project, select File > Open Project, or select one of the recently used projects in the File menu. The title bar of the ChipScope Pro Analyzer and the project tree displays the project name. If the new project is not saved during the course of the session, a dialog box appears when the ChipScope Pro Analyzer tool is about to exit, asking you if you wish to save the project.
  • Page 57 You can choose to print the signal names on each page or only on the first page. When Show Cursor Values is enabled, this value also affects the display of the X/O cursor values. ChipScope Pro Software and Cores User Guide www.xilinx.com UG029 (v14.3) October 16, 2012...
  • Page 58 You can enable or disable the inclusion of a footer at the bottom of each page by selecting the Show Footer checkbox. The footer contains useful information including the ChipScope Pro Analyzer project name, waveform settings, print settings, and page numbers.
  • Page 59 File > Page Setup menu option. Note: In the ChipScope Pro Analyzer program, you can print only to the default system printer. Changing the target printer in the print setup window does not have any effect. To change printers, you must close the ChipScope Pro Analyzer program, change your default system printer, and restart the ChipScope Pro Analyzer program.
  • Page 60 Viewing Options You can hide or display the split pane on the left of the ChipScope Pro Analyzer window and the Message pane at the bottom of the window. By default, both are displayed the first time the ChipScope Pro Analyzer tool is launched.
  • Page 61 If the ChipScope Pro Analyzer tool returns the error message Failed to Open Communication Port, verify that the cable is connected to the correct LPT port. If you have not installed the Parallel Cable driver, follow the instructions in the ChipScope Pro tool installation program to install the required device driver software.
  • Page 62 Setting Up ChipScope Pro Analyzer tool to Use Multiple Instances of cs_server Set up the ChipScope Pro Analyzer tool to use multiple cables first by starting multiple instances of the cs_server.exe Windows application or cs_server.sh Linux application on the same machine using different ports. For example, to start up two servers on different ports on Linux, use: # cs_server.sh -port 50001...
  • Page 63 If other programs are using the cable at the same time as the ChipScope Pro Analyzer tool, it can often be beneficial to turn this polling off. This can be done in the JTAG Chain menu by un-checking JTAG Chain > Auto Core Status Poll.
  • Page 64 Selecting the Clean previous project setting check box removes all signal names, buses, and other settings from your project. This operation cannot be undone. To select a design-level CDC file that was generated either by the ChipScope Pro Core Inserter or PlanAhead tools, click the Import Design-level CDC File check box, then click Select New File in the Design-level CDC File section.
  • Page 65 However, the trigger can be in any position in the window. If N Samples is selected, the buffer has as ChipScope Pro Software and Cores User Guide www.xilinx.com...
  • Page 66 Chapter 4: Using the ChipScope Pro Analyzer many windows as possible with the defined samples per trigger. The trigger is always the first sample in the window if N Samples is selected. Windows The Windows text field is only available when Window is selected in the Type combo box.
  • Page 67 • If occurring in exactly n clock cycles is selected, then n contiguous or n noncontiguous events satisfies the match function counter condition. ChipScope Pro Software and Cores User Guide www.xilinx.com UG029 (v14.3) October 16, 2012...
  • Page 68 Chapter 4: Using the ChipScope Pro Analyzer • If occurring in at least n clock cycles is selected, then n contiguous or n noncontiguous events satisfies the match function counter condition, and it remains satisfied until the overall trigger condition is met.
  • Page 69 0. After the sample buffer fills with data, the trigger disarms and the captured data appears in the Waveform and/or Listing window(s). ChipScope Pro Software and Cores User Guide www.xilinx.com UG029 (v14.3) October 16, 2012...
  • Page 70 Stopping the data acquisition disarms the active trigger and any data captured up to that point in time is lost. Trigger Run Modes The ChipScope Pro Analyzer tool supports three trigger run modes for the ILA core: • Single •...
  • Page 71 The startup trigger run mode allows you to set up the ILA core to trigger on events that occur after FPGA device startup without having to use the ChipScope Pro Analyzer tool to arm the ILA core. Using the Startup Trigger Run Mode requires you to follow three steps: Specify the trigger settings and save the startup trigger setup (CTJ) and design constraint (UCF) files.
  • Page 72 After you re-implement your design and create a new BIT file, configure the device with this BIT file using the ChipScope Pro Analyzer tool. To see if your startup trigger condition has occurred, first change the Trigger Run Mode to Startup. The software prompts you to specify the startup trigger files that were used during the implementation process to create the BIT file.
  • Page 73 To view the waveform for a particular ILA core, select Window > New Unit Windows, and the core desired. A dialog box appears for that ChipScope Pro core unit, and you can select the Trigger Setup, Waveform, Listing, and/or Bus Plot window, or any combination.
  • Page 74 To view the Listing window for a particular ILA core, select Window > New Unit Windows, and the core desired. A dialog box displays for that ChipScope Pro Unit, in which you can select any combination of Trigger Setup, Waveform, Listing, and/or Bus Plot windows.
  • Page 75 To view the Bus Plot window for a particular set of ILA buses, select Window > New Unit Windows and the core desired. A dialog box displays for that ChipScope Pro Unit, on which you can select any combination of Trigger Setup, Waveform, Listing, and /or Bus Plot window, or any combination.
  • Page 76 To open the Console window for a VIO core, select Window > New Unit Windows, and the core desired. A dialog box is displayed for that ChipScope Pro Unit, and you can select the Console window. (Windows cannot be closed from this dialog box.) The Console window is for VIO cores only.
  • Page 77 The length of time the activity is displayed in the table is called the persistence. The persistence is also individually selectable via the right-click menu. ChipScope Pro Software and Cores User Guide www.xilinx.com UG029 (v14.3) October 16, 2012...
  • Page 78 Chapter 4: Using the ChipScope Pro Analyzer Note: The activity arrow is displayed in black if the activity is synchronous and red if it is asynchronous. You can choose the VIO signal/bus value type by right-clicking on the signal or bus and selecting the Type menu choice.
  • Page 79 [See Reference 13, p. 225] The ChipScope Pro Analyzer tool provides real-time JTAG access to the on-chip voltage and temperature sensors of the System Monitor primitive. All the on-chip sensors are available before and after the FPGA device has been configured with a valid bitstream. The System Monitor functionality does not require that you instantiate a System Monitor primitive block into your design.
  • Page 80 Chapter 4: Using the ChipScope Pro Analyzer • Sampled maximum and minimum values that are derived from all sensor values that have been collected by the ChipScope Pro Analyzer tool since opening a JTAG cable connection (or the last System Monitor reset) •...
  • Page 81 (in kilobytes). IBERT v2.0 Console Window for Virtex-5 FPGA GTX Transceivers To open the console for a ChipScope Pro IBERT v2.0 core for Virtex-5 FPGA GTX transceivers, select Window> New Unit Windows and the core desired. A dialog box displays for that core, and you can select the IBERT V5 GTX Console.
  • Page 82 Chapter 4: Using the ChipScope Pro Analyzer MGT Settings The MGT Alias setting is initially set to the MGT number of the GTX transceiver, but can be changed by selecting the field and typing in a new value. The Tile Location setting denotes the X/Y coordinate of the GTX transceiver in the device.
  • Page 83 The DRP Settings panel contains a table that is made up of one or more vertical columns and horizontal rows. Each column represents a specific active GTX transceiver. Each row represents a specific DRP attribute or address. ChipScope Pro Software and Cores User Guide www.xilinx.com UG029 (v14.3) October 16, 2012...
  • Page 84 Chapter 4: Using the ChipScope Pro Analyzer When the radio button at the bottom of the panel is set to View By Attribute Name, all the DRP attributes are displayed in alphabetical order. The Radix combo lets you choose between Hex (hexadecimal) and Bin (binary). To change a value, just click in the text field where the value is, type in a new value, and press Enter.
  • Page 85 The Test Results panel shows which is the current run, the elapsed time, and the estimated time remaining. Below this status information is a running log of the sweep test results. These results are also saved to the Log File. ChipScope Pro Software and Cores User Guide www.xilinx.com UG029 (v14.3) October 16, 2012...
  • Page 86 The JTAG Scan Rate toolbar and IBERT_V5GTX >JTAG Scan Rate menu options are used to select how frequently the ChipScope Pro Analyzer tool queries the IBERT core for status information. The default is 1s between queries, but it can be set to 250 ms, 500 ms, 1s, 2s, 5s, or Manual Scan.
  • Page 87 TX pins. The Channel Reset button resets the GTX transceiver channel by clearing and resetting all internal PMA and PCS circuitry as well as the related fabric interfaces. ChipScope Pro Software and Cores User Guide www.xilinx.com UG029 (v14.3) October 16, 2012...
  • Page 88 Chapter 4: Using the ChipScope Pro Analyzer The TX Polarity Invert setting controls the polarity of the data sent out of the TX pins of the GTX transceiver channel. To change the polarity of the TX side of the GTX transceiver, check the TX Polarity Invert box.
  • Page 89 Setting up the sweep test first involves setting up the sweep parameters. The GTX transceiver parameters that are available for sweep default to the following: • TX Diff Swing • TX Pre-Emphasis • TX Post-Emphasis ChipScope Pro Software and Cores User Guide www.xilinx.com UG029 (v14.3) October 16, 2012...
  • Page 90 Chapter 4: Using the ChipScope Pro Analyzer • RX EQ The sweep parameters can be initialized in one of two ways: • Click the Clear All Parameters button to clear all parameters to the Select… option. • Click the Set Parameters to Current Values button to set the parameters to their current values on the MGT/BERT Settings panel.
  • Page 91 One useful sort strategy is to sort the plots from the widest to the lowest UI opening by clicking the Opening at the Lowest BER Level column header. ChipScope Pro Software and Cores User Guide www.xilinx.com UG029 (v14.3) October 16, 2012...
  • Page 92 The JTAG Scan Rate toolbar and IBERT_V6GTX > JTAG Scan Rate menu options are used to select how frequently the ChipScope Pro Analyzer tool queries the IBERT core for status information. The default is 1s between queries, but it can be set to 250 ms, 500 ms, 1s, 2s, 5s, or Manual Scan.
  • Page 93 The TX Post-Emphasis combo box controls the amount of post-emphasis on the transmitted signal. Change the value in the combo box to change the emphasis. The RX Equalization setting controls the internal RX equalization circuit. ChipScope Pro Software and Cores User Guide www.xilinx.com UG029 (v14.3) October 16, 2012...
  • Page 94 Chapter 4: Using the ChipScope Pro Analyzer BERT Settings The TX/RX Data Pattern settings are used to select the data pattern that is used by the transmit pattern generator and receive pattern checker, respectively. These patterns include PRBS 7, 15, 23, and 31, and Clk 2x and 10x.
  • Page 95 Down buttons. To revert the sweep attributes and their order to the default setting, click the Reset to Default button. Click OK to apply the settings, or Cancel to exit without saving. ChipScope Pro Software and Cores User Guide www.xilinx.com UG029 (v14.3) October 16, 2012...
  • Page 96 Chapter 4: Using the ChipScope Pro Analyzer Sampling Point Region The sampling point is the horizontal point within the eye to sample. Visualize on transition region at the far left, and the next at the far right. The RX Sampling Point is one of 128 discrete sampling positions.
  • Page 97 The third screen is the confirmation screen, summarizing the source and destination(s) for the settings. Click Apply to execute the import or export. This operation cannot be undone. ChipScope Pro Software and Cores User Guide www.xilinx.com UG029 (v14.3) October 16, 2012...
  • Page 98 The JTAG Scan Rate toolbar and IBERT_V6GTH > JTAG Scan Rate menu options are used to select how frequently the ChipScope Pro Analyzer tool queries the IBERT core for status information. The default is 1s between queries, but it can be set to 250 ms, 500 ms, 1s, 2s, 5s, or Manual Scan.
  • Page 99 (on average) for every trillion bits received. The RX Received Bit Count field contains a running tally of the number of bits received. This count resets when the BERT Reset button is pushed. ChipScope Pro Software and Cores User Guide www.xilinx.com UG029 (v14.3) October 16, 2012...
  • Page 100 Chapter 4: Using the ChipScope Pro Analyzer The RX Bit Error Count field contains a running tally of the number of bit errors detected. This count resets when the BERT Reset button is pushed. The BERT Reset button resets the bit error and received bit counters. It is appropriate to reset the BERT counters after the GTP transceiver channel is linked and stable.
  • Page 101 Down buttons. To revert the sweep attributes and their order to the default setting, click the Reset to Default button. Click OK to apply the settings, or Cancel to exit without saving. ChipScope Pro Software and Cores User Guide www.xilinx.com UG029 (v14.3) October 16, 2012...
  • Page 102 Chapter 4: Using the ChipScope Pro Analyzer Sampling Point Region The sampling point is the horizontal point within the eye to sample. Visualize on transition region at the far left, and the next at the far right. The RX Sampling Point is one of 128 discrete sampling positions.
  • Page 103 The JTAG Scan Rate toolbar and IBERT_S6GTP > JTAG Scan Rate menu options are used to select how frequently the ChipScope Pro Analyzer tool queries the IBERT core for status information. The default is 1s between queries, but it can be set to 250 ms, 500 ms, 1s, 2s, 5s, or Manual Scan.
  • Page 104 Chapter 4: Using the ChipScope Pro Analyzer (green), the measured line rate is displayed. If the channel is not linked, it displays NO Link (red). The CPLL/QPLL Status indicator shows the lock status of the CPLL/QPLL that is connected to the GTX transceiver. The valid states of this status indicator are CPLL/QPLL LOCKED (green) or CPLL/QPLL NOT LOCKED (red).
  • Page 105 The ports in the table that are editable look like text fields, and placing the cursor in those fields, typing a new value, and pressing Enter writes the new value to the MGT immediately. ChipScope Pro Software and Cores User Guide www.xilinx.com UG029 (v14.3) October 16, 2012...
  • Page 106 Chapter 4: Using the ChipScope Pro Analyzer RX Margin Analysis Panel Use the RX Margin Analysis panel to set up a channel test that sweeps through various transceiver settings to help find the optimal channel settings. The TX and RX settings shown in this panel are for the same GTX transceiver.
  • Page 107 Below this status information are three tabbed panels showing the results of the sweep test: • Sweep Test Log • Sweep Test Plots ChipScope Pro Software and Cores User Guide www.xilinx.com UG029 (v14.3) October 16, 2012...
  • Page 108 Chapter 4: Using the ChipScope Pro Analyzer • Sweep Test Info Sweep Test Log: The Sweep Test Log tabbed panel is always enabled and contains the running log of the sweep test results. The information on this panel is shown using a text- only display.
  • Page 109 The JTAG Scan Rate toolbar and IBERT_K7GTX > JTAG Scan Rate menu options are used to select how frequently the ChipScope Pro Analyzer tool queries the IBERT core for status information. The default is 1s between queries, but it can be set to 250 ms, 500 ms, 1s, 2s, 5s, or Manual Scan.
  • Page 110 Chapter 4: Using the ChipScope Pro Analyzer • Port Settings Panel • IBERT Virtex-7 FPGA GTH Transceiver Toolbar and Menu Options MGT/BERT Settings Panel The MGT/BERT Settings panel contains a table that is made up of one or more vertical columns and horizontal rows.
  • Page 111 The Radix combo box lets you choose between Hex (hexadecimal) and Bin (binary). To change a value, just click in ChipScope Pro Software and Cores User Guide www.xilinx.com UG029 (v14.3) October 16, 2012...
  • Page 112 Chapter 4: Using the ChipScope Pro Analyzer the text field where the value is, type in a new value, and press Enter. The new value is immediately set in the MGT. Port Settings Panel The Port Settings panel contains a table that is made up of one or more vertical columns and horizontal rows.
  • Page 113 You can set both the location of the file and the number of sweep iterations stored in each file. If the total number of sweep iterations exceeds the file limit, multiple files with ChipScope Pro Software and Cores User Guide www.xilinx.com...
  • Page 114 Chapter 4: Using the ChipScope Pro Analyzer starting iteration number appended to the base file name are created in the same directory as the initial result file. • Use the Dwell controls to specify how long a measurement is taken at a particular scan offset location.
  • Page 115 Click Apply to execute the import or export. This operation cannot be undone. Reset All To reset all the channels in the IBERT core, select IBERT_V7GTH > Reset All or click the Reset All button in the toolbar. ChipScope Pro Software and Cores User Guide www.xilinx.com UG029 (v14.3) October 16, 2012...
  • Page 116 The JTAG Scan Rate toolbar and IBERT_V7GTH > JTAG Scan Rate menu options are used to select how frequently the ChipScope Pro Analyzer tool queries the IBERT core for status information. The default is 1s between queries, but it can be set to 250 ms, 500 ms, 1s, 2s, 5s, or Manual Scan.
  • Page 117 The BERT Settings also include RX Received Bit Counter, RX Bit Error Count, and Bit Error Ratio (BER) indicator. The BERT Reset button is used to reset these counters. Clocking Settings ChipScope Pro Software and Cores User Guide www.xilinx.com UG029 (v14.3) October 16, 2012...
  • Page 118 Chapter 4: Using the ChipScope Pro Analyzer The TXUSRCLK Freq (MHz) indicator shows the approximate clocking frequency (in MHz) of the TXUSRCLK port of the GTP transceiver. The accuracy of this status indicator depends on the frequency of the system clock that was specified at compile time.
  • Page 119 • 1D Bathtub: Scans all horizontal sampling points through the 0 vertical row offset. This mode is useful for performing quick analysis of received phase margin. ChipScope Pro Software and Cores User Guide www.xilinx.com UG029 (v14.3) October 16, 2012...
  • Page 120 Chapter 4: Using the ChipScope Pro Analyzer The horizontal and vertical offsets can be controlled independently. Each offset can be controlled to have an interval and range. The Range combo box controls the maximum and minimum offset values of the scan. The Interval combo box controls how many rows or columns are skipped between each row or column that is scanned.
  • Page 121 In the Import/Export dialog box, you can save and recall settings from a specific MGT or apply the setting of one MGT to others in the design. To import or export settings, select ChipScope Pro Software and Cores User Guide www.xilinx.com...
  • Page 122 IBERT Console Window for 7 Series FPGA GTZ Transceivers To open the console for a ChipScope Pro IBERT core for Virtex-7 FPGA GTZ transceivers, select Window > New Unit Windows and the core desired. A dialog box displays for that core, and you can select the IBERT V7 GTZ Console.
  • Page 123 The DRP Settings panel contains a table that is made up of one or more vertical columns and horizontal rows. Each column represents a specific active GTZ transceiver octal group ChipScope Pro Software and Cores User Guide www.xilinx.com UG029 (v14.3) October 16, 2012...
  • Page 124 Chapter 4: Using the ChipScope Pro Analyzer of eight associated GTZ transceivers. Each row represents a specific DRP attribute or address. When the radio button at the bottom of the panel is set to View By Attribute Name, all the DRP attributes display in alphabetical order.
  • Page 125 After the sweep test has been set up, the test can be started by clicking the Start button. After the Start button is clicked, the sweep parameter table is disabled and the test starts running. ChipScope Pro Software and Cores User Guide www.xilinx.com UG029 (v14.3) October 16, 2012...
  • Page 126 Chapter 4: Using the ChipScope Pro Analyzer As the sweep test runs, the current sweep result file, current iteration, elapsed time, and estimated time remaining status indicators are displayed. The sweep results are shown in the Sweep Test Log text area near the bottom of the screen. The sweep test can be paused by clicking on the Pause button or stopped completely by clicking on the Stop &...
  • Page 127 The third screen is the confirmation screen, summarizing the source and destination(s) for the settings. Click Apply to execute the import or export. This operation cannot be undone. ChipScope Pro Software and Cores User Guide www.xilinx.com UG029 (v14.3) October 16, 2012...
  • Page 128 Use the JTAG Scan Rate toolbar and IBERT_V7GTZ > JTAG Scan Rate menu options to select how frequently the ChipScope Pro Analyzer tool queries the IBERT core for status information. The default is 1s between queries, but you can select 250 ms, 500 ms, 1s, 2s, 5s, or Manual Scan.
  • Page 129 • Fit Window: Same as Waveform > Zoom > Zoom Fit ChipScope Pro Analyzer Command Line Options On Windows systems, the ChipScope Pro Analyzer tool can be started either from the command line or from the Start menu. • On 32-bit Windows systems, you can invoke the ChipScope Pro Analyzer tool from the command line by running: <XILINX_ISE_INSTALL>\bin\nt\analyzer.exe...
  • Page 130 Chapter 4: Using the ChipScope Pro Analyzer Read specified init file at start up and write to the same file when the ChipScope Pro Analyzer tool exits. The default is: %userprofile%\.chipscope\cs_analyzer.ini -log <path and filename> -log stdout Write log messages to the specified file. Specifying stdout writes to standard output.
  • Page 131 A supported JTAG cable such as Platform Cable USB, Parallel Cable IV, or Parallel Cable III. • A Tcl shell (xtclsh is provided in the ChipScope Pro and ISE® tool installations) or the ActiveTcl 8.4 shell [See Reference 24, p.
  • Page 132 “CseJtag Tcl Commands,” page 137 for additional information about these commands. Note: Refer to the file csejtagglobals.tcl in the ChipScope Pro tool installation for all CseJtag Tcl global variable declarations. www.xilinx.com ChipScope Pro Software and Cores User Guide UG029 (v14.3) October 16, 2012...
  • Page 133 Gets the value of a JTAG target TAP pin. get_pin Pulses a JTAG target TAP pin. pulse_pin Waits for a specified amount of time. wait_time Gets information associated with a JTAG target. get_info ChipScope Pro Software and Cores User Guide www.xilinx.com UG029 (v14.3) October 16, 2012...
  • Page 134 CseFpga Tcl Commands The CseFpga Tcl command category consists of several commands (see Table 5-7). Note: Refer to the file csefpgaglobals.tcl in the ChipScope Pro tool installation for all CseFpga Tcl global variable declarations. Table 5-7: CseFpga Tcl Commands Command Description...
  • Page 135 ::chipscope::csefpga_set_sys_mon_reg Assign configuration mask data from a buffer to a specific ::chipscope::csefpga_assign_config_data_ device. to_device Assign configuration mask data from a file to a specific ::chipscope::csefpga_assign_config_data_ device. file_to_device ChipScope Pro Software and Cores User Guide www.xilinx.com UG029 (v14.3) October 16, 2012...
  • Page 136 CseCore Tcl Commands The CseCore Tcl command category consists of several commands (see Table 5-8). Note: Refer to the file csecoreglobals.tcl in the ChipScope Pro tool installation for all CseCore Tcl global variable declarations. Table 5-8: CseCore Tcl Commands Command Description...

  • Page 137: Table Of Contents

    • ::chipscope::csejtag_tap shift_device_ir • ::chipscope::csejtag_tap shift_chain_dr • ::chipscope::csejtag_tap shift_device_dr • ::chipscope::csejtag_db add_device_data • ::chipscope::csejtag_db lookup_device • ::chipscope::csejtag_db get_device_name_for_idcode • ::chipscope::csejtag_db get_irlength_for_idcode • ::chipscope::csejtag_db parse_bsdl • ::chipscope::csejtag_db parse_bsdl_file ChipScope Pro Software and Cores User Guide www.xilinx.com UG029 (v14.3) October 16, 2012...
  • Page 138 Create a new session using the client/server libraries to a server called lab_machine at port “50001”. %set handle [::chipscope::csejtag_session create messageRouterFn -server “lab_machine” -port “50001”] Back to list of all CseJtag Tcl Commands www.xilinx.com ChipScope Pro Software and Cores User Guide UG029 (v14.3) October 16, 2012...

  • Page 139: Chipscope::csejtag_Session Create

    Example Obtain a list containing the API version number and the build number version string %set api_info [::chipscope::csejtag_session get_api_version] Back to list of all CseJtag Tcl Commands ChipScope Pro Software and Cores User Guide www.xilinx.com UG029 (v14.3) October 16, 2012...
  • Page 140 An exception is thrown if the command fails. Example Send the message "Hello World!" to the message router function. %::chipscope::csejtag_session send_message $handle $CSE_MSG_INFO "Hello World!" Back to list of all CseJtag Tcl Commands www.xilinx.com ChipScope Pro Software and Cores User Guide UG029 (v14.3) October 16, 2012...
  • Page 141 200000}" $CSEJTAG_TARGET_PLATFORMUSB "port=USB2 (aliased to USB21) | USB21 | USB22 | USB23 | ..." "ESN=<electronic serial number string>" "frequency={12000000 | 6000000 | 3000000 | 1500000 | 750000}" ChipScope Pro Software and Cores User Guide www.xilinx.com UG029 (v14.3) October 16, 2012...
  • Page 142 The port string port The full target name string full_name The target-unique ID string. For the Xilinx Platform Cable USB, this is target_uid the Electronic Serial Number (ESN). The raw target info string rawinfo The integer containing target-specific flags...
  • Page 143 An exception is thrown if the subcommand fails. Example Close the current target in the specified session. %::chipscope::csejtag_target close $handle Back to list of all CseJtag Tcl Commands ChipScope Pro Software and Cores User Guide www.xilinx.com UG029 (v14.3) October 16, 2012...
  • Page 144 An exception is thrown if the subcommand fails. Example Return current target in the specified session. %set isConnected (::chipscope::csejtag_target is_connected $handle) Back to list of all CseJtag Tcl Commands www.xilinx.com ChipScope Pro Software and Cores User Guide UG029 (v14.3) October 16, 2012...
  • Page 145 Attempt to obtain an exclusive target lock and wait at least 1000 milliseconds. Obtains the status of the lock. %set lockStatus [::chipscope::csejtag_target lock $handle 1000] Back to list of all CseJtag Tcl Commands ChipScope Pro Software and Cores User Guide www.xilinx.com UG029 (v14.3) October 16, 2012...

  • Page 146: Chipscope::csejtag_Target Unlock

    An exception is thrown if the subcommand fails. Example Unlock the target in the specified session. %::chipscope::csejtag_target unlock $handle Back to list of all CseJtag Tcl Commands www.xilinx.com ChipScope Pro Software and Cores User Guide UG029 (v14.3) October 16, 2012...
  • Page 147 An exception is thrown if the subcommand fails. Example Obtain the current lock status. %set lockStatus [::chipscope::csejtag_target get_lock_status $handle] Back to list of all CseJtag Tcl Commands ChipScope Pro Software and Cores User Guide www.xilinx.com UG029 (v14.3) October 16, 2012...

  • Page 148: Chipscope::csejtag_Target Clean_Locks

    Clean locks as a last resort because the application closed unexpectedly and does not open the target successfully. ::chipscope::csejtag_target open %::chipscope::csejtag_target clean_locks $handle Back to list of all CseJtag Tcl Commands www.xilinx.com ChipScope Pro Software and Cores User Guide UG029 (v14.3) October 16, 2012...

  • Page 149: Chipscope::csejtag_Target Flush

    Attempt to flush an opened and locked buffer of a JTAG target to make data writes occur immediately. %::chipscope::csejtag_target flush $handle Back to list of all CseJtag Tcl Commands ChipScope Pro Software and Cores User Guide www.xilinx.com UG029 (v14.3) October 16, 2012...
  • Page 150 An exception is thrown if the subcommand fails. Example Set the TMS pin to 1. %::chipscope::csejtag_target set_pin $handle $CSEJTAG_TMS 1 Back to list of all CseJtag Tcl Commands www.xilinx.com ChipScope Pro Software and Cores User Guide UG029 (v14.3) October 16, 2012...
  • Page 151 An exception is thrown if the subcommand fails. Example Get the current value of the TDO pin. %set value [::chipscope::csejtag_target set_pin $handle $CSEJTAG_TDO] Back to list of all CseJtag Tcl Commands ChipScope Pro Software and Cores User Guide www.xilinx.com UG029 (v14.3) October 16, 2012...
  • Page 152 An exception is thrown if the subcommand fails. Example Pulse the TCK pin five times. %::chipscope::csejtag_target pulse_pin $handle $CSEJTAG_TCK 5 Back to list of all CseJtag Tcl Commands www.xilinx.com ChipScope Pro Software and Cores User Guide UG029 (v14.3) October 16, 2012...

  • Page 153: Chipscope::csejtag_Target Wait_Time

    An exception is thrown if the subcommand fails. Example Instruct the JTAG target to wait 1000 microseconds before performing another operation. %::chipscope::csejtag_target wait_time $handle 1000 Back to list of all CseJtag Tcl Commands ChipScope Pro Software and Cores User Guide www.xilinx.com UG029 (v14.3) October 16, 2012...

  • Page 154: Chipscope::csejtag_Target Get_Info

    An exception is thrown if the subcommand fails. Example Obtain information about the current JTAG target. %set targetInfo [::chipscope::csejtag_target get_info $handle] Back to list of all CseJtag Tcl Commands www.xilinx.com ChipScope Pro Software and Cores User Guide UG029 (v14.3) October 16, 2012...

  • Page 155: Chipscope::csejtag_Tap Autodetect_Chain

    JTAG chain must be detected and assigned manually. Example Attempt to automatically detect the chain using the default algorithm. %::chipscope::csejtag_tap autodetect_chain $handle $CSEJTAG_SCAN_DEFAULT Back to list of all CseJtag Tcl Commands ChipScope Pro Software and Cores User Guide www.xilinx.com UG029 (v14.3) October 16, 2012...

  • Page 156: Chipscope::csejtag_Tap Interrogate_Chain

    An exception is thrown if the subcommand fails. Example Attempt to interrogate the chain using the default algorithm. %::chipscope::csejtag_tap interrogate_chain $handle $CSEJTAG_SCAN_DEFAULT Back to list of all CseJtag Tcl Commands www.xilinx.com ChipScope Pro Software and Cores User Guide UG029 (v14.3) October 16, 2012...

  • Page 157: Chipscope::csejtag_Tap Get_Device_Count

    An exception is thrown if the subcommand fails. Example Obtain the number of devices in the JTAG chain. %set deviceCount [::chipscope::csejtag_tap get_device_count $handle] Back to list of all CseJtag Tcl Commands ChipScope Pro Software and Cores User Guide www.xilinx.com UG029 (v14.3) October 16, 2012...

  • Page 158: Chipscope::csejtag_Tap Set_Device_Count

    An exception is thrown if the subcommand fails. Example Set the number of devices in the JTAG chain to four. %::chipscope::csejtag_tap set_device_count $handle 4 Back to list of all CseJtag Tcl Commands www.xilinx.com ChipScope Pro Software and Cores User Guide UG029 (v14.3) October 16, 2012...

  • Page 159: Chipscope::csejtag_Tap Get_Irlength

    An exception is thrown if the subcommand fails. Example Get the IR length of the device at index 0. %set irLength [::chipscope::csejtag_tap get_irlength $handle 0] Back to list of all CseJtag Tcl Commands ChipScope Pro Software and Cores User Guide www.xilinx.com UG029 (v14.3) October 16, 2012...

  • Page 160: Chipscope::csejtag_Tap Set_Irlength

    Example Set the IR length of the device at index 0 to 11 bits. %::chipscope::csejtag_tap set_irlength $handle 0 11 Back to list of all CseJtag Tcl Commands www.xilinx.com ChipScope Pro Software and Cores User Guide UG029 (v14.3) October 16, 2012...

  • Page 161: Chipscope::csejtag_Tap Get_Device_Idcode

    An exception is thrown if the subcommand fails. Example Get the IDCODE of the device at index 0 %set idcode [::chipscope::csejtag_tap get_device_idcode $handle 0] Back to list of all CseJtag Tcl Commands ChipScope Pro Software and Cores User Guide www.xilinx.com UG029 (v14.3) October 16, 2012...
  • Page 162 An exception is thrown if the subcommand fails. Example Set the IDCODE of the device at index 0 to 01010101010101010101010101010101. %::chipscope::csejtag_tap set_device_idcode $handle 0 “01010101010101010101010101010101” Back to list of all CseJtag Tcl Commands www.xilinx.com ChipScope Pro Software and Cores User Guide UG029 (v14.3) October 16, 2012...
  • Page 163 Navigate the TAP state to Test Logic Reset and keep it in this state for five additional clock cycles. %::chipscope::csejtag_tap navigate $handle $CSEJTAG_TEST_LOGIC_RESET 5 Back to list of all CseJtag Tcl Commands ChipScope Pro Software and Cores User Guide www.xilinx.com UG029 (v14.3) October 16, 2012...
  • Page 164 A buffer that is full of the data that is shifted out of the TDO pin of the JTAG TAP. An exception is thrown if the subcommand fails. www.xilinx.com ChipScope Pro Software and Cores User Guide UG029 (v14.3) October 16, 2012...
  • Page 165 Run Test Idle state when finished. %set hextdobuf [::chipscope::csejtag_tap shift_chain_ir $handle $CSEJTAG_SHIFT_READWRITE $CSEJTAG_RUN_TEST_IDLE progressFunc 64 “FFFFFFFFFFFFFFFF”] Back to list of all CseJtag Tcl Commands ChipScope Pro Software and Cores User Guide www.xilinx.com UG029 (v14.3) October 16, 2012...

  • Page 166: Chipscope::csejtag_Tap Shift_Chain_Ir

    Specifies that a mask word hextdomaskval should be -hextdomask applied to the data buffer bits after the data is shifted out of hextdomaskval the TDO pin of the JTAG TAP. www.xilinx.com ChipScope Pro Software and Cores User Guide UG029 (v14.3) October 16, 2012...
  • Page 167 11 bits of received data, and navigates to the Run Test Idle state when finished. %set hextdobuf [::chipscope::csejtag_tap shift_device_ir $handle 1 $CSEJTAG_SHIFT_READWRITE $CSEJTAG_RUN_TEST_IDLE progressFunc 11 “7FF”] Back to list of all CseJtag Tcl Commands ChipScope Pro Software and Cores User Guide www.xilinx.com UG029 (v14.3) October 16, 2012...

  • Page 168: Chipscope::csejtag_Tap Shift_Chain_Dr

    A buffer that is full of the data that is shifted out of the TDO pin of the JTAG TAP. An exception is thrown if the subcommand fails. www.xilinx.com ChipScope Pro Software and Cores User Guide UG029 (v14.3) October 16, 2012...
  • Page 169 Run Test Idle state when finished. %set hextdobuf [::chipscope::csejtag_tap shift_chain_dr $handle $CSEJTAG_SHIFT_READWRITE $CSEJTAG_RUN_TEST_IDLE progressFunc 64 “FFFFFFFFFFFFFFFF”] Back to list of all CseJtag Tcl Commands ChipScope Pro Software and Cores User Guide www.xilinx.com UG029 (v14.3) October 16, 2012...
  • Page 170 Specifies that a mask word hextdomaskval should be -hextdomask applied to the data buffer bits after the data is shifted out hextdomaskval of the TDO pin of the JTAG TAP. www.xilinx.com ChipScope Pro Software and Cores User Guide UG029 (v14.3) October 16, 2012...
  • Page 171 Run Test Idle state when finished. %set hextdobuf [::chipscope::csejtag_tap shift_device_dr $handle 1 $CSEJTAG_SHIFT_READWRITE $CSEJTAG_RUN_TEST_IDLE progressFunc 11 “7FF”] Back to list of all CseJtag Tcl Commands ChipScope Pro Software and Cores User Guide www.xilinx.com UG029 (v14.3) October 16, 2012...

  • Page 172: Chipscope::csejtag_Db Add_Device_Data

    Adding data from the file my_idcode.lst to the internal device database. Also, store the data record buffer and buffer size in local variables. %::chipscope::csejtag_db add_device_data $handle “my_idcode.lst” $my_idcode_buf $my_idcode_bufLen Back to list of all CseJtag Tcl Commands www.xilinx.com ChipScope Pro Software and Cores User Guide UG029 (v14.3) October 16, 2012...

  • Page 173: Chipscope::csejtag_Db Lookup_Device

    Example Look in the database for the device information belonging to IDCODE 01010101010101010101010101010101. %set deviceInfo [::chipscope::csejtag_db lookup_device $handle “01010101010101010101010101010101”] Back to list of all CseJtag Tcl Commands ChipScope Pro Software and Cores User Guide www.xilinx.com UG029 (v14.3) October 16, 2012...

  • Page 174: Chipscope::csejtag_Db Get_Device_Name_For_Idcode

    Look in the database for the name of the device belonging to IDCODE 01010101010101010101010101010101. %set deviceName [::chipscope::csejtag_db get_device_name_for_idcode $handle “01010101010101010101010101010101”] Back to list of all CseJtag Tcl Commands www.xilinx.com ChipScope Pro Software and Cores User Guide UG029 (v14.3) October 16, 2012...

  • Page 175: Chipscope::csejtag_Db Get_Irlength_For_Idcode

    Look in the database for the IR length of the device belonging to IDCODE 01010101010101010101010101010101. %set irlen [::chipscope::csejtag_db get_irlength_for_idcode $handle “01010101010101010101010101010101”] Back to list of all CseJtag Tcl Commands ChipScope Pro Software and Cores User Guide www.xilinx.com UG029 (v14.3) October 16, 2012...
  • Page 176 Extract device information from the file device.bsd that was placed in the buffer of size bsdl_bufLen . bsdl_buf %::chipscope::csejtag_db parse_bsdl $handle “device.bsd” $bsdl_buf $bsdl_bufLen Back to list of all CseJtag Tcl Commands www.xilinx.com ChipScope Pro Software and Cores User Guide UG029 (v14.3) October 16, 2012...

  • Page 177: Chipscope::csejtag_Db Parse_Bsdl_File

    An exception is thrown if the subcommand fails. Example Extract device information from the file device.bsd. %::chipscope::csejtag_db parse_bsdl_file $handle “device.bsd” Back to list of all CseJtag Tcl Commands ChipScope Pro Software and Cores User Guide www.xilinx.com UG029 (v14.3) October 16, 2012...
  • Page 178 The following CseFpga Commands are described in detail in this section: • ::chipscope::csefpga_configure_device • ::chipscope::csefpga_configure_device_with_file • ::chipscope::csefpga_get_config_reg • ::chipscope::csefpga_get_instruction_reg • ::chipscope::csefpga_get_usercode • ::chipscope::csefpga_get_user_chain_count • ::chipscope::csefpga_is_config_supported • ::chipscope::csefpga_is_configured • ::chipscope::csefpga_is_sys_mon_supported • ::chipscope::csefpga_run_sys_mon_command_sequence • ::chipscope::csefpga_get_sys_mon_reg • ::chipscope::csefpga_set_sys_mon_reg www.xilinx.com ChipScope Pro Software and Cores User Guide UG029 (v14.3) October 16, 2012...

  • Page 179: Chipscope::csefpga_Configure_Device

    Use the JTAG SHUTDOWN command to shut down device. For shutdown_sequence shutdown_sequence= Spartan®-3 and Spartan-6 FPGA devices, this option has the true, same effect as "reset_device=true". Default is shutdown_sequence= false "shutdown_sequence=false". ChipScope Pro Software and Cores User Guide www.xilinx.com UG029 (v14.3) October 16, 2012...
  • Page 180 %fconfigure $fp -translation binary -blocking 1 %set fileData [read $fp] %close $fp %set configStatus [::chipscope::csefpga_configure_device $handle 2 "bit" $CSE_DEFAULT_OPTIONS $fileData [file size $filename] "progressCallBack"] Back to list of all CseFpga Tcl Commands www.xilinx.com ChipScope Pro Software and Cores User Guide UG029 (v14.3) October 16, 2012...
  • Page 181 Configure the third device in the JTAG chain with the file mydesign.bit. %set fileName "mydesign.bit" %set configStatus [::chipscope::csefpga_configure_device $handle 2 $fileName $CSE_DEFAULT_OPTIONS "progressCallBack"] Back to list of all CseFpga Tcl Commands ChipScope Pro Software and Cores User Guide www.xilinx.com UG029 (v14.3) October 16, 2012...

  • Page 182: Chipscope::csefpga_Get_Config_Reg

    Read the contents of the configuration register of the third device in the JTAG chain. %set ConfigReg [csefpga_get_config_reg $handle 2 $DeviceBitCount] Back to list of all CseFpga Tcl Commands www.xilinx.com ChipScope Pro Software and Cores User Guide UG029 (v14.3) October 16, 2012...

  • Page 183: Chipscope::csefpga_Get_Instruction_Reg

    Read the contents of the configuration register of the third device in the JTAG chain. %set InstReg [csefpga_get_instruction_reg $handle 2 $DeviceBitCount] Back to list of all CseFpga Tcl Commands ChipScope Pro Software and Cores User Guide www.xilinx.com UG029 (v14.3) October 16, 2012...

  • Page 184: Chipscope::csefpga_Get_Usercode

    Read the contents of the USERCODE register of the third device in the JTAG chain. %set usercode [csefpga_get_usercode $handle 2] Back to list of all CseFpga Tcl Commands www.xilinx.com ChipScope Pro Software and Cores User Guide UG029 (v14.3) October 16, 2012...

  • Page 185: Chipscope::csefpga_Get_User_Chain_Count

    Get the number of USER scan chain registers supported by the device to which $idcode refers. %set numUserRegs [csefpga_get_user_chain_count $handle $idcode] Back to list of all CseFpga Tcl Commands ChipScope Pro Software and Cores User Guide www.xilinx.com UG029 (v14.3) October 16, 2012...

  • Page 186: Chipscope::csefpga_Is_Config_Supported

    An exception is thrown if the command fails. Example Determine if the device referred to by $idcode can be configured. %set isConfigurable [csefpga_is_config_supported $handle $idcode] Back to list of all CseFpga Tcl Commands www.xilinx.com ChipScope Pro Software and Cores User Guide UG029 (v14.3) October 16, 2012...

  • Page 187: Chipscope::csefpga_Is_Configured

    An exception is thrown if the command fails. Example Get the configuration status of the third device in the JTAG chain. %set isConfigured [csefpga_is_configured $handle 2] Back to list of all CseFpga Tcl Commands ChipScope Pro Software and Cores User Guide www.xilinx.com UG029 (v14.3) October 16, 2012...

  • Page 188: Chipscope::csefpga_Is_Sys_Mon_Supported

    Example Determine if the device referred to by $idcode contains a System Monitor block %set hasSysMon [csefpga_is_sys_mon_supported $handle $idcode] Back to list of all CseFpga Tcl Commands www.xilinx.com ChipScope Pro Software and Cores User Guide UG029 (v14.3) October 16, 2012...
  • Page 189 0x10 and read from DRP register address 0x11 . %set hexOutData [csefpga_run_sys_mon_command_sequence $handle 1 [list 10 11] [list 55AA 0000] [list 1 0] 2] Back to list of all CseFpga Tcl Commands ChipScope Pro Software and Cores User Guide www.xilinx.com UG029 (v14.3) October 16, 2012...
  • Page 190 For the second device in the JTAG chain, read the System Monitor register at address 0x07 . %set hexOutData [csefpga_get_sys_mon_reg $handle 1 7] Back to list of all CseFpga Tcl Commands www.xilinx.com ChipScope Pro Software and Cores User Guide UG029 (v14.3) October 16, 2012...
  • Page 191 For the second device in the JTAG chain, write 0xABCD to the System Monitor register at address 0x09 . %csefpga_set_sys_mon_reg $handle 1 9 abcd Back to list of all CseFpga Tcl Commands ChipScope Pro Software and Cores User Guide www.xilinx.com UG029 (v14.3) October 16, 2012...
  • Page 192 Get the number of cores attached to the ICON core in the USER3 register of the third device in the JTAG chain. %set coreCount [csecore_get_core_count $handle 2 3] Back to list of all CseCore Tcl Commands www.xilinx.com ChipScope Pro Software and Cores User Guide UG029 (v14.3) October 16, 2012...
  • Page 193 CseCore Tcl Commands ::chipscope::csecore_get_core_status Retrieves the static status word from the target ChipScope Pro core. Syntax ::chipscope::csecore_get_core_status handle [list deviceIndex userRegNumber coreIndex] bitCount Arguments Table 5-60: Arguments for Subcommand ::chipscope::csecore_get_core_status Argument Type Description Handle to the session that is returned by...
  • Page 194 Required IDCODE for the desired device. idcode Returns Returns 1 if the device referred to by idcode supports ChipScope Pro cores, otherwise returns 0. An exception is thrown if the command fails. Example Determine if device referred to by $idcode supports ChipScope Pro cores...
  • Page 195 • Index for core unit. First core unit connected to ICON has index 0. Tcl array name. After the command is executed coreInfoTclArray successfully, the array contains information described in the Returns section below. ChipScope Pro Software and Cores User Guide www.xilinx.com UG029 (v14.3) October 16, 2012...
  • Page 196 VIO core has. %set coreRef [list 3 2 0] %csevio_get_core_info $handle $coreRef coreInfoTclArray %puts stdout “$coreInfoTclArray($CSEVIO_ASYNC_INPUT_COUNT)” Back to list of all CseVIO Tcl Commands www.xilinx.com ChipScope Pro Software and Cores User Guide UG029 (v14.3) October 16, 2012...
  • Page 197 Determine if the first core connected to ICON core inside fourth device on second USER register is a VIO core %set coreRef [list 3 2 0] %set isVIO [csevio_is_vio_core $handle $coreRef] Back to list of all CseVIO Tcl Commands ChipScope Pro Software and Cores User Guide www.xilinx.com UG029 (v14.3) October 16, 2012...
  • Page 198 Initialize the VIO core connected to ICON core inside fourth device on second USER register is a VIO core %set coreRef [list 3 2 0] %csevio_init_core $handle $coreRef Back to list of all CseVIO Tcl Commands www.xilinx.com ChipScope Pro Software and Cores User Guide UG029 (v14.3) October 16, 2012...
  • Page 199 Terminates the VIO core connected to ICON core inside fourth device on second USER register is a VIO core %set coreRef [list 3 2 0] %csevio_terminate_core $handle $coreRef Back to list of all CseVIO Tcl Commands ChipScope Pro Software and Cores User Guide www.xilinx.com UG029 (v14.3) October 16, 2012...
  • Page 200 0 of the ASYNC_INPUT port: %set coreRef [list 3 2 0] %set csevio_define_signal $handle $coreRef “status_bit” $CSEVIO_ASYNC_INPUT 0 Back to list of all CseVIO Tcl Commands www.xilinx.com ChipScope Pro Software and Cores User Guide UG029 (v14.3) October 16, 2012...
  • Page 201 “ control_bus ” that is assigned to bits 3:0 of the SYNC_OUTPUT port: %set coreRef [list 3 2 0] %set csevio_define_bus $handle $coreRef “control_bus” $CSEVIO_SYNC_OUTPUT [list 0 1 2 3] Back to list of all CseVIO Tcl Commands ChipScope Pro Software and Cores User Guide www.xilinx.com UG029 (v14.3) October 16, 2012...
  • Page 202 SYNC_OUTPUT port: %set coreRef [list 3 2 0] %set csevio_undefine_name $handle $coreRef “control_bus” $CSEVIO_SYNC_OUTPUT Back to list of all CseVIO Tcl Commands www.xilinx.com ChipScope Pro Software and Cores User Guide UG029 (v14.3) October 16, 2012...
  • Page 203 Send a single clock cycle pulse of 1 followed by 0s to the reset signal %set outputTclArray(reset.pulsetrain) 00000000000000000000000000000001 %csevio_write_values $handle $coreRef outputTclArray Back to list of all CseVIO Tcl Commands ChipScope Pro Software and Cores User Guide www.xilinx.com UG029 (v14.3) October 16, 2012...
  • Page 204 A bus called “data_bus” is defined as an 8-bit bus in the ASYNC_INPUT port. Get the values of “ status ” and “ data_bus ” and print them to stdout %csevio_read_values $handle $coreRef inputTclArray www.xilinx.com ChipScope Pro Software and Cores User Guide UG029 (v14.3) October 16, 2012...
  • Page 205 <XILINX_ISE_INSTALL>\cse\tcl\csejtag_example1.tcl The script can be run in the Tcl shell (xtclsh) that is included with Xilinx ISE Design Suite or in the ActiveTcl 8.4 Tcl shell (tclsh) from ActiveState Software Inc. ([See Reference 24, p.
  • Page 206 Other example Tcl scripts (such as the CSE VIO example Tcl script called csevio_example1.tcl) can be found in the same directory as csejtag_example1.tcl. These scripts offer examples of other CSE/Tcl function calls. www.xilinx.com ChipScope Pro Software and Cores User Guide UG029 (v14.3) October 16, 2012...
  • Page 207 ISE® software integration. The purpose of this appendix is to assist you with common errors and issues you might face when using the ChipScope Pro tools. In addition, this appendix provides a general practices for troubleshooting your ChipScope Pro and Xilinx®...
  • Page 208 Appendix A: ChipScope Pro Tools Troubleshooting Guide ChipScope Pro Tools Installation Troubleshooting Common Error Messages/problems that point to issues with a ChipScope Pro tools install are shown in Table A-1. Table A-1: Troubleshooting ChipScope Pro Tools Installation Issues Issue(s) Solution(s) or Work-Around(s)
  • Page 209 Xilinx JTAG Programming Cable Troubleshooting Xilinx JTAG Programming Cable Troubleshooting This section describes how to determine if your Xilinx JTAG programming cable is connected correctly and how to troubleshoot common Xilinx JTAG (Joint Test Action Group, IEEE standard) cable connection issues. Here is a list of issues that are covered in this section: •...
  • Page 210 Appendix A: ChipScope Pro Tools Troubleshooting Guide Table A-2: Verifying Correct Platform Cable USB Connection Issue Solution or Workaround Start the ChipScope Pro Analyzer tool. How can I tell if I am connecting to the Platform Cable USB Select the JTAG Chain menu option.
  • Page 211 Is your cable is plugged into the If NO: Connect the cable and attempt to connect in the ChipScope Pro appropriate USB port? Analyzer tool. If YES: Go to Issue #3.
  • Page 212 Issue(s) Solution(s) or Work-Around(s) Has the correct cable been specified If NO or NOT SURE: In the ChipScope Pro Analyzer tool, check that the at connection? correct cable has been selected in the JTAG Chain menu. Select the correct cable and retry connection.
  • Page 213 If NO or NOT SURE: Use a test instrument to probe the voltage on the connection at the appropriate voltage board to make sure it is in the appropriate range. level? If YES: then open a case with Xilinx Technical Support including the following information: • Xinfo •...
  • Page 214 JTAG operations. If NO: Go to Issue #4. Are non-Xilinx devices in the If YES: Check to make sure that any active-low TRST# pins of these non-Xilinx JTAG chain? devices are pulled high, then try to detect the JTAG chain again.
  • Page 215 Are you running TCK to fast? If YES or NOT SURE: Reduce the speed of the cable using the JTAG Chain > Xilinx Platform USB Cable > Speed option to slow the frequency of the TCK pin to the lowest setting.
  • Page 216 If this does not help, try running the following commands in iMPACT batch mode to clean the stale cable locks: > impact -batch # cleancablelock # exit If NO: Open a case with Xilinx Technical Support including the following information: • Xinfo •...
  • Page 217 This section deals with issues where the ChipScope Pro Analyzer tool can access the cable and the JTAG chain but is either not detecting any debug cores in the Xilinx FPGAs or is having trouble triggering an ILA core or displaying captured ILA core data.
  • Page 218 If NO: Go to Issue #6. Has the device correctly exited from If NO: The ChipScope Pro Analyzer tool might not be able to find the core the device start-up sequence? because the configuration options are not set correctly. If the BitGen option LCK_cycle (or Release DLL in Project Navigator) is not set to "Nowait,"...
  • Page 219 If the core netlist file (*.ngc/ngo) was moved during implementation the associated constraint file (*.ncf) might not have been moved. If YES: Open a case with Xilinx Technical Support including the following information: •...
  • Page 220 To fix this, ensure that you have mapped a valid clock using either the ChipScope Pro Core Inserter tool or in your RTL code (if manually using generated cores). If you are not sure if the clock mapped to the ILA core is running, try to connect your system clock instead (or a clock that you are sure is running).
  • Page 221 If YES or NOT SURE: Reduce the speed of the cable using the JTAG Chain fast? > Xilinx Platform USB Cable > Speed option to slow the frequency of the TCK pin to the lowest setting. If NO: Open a case with Xilinx Technical Support including the following information: •...
  • Page 222 If NO: Simplify the ILA core by reducing the number of trigger ports, timing? number of trigger bits per port, data width, and/or data depth in order to get this design to meet timing again. If YES: Open a case with Xilinx Technical Support including the following information: • cs_analyzer.log •...
  • Page 223 Gathering Information for Xilinx Technical Support Gathering Information for Xilinx Technical Support Obtaining Xinfo Information The Xinfo application is used to collect system info used by Xilinx tools which gives installation logs and environment details that are useful for debug. On Windows Run Start >...
  • Page 224 Appendix A: ChipScope Pro Tools Troubleshooting Guide www.xilinx.com ChipScope Pro Software and Cores User Guide UG029 (v14.3) October 16, 2012...
  • Page 225 PlanAhead™ Design Analysis Tool Xilinx Support System Generator for DSP Xilinx Online Store Silicon Stepping Virtex-5 System Monitor User Guide 22. UG192, 23. UG370, Virtex-6 System Monitor User Guide ChipScope Pro Software and Cores User Guide www.xilinx.com UG029 (v14.3) October 16, 2012...
  • Page 226 Appendix B: References Other references: ActiveState Agilent Technologies Tcl Developer Xchange Byte Tools UG480, 7 Series FPGAs XADC Dual 12-Bit MSPS Analog-to-Digital Converter User Guide www.xilinx.com ChipScope Pro Software and Cores User Guide UG029 (v14.3) October 16, 2012...

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