Cpu Shared Memory Structure - Mitsubishi MELSEC-Q Series User Manual

14
COMMUNICATIONS BETWEEN CPU MODULES

14.3.1 CPU shared memory structure

The following indicates the CPU shared memory structure and accessibility of the C
Controller module.
*1, *6
Area name
Address
0 (0 )
H H
Host CPU operation
information area
1FF (5F )
H H
200 (60 )
H H
System area
7FF (BF )
H H
800 (C0 )
H H
Auto refresh area
User free area
FFF (1FF )
H H
*1 Indicates the address of the CPU shared memory.
*2
Use the QBF ToBuf function to write data to the auto refresh area and user free area of the host CPU (C Controller module).
*3
Use the QBF FromBuf function to read data from the host CPU operation information area, auto refresh area, and user free area of the
host CPU (C Controller module).
*4 Use the QBF FromBuf function to read data from the host CPU operation information area, auto refresh area, and user free area of
another CPU (Programmable controller CPU, Motion CPU).
*5 Refer to the manual of the corresponding CPU module for how to make access from the programmable controller CPU/Motion CPU of
*6 When CPU No. 1 is the Basic model QCPU, the address of the CPU shared memory is the value within the parentheses.
Programmable
controller CPU
Power supply
CPU shared memory
of another CPU
Sequence
program
Figure 14.6 Access diagram
Access from host CPU
Access to host CPU 1)
*2 *3
Write Read
Disabled Enabled
Disabled Disabled
Enabled Enabled
Enabled Enabled
Figure 14.7 Accessibility table
14.3 Data Communications Using CPU Shared Memory
Programmable
controller CPU
Motion CPU
C Controller module
(another CPU)
2) 2)
CPU shared memory
of another CPU
Program
Access to another CPU 2)
*4
Write Read
Disabled Enabled
Disabled Enabled
Disabled Enabled
Disabled Enabled
14.3.1 CPU shared memory structure
C Controller module
(host CPU)
User program
1)
CPU shared memory
of host CPU
3)
Access from another CPU
Access to host CPU 3)
*5
Write Read
Disabled Enabled
Disabled Enabled
Disabled Enabled
Disabled Enabled
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