Page 3 SAFETY PRECAUTIONS (Always read these cautions before using the product) Before using this product, please read this manual and the related manuals introduced in this manual, and pay full attention to safety to handle the product correctly. Please store this manual in a safe place and make it accessible when required. Always forward a copy of the manual to the end user.
Page 4 CONDITIONS OF USE FOR THE PRODUCT (1) Mitsubishi programmable controller ("the PRODUCT") shall be used in conditions; i) where any problem, fault or failure occurring in the PRODUCT, if any, shall not lead to any major or serious accident; and...
Page 5 This manual confers no industrial property rights or any rights of any other kind, nor does it confer any patent licenses. Mitsubishi Electric Corporation cannot be held responsible for any problems involving industrial property rights which may occur as a result of using the contents noted in this manual.
Page 6 INTRODUCTION This document is the MELSEC-Q/L Programming Manual (Common Instructions). It describes the common instructions required for programming of the QCPU and LCPU. • "Common instructions" are all instructions except for dedicated instructions for such intelligent function modules as QJ71C24N and QJ71E71-100; PID control instructions; SFC instructions; ST instructions; instructions for socket communication features;...
Page 7 MEMO...
Page 8: Table Of Contents
CONTENTS SAFETY PRECAUTIONS ........................A - 1 CONDITIONS OF USE FOR THE PRODUCT ..................A - 2 REVISIONS ............................A - 3 INTRODUCTION ..........................A - 4 CONTENTS ............................A - 6 MANUALS............................A - 17 Common Instructions 1/2 1. GENERAL DESCRIPTION 1 - 1 to 1 - 8 Related Programming Manuals 1 - 2 Abbreviations and Generic Names...
Page 9 2.5.11 Character string processing instructions ..............2 - 43 2.5.12 Special function instructions ..................2 - 46 2.5.13 Data control instructions ..................... 2 - 49 2.5.14 Switching instructions ....................2 - 51 2.5.15 Clock instructions ....................... 2 - 52 2.5.16 Expansion clock instruction ..................2 - 55 2.5.17 Program control instructions..................
Page 10 5.1.2 Pulse operation start, pulse series connection, pulse parallel connection (LDP,LDF,ANDP,ANDF,ORP,ORF) ................5 - 5 5.1.3 Pulse NOT operation start, pulse NOT series connection, pulse NOT parallel connection (LDPI,LDFI,ANDPI,ANDFI,ORPI,ORFI) ............... 5 - 7 Association Instructions 5 - 10 5.2.1 Ladder block series connection and parallel connection (ANB,ORB) ......5 - 10 5.2.2 Operation results push,read,pop (MPS,MRD,MPP) ...........
Page 11 6.2.3 BIN 16-bit multiplication and division operations (*(P),/(P))........6 - 30 6.2.4 BIN 32-bit multiplication and division operations (D*(P),D/(P)) ........6 - 32 6.2.5 BCD 4-digit addition and subtraction operations (B+(P),B-(P)) ........6 - 34 6.2.6 BCD 8-digit addition and subtraction operations (DB+(P),DB-(P)) ......6 - 38 6.2.7 BCD 4-digit multiplication and division operations (B*(P),B/(P)) ........
Page 12 6.4.8 Identical 32-bit data block transfers (DFMOV(P))............. 6 - 125 6.4.9 16-bit and 32-bit data exchanges (XCH(P),DXCH(P)) ..........6 - 127 6.4.10 Block 16-bit data exchanges (BXCH(P)) ..............6 - 129 6.4.11 Upper and lower byte exchanges (SWAP(P)) ............6 - 131 Program Branch Instructions 6 - 132 6.5.1...
Page 13 7.4.1 Bit set and reset for word devices (BSET(P),BRST(P)) ..........7 - 59 7.4.2 Bit tests (TEST(P),DTEST(P))..................7 - 61 7.4.3 Batch reset of bit devices (BKRST(P)) ............... 7 - 64 Data processing instructions 7 - 66 7.5.1 16-bit and 32-bit data searches (SER(P),DSER(P))........... 7 - 66 7.5.2 16-bit and 32-bit data checks (SUM(P),DSUM(P)).............
Page 14 7.10 Debugging and failure diagnosis instructions 7 - 174 7.10.1 Special format failure checks (CHKST,CHK) ............7 - 174 7.10.2 Changing check format of CHK instruction (CHKCIR,CHKEND) ......7 - 178 7.11 Character string processing instructions 7 - 182 7.11.1 Conversion from BIN 16-bit or 32-bit to decimal ASCII (BINDA(P),DBINDA(P))..7 - 182 7.11.2 Conversion from BIN 16-bit or 32-bit data to hexadecimal ASCII (BINHA(P),DBINHA(P)) ....................
Page 15 7.12.17 Exponentiation operation on floating-point data (Single precision) (POW(P))..7 - 282 7.12.18 Exponentiation operation on floating-point data (Single precision) (POWD(P)) ..7 - 284 7.12.19 Square root operation for floating-point data (Single precision) (SQR(P)) ....7 - 286 7.12.20 Square root operation for floating-point data (Double precision) (SQRD(P)) ... 7 - 288 7.12.21 Exponent operation on floating-point data (Single precision) (EXP(P))....
Page 16 7.17.2 Program output OFF standby instruction (POFF(P))..........7 - 377 7.17.3 Program scan execution registration instruction (PSCAN(P)) ........7 - 379 7.17.4 Program low speed execution registration instruction (PLOW(P)) ......7 - 381 7.17.5 Program execution status check instruction (PCHK)..........7 - 383 7.18 Other instructions 7 - 385 7.18.1 Resetting watchdog timer (WDT(P)).................
Page 17 11. QCPU INSTRUCTIONS 11 - 1 to 11 - 4 11.1 System Switching Instruction (SP.CONTSW) 11 - 2 12. ERROR CODES 12 - 1 to 12 - 88 12.1 Error Code List 12 - 2 12.1.1 Error codes ......................... 12 - 3 12.1.2 Reading an error code....................
Page 18 INDEX Index - 1 to Index - 10 INDEX Index- 2 INSTRUCTION INDEX Index- 7 A-16...
Page 19 MANUALS To understand the main specifications, functions, and usage of the CPU module, refer to the basic manuals. Read other manuals as well when using a different type of CPU module and its functions. Order each manual as needed, referring to the following list. The numbers in the "CPU module"...
Page 20 Basic manual, :Other CPU module manuals CPU module Manual name Description < Manual number (model code) > ■Programming Manual MELSEC-Q /L Programming Manual (Common How to use sequence instructions, basic instructions, Instructions) and application instructions < SH-080809ENG (13JW10) > System configuration, performance specifications, MELSEC-Q /L/QnA Programming Manual (SFC) functions, programming, debugging, and error codes <...
Page 21 GENERAL DESCRIPTION...
Page 22: Common Instructions
This manual describes the common instructions required for programming of the QCPU and LCPU. "Common instructions" are all instructions except for dedicated instructions for such intelligent function modules as QJ71C24N and QJ71E71-100; PID control instructions; SFC instructions; ST instructions; instructions for socket communication features; trigger logging instructions for the LCPU;...
Page 23 (2) High Performance model QCPU Qn(H)/QnPH/ QnPRHCPU Explains the functions, User's Manual programming methods, (Function Explanation, devices and others that Program are necessary to create Fundamentals) programs with the CPU. This manual MELSEC-Q/L MELSEC-Q/L/ MELSEC-Q/L/ MELSEC-Q/L MELSEC-Q/L Programming QnA Programming QnA Programming Programming Programming...
Page 24 (4) Universal model QCPU QnUCPU Explains the functions, User's Manual programming methods, (Function Explanation, devices and others that Program are necessary to create Fundamentals) programs with the CPU. This manual MELSEC-Q/L MELSEC-Q/L/ MELSEC-Q/L/ MELSEC-Q/L MELSEC-Q/L QnA Programming Programming QnA Programming Programming Programming Manual...
Page 25: Abbreviations And Generic Names
Generic term/Abbreviation Description of Generic Name/Abbreviation ■ Series Q series Abbreviation for Mitsubishi MELSEC-Q series programmable controller L series Abbreviation for Mitsubishi MELSEC-L series programmable controller ■ CPU module type Generic term for Basic model QCPU, High Performance model QCPU, Process CPU,...
Page 26 (Continued) Generic Name/Abbreviation Description of Generic Name/Abbreviation ■ Base unit model Generic term for Q33B, Q35B, Q38B and Q312B main base units on which CPU module (except Q00JCPU), Q series power supply module, Q series I/O module, and intelligent function module can be mounted. Generic term for Q32SB, Q33SB and Q35SB slim type main base units on which Basic model QCPU (except Q00JCPU), High Performance model QCPU, slim type power supply module, Q series I/O module, and intelligent function module can be mounted.
Page 27 (Continued) Generic Name/Abbreviation Description of Generic Name/Abbreviation ■ Others Programing Tool This is a generic name for GX Developer and GX Works2. Product name of Q/L series Corresponding SW D5C-GPPW-type GPP function soft- ware package GX Developer : Version of the software Check the GX Developer versions that can be used for each CPU module in "System Configuration,"...
Page 28 MEMO...
Page 29 INSTRUCTION TABLES...
Page 30: Types Of Instructions
Types of Instructions The major types of CPU module instructions consist of sequence instructions, basic instructions, application instructions, data link instructions, QCPU instructions and redundant system instructions. These types of instructions are listed in Table 2.1 below. Table 2.1 Types of Instructions Reference Types of Instruction Meaning...
Page 31 Table 2.1 Types of Instructions (Continued) Reference Types of Instruction Meaning Chapter Link refresh instruction Designated network refresh Instruction Routing information read/write for Data Link Reads, writes, and registers routing information instruction Multiple Multiple CPU dedicated Writing to host CPU shared memory, Reading from other CPU shared memory dedicated instruction instruction...
Page 32: How To Read Instruction Tables
How to Read Instruction Tables The instruction tables found from Section 2.3 to 2.5 have been made according to the following format: Table 2.2 How to Read Instruction Tables Execution Category Symbol Processing Details ondition (D)+(S) 6-16 16-bit addition subtraction S1 S2 D operations (S1)+(S2)
Page 33 3) ..Shows symbol diagram on the ladder. S1 S2 Indicates destination. Indicates destination. Indicates source. Indicates source. Indicates instruction symbol. Indicates instruction symbol. Fig. 2.1 Symbol Diagram on the Ladder Destination.... Indicates where data will be sent after operation. Source ....Stores data prior to operation. 4) ..Indicates the type of processing that is performed by individual instructions.
Page 34: Sequence Instructions
Sequence Instructions 2.3.1 Contact instructions Table 2.3 Contact Instructions Execution Category Symbol Processing Details Condition • Starts logic operation (Starts a contact logic operation) • Starts logical NOT operation (Starts b contact logic operation) • Logical product (a contact series connection) •...
Page 35: Association Instructions
*2: The number of steps may vary depending on the device and type of CPU module being used. Device Number of Steps Internal device, file register (R0 to R32767) Direct access input (DX) Devices other than above The number of steps may vary depending on the device being used. Device Number of Steps Number of Basic Steps...
Page 36: Output Instructions
2.3.3 Output instructions Table 2.5 Output Instructions Execution Category Symbol Processing Details Condition 5-20 5-22 • Device output 5-26 5-28 5-30 • Sets device 5-35 5-32 • Resets device 5-35 Output • Generates 1 cycle program pulse at leading edge of input signal. 5-37 •...
Page 37: Master Control Instructions
2.3.5 Master control instructions Table 2.7 Master Control Instructions Execution Category Symbol Processing Details Condition • Starts master control Master 5-47 control • Resets master control 2.3.6 Termination instructions Table 2.8 Termination Instructions Execution Category Symbol Processing Details Condition 5-51 FEND •...
Page 38: Basic Instructions
Basic instructions 2.4.1 Comparison operation instructions Table 2.10 Comparison Operation Instructions Execution Category Symbol Processing Details Condition S1 S2 • Conductive status when (S1) (S2) AND= S1 S2 • Non-conductive status when (S1) (S2) S1 S2 LD<> S1 S2 • Conductive status when (S1) (S2) AND<>...
Page 39 Table 2.10 Comparison Operation Instructions (Continued) Execution Category Symbol Processing Details Condition LDD= S1 S2 • Conductive status when ANDD= (S1+1, S1) (S2+1, S2) S1 S2 • Non-Conductive status when (S1+1, S1) (S2+1, S2) ORD= S1 S2 LDD<> S1 S2 •...
Page 40 Table 2.10 Comparison Operation Instructions (Continued) Execution Category Symbol Processing Details Condition LDE= S1 S2 • Conductive status when ANDE= (S1+1, S1) (S2+1, S2) S1 S2 • Non-Conductive status when (S1+1, S1) (S2+1, S2) ORE= S1 S2 LDE<> S1 S2 •...
Page 41 Table 2.10 Comparison Operation Instructions (Continued) Execution Category Symbol Processing Details Condition • Conductive status when LDED= S1 S2 (S1+3, S1+2, S1+1, S1) ANDED= (S2+3, S2+2, S2+1, S2) S1 S2 • Non-Conductive status when (S1+3, S1+2, S1+1, S1) ORED= S1 S2 (S2+3, S2+2, S2+1, S2) •...
Page 42 Table 2.10 Comparison Operation Instructions (Continued) Execution Category Symbol Processing Details Condition • Compares character string S1 and LD$= S1 S2 character string S2 one character at a time. *2 AND$= S1 S2 • Conductive status when (character string S1) (character string S2) •...
Page 43 Table 2.10 Comparison Operation Instructions (Continued) Execution Category Symbol Processing Details Condition BKCMP= BKCMP S1 S2 D BKCMP<> BKCMP S1 S2 D BKCMP> BKCMP S1 S2 D BKCMP<= BKCMP S1 S2 D • This instruction compares BIN 16-bit BKCMP< BKCMP S1 S2 D data stored in n-point devices starting BIN 16-bit...
Page 44: Arithmetic Operation Instructions
2.4.2 Arithmetic operation instructions Table 2.11 Arithmetic Operation Instructions Execution Category Symbol Processing Details Condition 6-22 • (D)+(S) S1 S2 D 6-24 • (S1)+(S2) BIN 16-bit S1 S2 D addition and subtraction operations 6-22 • (D) S1 S2 D 6-24 •...
Page 45 *1: The number of steps may vary depending on the device and type of CPU module being used. Number of Component Device Steps • Word device: Internal device (except for file register ZR) • Bit device: Devices whose device Nos. are multiples of 16, whose digit High Performance model QCPU Note 1) designation is K8, and which use no indexing.
Page 46 Table 2.11 Arithmetic Operation Instructions (Continued) Execution Category Symbol Processing Details Condition 6-34 • (D)+(S) S1 S2 D BCD 4-digit 6-36 • (S1)+(S2) addition S1 S2 D subtraction 6-34 • (D) operations S1 S2 D 6-36 • (S1) (S2) S1 S2 D 6-38 •...
Page 47 Table 2.11 Arithmetic Operation Instructions (Continued) Execution Category Symbol Processing Details Condition 6-46 • (D+1, D)+(S+1, S) (D+1, D) Floating decimal S1 S2 D point data 6-48 • (S1+1, S1)+(S2+1, S2) (D+1, D) addition S1 S2 D subtraction 6-46 • (D+1, D) (S+1, S) (D+1, D) operations...
Page 48 Table 2.11 Arithmetic Operation Instructions (Continued) Execution Category Symbol Processing Details Condition • This instruction adds BIN 16-bit data S1 S2 stored in n-point devices starting from the BIN 16-bit device specified by (S1) to the n-point data data block BK+P stored in the devices starting from the BK+P...
Page 49 *7: The number of steps may vary depending on the device and type of CPU module being used. Number of Component Device Steps • Word device: Internal device (except for file register ZR) • Bit device: Devices whose device Nos. are multiples of 16, whose digit High Performance model QCPU Note 1) designation is K8, and which use no indexing.
Page 50: Data Conversion Instructions
2.4.3 Data conversion instructions Table 2.12 Data Conversion Instructions Execution Category Symbol Processing Details Condition BCD conversions BCDP BCDP BIN (0 to 9999) 6-74 conversions DBCD DBCD BCD conversions (S+1, S) (D+1, D) DBCDP BIN (0 to 99999999) DBCDP BIN conversions BINP BINP BCD (0 to 9999)
Page 51 Table 2.12 Data Conversion Instructions (Continued) Execution Category Symbol Processing Details Condition Conversion (D+1, D) 6-89 16-bit DBLP BIN (-32768 to 32767) DBLP WORD WORD 32-bit Conversion 6-90 (S+1, S) conversion WORDP WORDP BIN (-32768 to 32767) Conversion to gray code GRYP BIN (-32768 to 32767) GRYP...
Page 52: Data Transfer Instructions
2.4.4 Data transfer instructions Table 2.13 Data Transfer Instructions Execution Category Symbol Processing Details Condition 16-bit data ( D ) transfer MOVP MOVP 6-107 DMOV DMOV 32-bit data (D+1,D) (S+1,S) transfer DMOVP DMOVP Floating EMOV EMOV decimal point data (S+1, S) (D+1, D) 6-109 transfer...
Page 53 Table 2.13 Data Transfer Instructions (Continued) Execution Category Symbol Processing Details Condition BXCH BXCH Block data 6-129 exchange BXCHP BXCHP Exchange b15 to b8 b7 SWAP SWAP 8 bits 8 bits of upper 6-131 and lower SWAPP b15 to b8 b7 SWAPP bytes 8 bits...
Page 54 *3: The number of steps may vary depending on the device and type of CPU module being used. Number of Component Device Steps • Word device: Internal device (except for file register ZR) • Bit device: Devices whose device Nos. are multiples of 16, whose digit QCPU designation is K4, and which use no indexing.
Page 55: Program Branch Instructions
2.4.5 Program branch instructions Table 2.14 Program Branch Instructions Execution Category Symbol Processing Details Condition • Jumps to Pn when input conditions are met. • Jumps to Pn from the scan after the 6-132 meeting of input condition. Jump • Jumps unconditionally to Pn. •...
Page 56: Other Convenient Instructions
2.4.8 Other convenient instructions Table 2.17 Other convenient instructions Execution Category Symbol Processing Details Condition (S)+0 Down (S)+1 6-147 UDCNT1 UDCNT1 Present Cn value 1 2 3 4 6 7 6 5 3 2 1 0 -1 -2 -3 -2 -1 0 Cn contact Up/Down counter...
Page 57: Application Instructions
Application Instructions 2.5.1 Logical operation instructions Table 2.18 Logical Operation Instructions Execution Category Symbol Processing Details Condition WAND WAND WANDP WANDP WAND WAND S1 S2 D (S1) (S2) WANDP WANDP S1 S2 D DAND DAND Logical (D+1,D) (S+1,S) (D+1,D) product DANDP DANDP DAND...
Page 58 Table 2.18 Logical Operation Instructions (Continued) Execution Category Symbol Processing Details Condition DXOR DXOR S1 S2 D 7-22 (S2+1,S2) (D+1,D) (S1+1,S1) DXORP DXORP S1 S2 D Exclusive BKXOR (S1) (S2) BKXOR S1 S2 D 7-25 BKXORP BKXORP S1 S2 D WXNR WXNR 7-27...
Page 59 *1: The number of basic steps is three for the Universal model QCPU and LCPU only. *2: The number of steps may vary depending on the device and type of CPU module being used. Number of Component Device Steps • Word device: Internal device (except for file register ZR) •...
Page 60: Rotation Instructions
2.5.2 Rotation instructions Table 2.19 Rotation Instructions Execution Category Symbol Processing Details Condition SM700 RORP RORP Right rotation by n bits Carry flag Right 7-35 rotation SM700 RCRP RCRP Right rotation by n bits Carry flag SM700 ROLP ROLP Carry flag Left rotation by n bits Left 7-38...
Page 61: Shift Instructions
2.5.3 Shift instructions Table 2.20 Shift Instructions Execution Category Symbol Processing Details Condition Carry flag SFRP b0 SM700 SFRP n-bit shift 0 to 0 of 16-bit 7-46 data Carry flag SFLP SM700 SFLP 0 to 0 BSFR BSFR Carry flag SM700 BSFRP BSFRP...
Page 62: Bit Processing Instructions
2.5.4 Bit processing instructions Table 2.21 Bit Processing Instructions Execution Category Symbol Processing Details Condition BSET BSET BSETP BSETP 7-59 set/reset BRST BRST BRSTP BRSTP (S1) TEST TEST S1 S2 D TESTP TESTP S1 S2 D Bit designated by (S2) Bit tests 7-61 DTEST...
Page 63: Data Processing Instructions
2.5.5 Data processing instructions Table 2.22 Data Processing Instructions Execution Category Symbol Processing Details Condition (S2) (S1) S1 S2 D (D): Match No. SERP SERP S1 S2 D (D + 1): Number of matches Data 7-66 searches 32 bits DSER DSER S1 S2 D (S2)
Page 64 Table 2.22 Data Processing Instructions (Continued) Execution Category Symbol Processing Details Condition • Separates 16-bit data designated by (S) into 4-bit units, and stores at the lower 4 7-77 DISP bits of n points from (D). (n DISP • Links the lower 4 bits of n points from the device designated by (S) and stores at the 7-79 UNIP...
Page 65 Table 2.22 Data Processing Instructions (Continued) Execution Category Symbol Processing Details Condition S1 n SORT S2 D1 • Sorts data of n points from device · S2: Number of comparisons to be SORT made during a single run designated by (S1) in 16-bit units. ·...
Page 66: Structure Creation Instructions
2.5.6 Structure creation instructions Table 2.23 Structure Creation Instructions Execution Category Symbol Processing Details Condition • Executes n times between the 7-105 NEXT NEXT NEXT Number of repeats BREAK BREAK • Forcibly ends the execution of the 7-108 NEXT cycle and jumps pointer Pn. BREAKP BREAKP CALL...
Page 67 Table 2.23 Structure Creation Instructions (Continued) Execution Category Symbol Processing Details Condition EFCALL EFCALL • Performs non-execution processing of EFCALL Pn S1toSn subroutine program Pn if input :File name conditions have not been met. (S1 to 7-125 Sn are arguments sent to subroutine EFCALLP program.
Page 68: Data Table Operation Instructions
2.5.7 Data table operation instructions Table 2.24 Data table Operation Instructions Execution Category Symbol Processing Details Condition Pointer Pointer + 1 FIFW FIFW 7-150 FIFWP Device at FIFWP pointer + 1 (S) Pointer Pointer - 1 FIFR FIFR 7-152 FIFRP FIFRP (S) Pointer Pointer - 1...
Page 69 2.5.8 Buffer memory access instructions Table 2.25 Buffer Memory Access Instructions Execution Category Symbol Processing Details Condition FROM FROM n1 n2 D • Reads data in 16-bit units from an intelligent function module. FROMP FROMP n1 n2 D Data read 7-159 DFRO DFRO...
Page 70: Debugging And Failure Diagnosis Instructions
2.5.10 Debugging and failure diagnosis instructions Table 2.27 Debugging and Failure Diagnosis Instructions Execution Category Symbol Processing Details Condition • The CHK instruction is executed when CHKST is executable. • Jumps to the step following the CHK CHKST CHKST instruction when CHKST is in a non-executable status.
Page 71: Character String Processing Instructions
2.5.11 Character string processing instructions Table 2.28 Character String Processing Instructions Execution Category Symbol Processing Details Condition • Converts 1-word BIN value designated BINDA BINDA by (S) to a 5-digit, decimal ASCII value, and stores it at the word device BINDAP BINDAP designated by (D).
Page 72 Table 2.28 Character String Processing Instructions (Continued) Execution Category Symbol Processing Details Condition • Converts a 4-digit, decimal ASCII value DABCD DABCD designated by (S) to a 1-word BCD Decimal value, and stores it at a word device DABCDP DABCDP ASCII number designated by (D).
Page 73 Table 2.28 Character String Processing Instructions (Continued) Execution Category Symbol Processing Details Condition • Converts the 1-word BIN value at the Hexadecimal device numbers designated by (S) to 7-227 hexadecimal ASCII, and stores n characters of them at the device numbers ASCP ASCP ASCII...
Page 74: Special Function Instructions
2.5.12 Special function instructions Table 2.29 Special Function Instructions Execution Category Symbol Processing Details Condition 7-249 Sin (S+1,S) (D+1,D) SINP SINP 7-253 (D+1,D) Cos (S+1,S) COSP COSP Trigonometric 7-257 Tan(S+1,S) (D+1,D) functions TANP TANP (Floating- ASIN point single- ASIN 7-261 (S+1,S) (D+1,D) precision)
Page 75 Table 2.29 Special Function Instructions (Continued) Execution Category Symbol Processing Details Condition (S+1, S) (D+1, D) 7-274 Conversion from angles to radians RADP RADP RADD RADD (D+3, D+2, D+1, D) (S+3, S+2, S+1, S) 7-276 Angles Conversion from angle to radian RADDP RADDP Radians...
Page 76 Table 2.29 Special Function Instructions (Continued) Execution Category Symbol Processing Details Condition • Generates a random number (from 0 to Random number less than 32767) and stores it at the RNDP RNDP device designated by (D). generation 7-303 Random • Updates random number series SRND SRND according to the 16-bit BIN data stored...
Page 77: Data Control Instructions
2.5.13 Data control instructions Table 2.30 Data Control Instructions Execution Category Symbol Processing Details Condition • When (S3) (S1) LIMIT LIMIT S1 S2 ..Stores value of (S1) at (D) • When (S1) (S3) (S2) ..Stores value of (S3) at (D) •...
Page 78 Table 2.30 Special Function Instructions (Continued) Execution Category Symbol Processing Details Condition • Executes scaling for the scaling conversion data (16-bit data units) S1 S2 D specified by (S2) with the input value specified by (S1), and then stores the result into the device specified by (D).
Page 79: Switching Instructions
2.5.14 Switching instructions Table 2.31 Switching Instructions Execution Category Symbol Processing Details Condition Block RSET RSET • Converts extension file register block number 7-336 number to number designated by (S). switching RSETP RSETP QDRSET QDRSET File name • Sets file names used as file registers. 7-338 QDRSETP File name QDRSETP...
Page 80: Clock Instructions
2.5.15 Clock instructions Table 2.32 Clock Instructions Execution Category Symbol Processing Details Condition (Clock elements) (D) +0 Year DATERD DATERD D Month 7-343 Hour Minute DATERDP DATERDP D Sec. Read/ Day of the week write clock (D) +0 (Clock elements) Year data DATEWR...
Page 81 Table 2.32 Character String Processing Instructions (Continued) Execution Category Symbol Processing Details Condition LDDT= S1 S2 n Year Year ANDDT= S1 S2 Companson Month Month operation resuit ORDT= S1 S2 LDDT<> S1 S2 n Year Year ANDDT<> S1 S2 n Companson Month Month...
Page 82 Table 2.32 Character String Processing Instructions (Continued) Execution Category Symbol Processing Details Condition LDTM= S1 S2 n Hour Hour ANDTM= S1 S2 Companson Minute Minute operation resuit Second Second ORTM= S1 S2 LDTM<> S1 S2 n Hour Hour ANDTM<> S1 S2 n Companson Minute Minute...
Page 83: Expansion Clock Instruction
2.5.16 Expansion clock instruction Table 2.33 Expansion clock instruction Execution Category Symbol Processing Details Condition (Clock elements) (D) +0 Year S.DAT- S.DATERD D Month Reading data of the Hour 7-365 Minute expan- Sec. SP.DAT- sion clock Day of the week SP.DATERD D 1/1000 sec.
Page 84: Program Control Instructions
2.5.17 Program control instructions Table 2.34 Program Control Instructions Execution Category Symbol Processing Details Condition PSTOP PSTOP File name • Places designated program in standby 7-376 status. PSTOPP PSTOPP File name POFF POFF File name • Turns OUT instruction coil of designated program OFF, and places program in 7-377 standby status.
Page 85: Other Instructions
2.5.18 Other instructions Table 2.35 Other Instructions Execution Category Symbol Processing Details Condition • Resets watchdog timer during sequence 7-385 reset program. WDTP WDTP Timing n1 scans n2 scans 7-387 DUTY DUTY n1 n2 D clock SM420 to SM424, SM430 to SM434 •...
Page 86 Table 2.35 Other Instructions (Continued) Execution Category Symbol Processing Details Condition • This instruction reads the module TYPERD TYPERD information stored in the area starting from Module model 7-408 the I/O number specified by "n", and stores name read it in the area starting from the device TYPERDP TYPERDP specified by (D).
Page 87: Instructions For Data Link
Instructions for Data Link 2.6.1 Instructions for Network refresh Table 2.36 Instructions for Network refresh Execution Category Symbol Processing Details Condition S.ZCOM S.ZCOM Link instruc- SP.ZCOM SP.ZCOM Jn tion: Net- Refreshes the designated network. S.ZCOM work refresh S.ZCOM SP.ZCOM SP.ZCOM Un 2.6.2 Instructions for Reading/Writing Routing Information Table 2.37 Instructions for Reading/Writing Routing Information...
Page 88: Multiple Cpu Dedicated Instruction
Multiple CPU dedicated instruction 2.7.1 Instructions for Writing to the CPU Shared Memory of Host Table 2.38 Instructions for Writing to the CPU Shared Memory of Host CPU Execution Category Symbol Processing Details Condition S. TO S.TO • Writes device data of the host station to the host CPU shared memory.
Page 89: Multiple Cpu High-Speed Transmission Dedicated Instruction
Multiple CPU high-speed transmission dedicated instruction 2.8.1 Instructions for Multiple CPU high-speed transmission dedicated Table 2.40 Multiple CPU high-speed transmission dedicated instruction Execution Category Symbol Processing Details Condition In multiple CPU system, data stored in a D.DDWR D.DDWR device specified by host CPU ( ) or later is Writing Devices stored by the number of write points specified...
Page 90: Redundant System Instructions (For Redundant Cpu)
Redundant system instructions (For Redundant CPU) 2.9.1 Instructions for Redundant system (For Redundant CPU) Table 2.41 Redundant System Instructions (For Redundant CPU) Execution Category Symbol Processing Details Condition Switches between the control system and System standby system at the END processing of the SP.CONTSW 11-2 SP.CONTSW S D...
Page 91 CONFIGURATION OF INSTRUCTIONS...
Page 92: Configuration Of Instructions
Configuration of Instructions Most CPU module instructions consist of an instruction part and a device part. Each part is used for the following purpose: • Instruction part ..indicates the function of the instruction. • Device part .... indicates the data that is to be used with the instruction. The device part is classified into source data, destination data, and number of devices.
Page 93: Designating Data
Designating Data The following six types of data can be used with CPU module instructions....... Section 3.2.1 Data that can be handled by Bit data CPU module .......Section 3.2.2 Numeric data Integer data Word data ...Section 3.2.3 Double-word data Real number ..
Page 94: Using Word (16 Bits) Data
3.2.2 Using word (16 bits) data Word data is 16-bit numeric data used by basic instructions and application instructions. The following two types of word data can be used with CPU module: • Decimal constants....K-32768 to K32767 • Hexadecimal constants ..H0000 to HFFFF Word devices and bit devices designated by digit can be used as word data.
Page 95 (c) When destination (D) data is a word device The word device for the destination becomes 0 following the bit designated by digit designation at the source. Ladder Example Processing With 16-Bit Instruction K1X0 X3 X2 X1 X0 X010 Filled with 0s MOV K1X0 0 0 0 0 0 0 0 0 0 0 X2 X1 X0...
Page 96: Using Double Word Data (32 Bits)
3.2.3 Using double word data (32 bits) Double word data is 32-bit numerical data used by basic instructions and application instructions. The two types of double word data that can be dealt with by CPU module are as follows: • Decimal constants....K-2147483648 to K2147483647 •...
Page 97 (c) When destination (D) data is a word device The word device for the destination becomes 0 following the bit designated by digit designation at the source. Ladder Example Processing With 32 bit Instructions K1X0 X3 X2 X1 X0 Filled with 0s DMOV K1X0 0 0 0 0 0 0 0 0 0 0 X2 X1 X0...
Page 98: Using Real Number Data
(2) Using word devices A word device designates devices used by the lower 16 bits of data. A 32-bit instruction uses (designation device number) and (designation device number + 1). DMOV K100 Designation of 2 points of word devices D0 and D1 (32 bits) 32-bit data transfer instruction 3.2.4 Using real number data...
Page 99 • Variable part The 23 bits from b0 to b22, represents the XXXXXX... at binary 1.XXXXXX..(2) Double-precision floating-point data Instructions which deal with double-precision floating-point datadesignate devices which are used for the lower 16 bits of data. Double-precision floating-point data are stored in the 64 bits which make up (designated device number) to (designated device number + 3).
Page 100 1. The CPU module floating decimal point data can be monitored using the monitoring function of a peripheral device. 2. When floating-point data is used to express 0, all data in the following range are turned to 0. (a) Single-precision floating-point data: b0 to b31 (b) Double-precision floating-point data: b0 to b63 3.
Page 101: Using Character String Data
3.2.5 Using character string data Character string data is character data used by basic instructions and application instructions. The target ranges from the designated character to the NULL code (00 ) that indicates the end of the character string. (1) When designated character is the NULL code One word is used to store the NULL code.
Page 102: Indexing
Indexing (1) Overview of indexing (a) Indexing is an indirect setting made by using an index register. When an Indexing is used in a sequence program, the device to be used will become the device number specified directly plus the contents of the index register. For example, if D2Z2 has been specified, the specified device is calculated as follows: D(2+3) = D5 and the content of Z2 is 3 become the specified device.
Page 103 2) Devices with limits for use with index registers Device Meaning Application Example T0Z0 K100 • Only Z0 and Z1 can be used for T1Z1 timer contacts and coils. C0Z1 K100 • Only Z0 and Z1 can be used for C1Z0 counter contacts and coils.
Page 104 • Specifing the 32-bit indexing using “ZZ” specification. 32-bit indexing with the "ZZ" specification is only available for the following CPU modules. See the programming tool operating manual for the available programming tools. • The first five digits of the serial No. for QnU(D)(H)CPU is “10042” or higher. (excluding Q00UJCPU) •...
Page 105 3) Device that indexing can be used Indexing can be used only for the device shown below. Device Meaning Serial number access format file register Extended data register (D) Extended link register (W) 4) Usable range of index registers The following table shows the usable range of index registers for indexing with 32-bit index registers.
Page 106 (b) Example of specifing 32-bit indexing with “ZZ” specification. 1) One index register can specify 32-bit indexing by using “ZZ” specification such as “ZR0ZZ4”. The 32-bit indexing with “ZZ” specification is as follows. Stores 100000 at Z4 and Z5. DMOVP K100000 Indexing ZR device with 32-bit MOVP...
Page 107: Index
5) The 32-bit indexing used “ZZ” specification and the acutual processing device are as follows. (Z0 (32-bit) 100000.Z2 (16-bit) Ladder Example Actual Process Device ZR101000 D10 DMOV K100000 Z0 K-20 Description ZR1000ZZ0 D30Z2 ZR1000ZZ0 ZR(1000+100000)=ZR101000 D30Z2 D(30-20)=D10 Fig.3.10 Ladder Example and Actual Process Device 6) Available functions for “ZZ”...
Page 108 (4) Index modification using extended data register (D) and extended link register (W) (Universal model QCPU (excluding Q00UJCPU) and LCPU) Like index modification using data register (D) and link register (W) of internal user device, a device can be specified by index modification within the range of the extended data register (D) and extended link register (W).
Page 109 2) Index modification where the device number crosses over the boundary among the file register (ZR), extended data register (D), and extended link register (W) Index modification where the device number crosses over the boundary among the file register (ZR), extended data register (D), and extended link register (W) will not cause an error.
Page 110 (5) Other index modifications (a) Bit data Device numbers can be index modified when performing digit designation. However, Indexing is not possible by digit designation. BIN K4X0Z2 Setting is possible since this indicates Indexing for device number. If Z2=3, then (X0+3)=X3 BIN K4Z3X0 Setting is not possible since this indicates Indexing by digit designation.
Page 111 (e) Index modification using extended data register (D) and extended link register (W) by 32 bits (Universal model QCPU(except Q00UJCPU) and LCPU.) Like index modification using file register (ZR), index modification using extended data register (D) and extended link register (W) by 32 bits can be performed by the following two methods.
Page 112 (b) Performing indexing with the CALL instruction Pulses can be output with the CALL instruction by use of the edge relay (V). However, pulse output using the PLS/PLF/pulse ( P) instruction is not allowed. [When edge relay is used] [When edge relay is not used] (M0Z1 provides normal pulse output.) (M0Z1 does not provide normal pulse output.) SM400...
Page 113: Indirect Specification
Indirect Specification (1) Indirect Specification (a) Indirect specification is a method that specifies address of the device to be used in a sequence program using two word devices (two points of word device). Use indirect specification as index modification when the index register is insufficient. Stores the address of ADRSET D100...
Page 114 (3) Precautions (a) The address for indirect specification uses two words.Therefore, to substitute indirect specification for index modification, the addition/subtraction of 32-bit data is required. The following is the ladder used for the address addition/subtraction of the device stored in D1 and D0 for indirect specification. [To add "1"...
Page 115: Reducing Instruction Processing Time
Reducing Instruction Processing Time 3.5.1 Subset Processing Subset processing is used to place limits on bit devices used by basic instructions and application instructions in order to increase processing speed. However, the instruction symbol does not change. To shorten scans, run instructions under the conditions indicated below. (1) Conditions which each device must meet for subset processing (a) When using word data Device...
Page 116: Operation Processing With Standard Device Registers (Z) (Universal Model Qcpu And Lcpu Only)
(2) Instructions for which subset processing can be used Types of Instructions Instruction Symbols LD,LDI,AND,ANI,OR,ORI,LDP,LDF,ANDP,ANDF,ORP,ORF,LDPI,ANDPI,ANDFI, Contact instructions ORPI,ORFI Output instructions OUT,SET,RST Comparison operation instruction • • +, ,*,/,INC,DEC,D+,D ,D*,D/,DINC,DDEC Arithmetic operation • B+,B ,B*,B/, E+,E ,E*,E/ Data conversion instructions • BCD, BIN, DBCD, DBIN, FLT, DFLT, INT, DINT •...
Page 117: Cautions On Programming (Operation Errors)
Cautions on Programming (Operation Errors) Operation errors are returned in the following cases when executing basic instructions and application instructions with CPU module: • An error listed on the explanatory page for the individual instruction occurred. • When an intelligent function module device is used, no intelligent function module is installed at the specified I/O number position.
Page 118 2) Universal model QCPU and LCPU The device range is checked. When the device number is outside the device range, an operation error occurs. For example, when12 k points are assigned to a data register, an error occurs if the device number of the data register exceeds D12287. DMOV K100 D12287 When D12287 is specified with the DMOV instruction,...
Page 119 2) Universal model QCPU and LCPU The device range is checked. When the device number is outside the device range, an operation error occurs. For example, when12 k points are assigned to a data register, an error occurs if the device number of the data register exceeds D12287. BMOV D0 D12287 When D12287 is specified with the BMOV instruction,...
Page 120 When performing the following access in Universal model QCPU or LCPU, an error (error code: 4101) occurs. 1) Access crossing the boundary of devices caused by indexing (range of A area) The allocation order of individual devices is shown below: Area A Contact and coil of T Contact and coil of ST...
Page 121 Remark For how to change the internal user device allocation, refer to the User’s Manual (Functions Explanation, Program Fundamentals) for the CPU module used. (d) Device range checks are conducted when indexing is performed by direct access output (DY). (e) Precautions for using the extended data register (D) or extended link register (W) (for the Universal model QCPU except the Q00UJCPU, and LCPU ) With the following specification methods, data cannot be specified crossing over the boundary of the internal user device and extended data register (D) or extended link...
Page 122 (2) Device data check Device data checks for the devices used by basic instructions and application instructions in CPU module are as indicated below: (a) When using BIN data No error is returned even if the operation results in overflow or underflow. The carry flag does not go on at such times, either.
Page 123: Conditions For Execution Of Instructions
Conditions for Execution of Instructions The following four types of execution conditions exist for the execution of CPU module sequence instructions, basic instructions, and application instructions: • Non-conditional execution..Instructions executed without regard to the ON/OFF status of the device Example LD X0, OUT Y10 •...
Page 124: Counting Step Number
Counting Step Number The number of steps in CPU module sequence instructions, basic instructions, and application instructions differs depending on whether indirect setting of the device used is possible or not. (1) Counting the number of basic steps The basic number of steps for basic instructions and application instructions is calculated by adding the device number and 1.
Page 125 (c) Devices with additional steps (Universal model QCPU(except Q00UJCPU) and LCPU) 1) Instructions applicable to subset processing The following table shows steps depending on the devices. Added Steps Basic Number of Instruction Symbols Devices with Additional Steps (Number of Steps Instruction Steps) Serial number access format file register, Extended data register (D),...
Page 126 Added Steps Basic Number of Instruction Symbols Devices with Additional Steps (Number of Steps Instruction Steps) Standard device register * +,-,+P,-P,WAND,WOR,WXOR,WXNR, Serial number access format file register WANDP,WORP,WXORP,WXNRP Extended data register (D), (2 devices) Extended link register (W) Multiple CPU shared device* Standard device register * Serial number access format file register D+,D-,D+P,D-P,DAND,DOR,DXOR,DXNR,...
Page 127 Added Steps Basic Number of Instruction Symbols Devices with Additional Steps (Number of Steps Instruction Steps) Index register/Standard device register * Serial number access format file register INC,INCP,DEC,DECP,DINC,DINCP, Extended data register (D), DDEC,DDECP Extended link register (W) Multiple CPU shared device* Serial number access format file register Extended data register (D), MOV,MOVP...
Page 128 Added Steps Locations Where Standard Device Regis- Basic Number of Instruction Symbols (Number of ter Is Used Steps Instruction Steps) -2(1) , and -1(2) +,-,+P,-P,D+,D-,D+P,D-P, WAND,WOR,WXOR,WXNR, (only when that device that the ± DAND,DOR,DXOR,DXNR, 0(3) number of steps does not increase is WANDP,WORP,WXORP,WXNRP, DANDP,DORP,DXORP,DXNRP specified for...
Page 129 Example MOV If U1 G10 ZR123 has been designated, a total of 2 steps are added. ZR123 Serial number access format file registers : 1 step : 1 step Intelligent function module devices Increased by 2 steps 3-39...
Page 130: Operation When The Out, Set/Rst, Or Pls/Plf Instructions Use The Same Device
Operation when the OUT, SET/RST, or PLS/PLF Instructions Use the Same Device The following describes the operation for executing multiple instructions of the OUT, SET/RST, or PLS/PLF that use the same device in one scan. (1) OUT instructions using the same device Do not program more than one OUT instruction using the same device in one scan.
Page 131 (2) SET/RST instructions using the same device (a) The SET instruction turns ON the specified device when the execution command is ON and performs nothing when the execution command is OFF. For this reason, when the SET instructions using the same device are executed two or more times in one scan, the specified device will be ON if any one of the execution commands is ON.
Page 132 (3) PLS instructions using the same device The PLS instruction turns ON the specified device when the execution command is turned ON from OFF. It turns OFF the device at any other time (OFF to OFF, ON to ON, or ON to OFF). If two or more PLS instructions using the same device are executed in one scan, each instruction turns ON the device when the corresponding execution command is turned ON from OFF and turns OFF the device in other cases.
Page 133 • The X0 and X1 turn ON from OFF at the same time. M0 turns OFF because X1 status is M0 turns ON because X1 other than OFF goes ON (OFF ON). (M0 remains ON.) (M0 remains OFF.) M0 turns ON because M0 turns OFF because X0 status is other X0 goes ON (OFF than OFF...
Page 134 [Timing Chart] • The ON/OFF timing of the X0 and X1 is different. (The specified device does not turn ON throughout the scan.) M0 turns OFF because X1 status is M0 turns OFF because X1 other than ON status is other than ON OFF.
Page 135: Precautions For Use Of File Registers
3.10 Precautions for Use of File Registers This section explains the precautions for use of the file registers in the QCPU and LCPU. (1) CPU modules that cannot use file registers The Q00JCPU and Q00UJCPU cannot use the file registers. When using the file registers, use the CPU module of other than the Q00JCPU and Q00UJCPU.
Page 136 Remark For the file register setting method and file register area securing method, refer to User’s Manual (Functions Explanation, Program Fundamentals) for the CPU module used. (4) Designation of file register number in excess of the registered number of points (a) Basic Model QCPU, High Performance model QCPU, Process CPU, and Redundant An error will not occur if data are written or read to or from the file registers that have numbers greater than the registered number of points.
Page 137 (b) Serial number access method In the serial number access method, specify the file registers beyond 32k points with consecutive device numbers. The file registers of multiple blocks can be used as consecutive file registers. Use "ZR" as the device name. Standard RAM/Memory card ZR32768 (Block 0)
Page 138 3) When a block number is switched by the RSET instruction, refresh is performed to the data of the file register (R) in the switched block number. When a block number is switched by the RSET instruction, refresh is performed to the data of the file register (R) in the block number at the time of the END instruction execution.
Page 139 HOW TO READ INSTRUCTIONS...
Page 140 The description of instructions that are contained in the following chapters are presented in the following format. 1) Code used to write instruction (instruction symbol). 2) Section number and general category of instructions described. 3) Shows if instructions are enabled or disabled for each CPU module type. Icon Meaning Basic model...
Page 141 4) Indicates ladder mode expressions and execution conditions for instructions. Non-conditional Executed One Time Executed One Execution Condition Executed while ON Executed while OFF Execution at ON Time at OFF Code recorded on No symbol description page recorded 5) Indicates the data set for each instruction and the data type. Data Type Meaning Bit data or head number in bit data...
Page 142 6) Devices which can be used by the instruction in question are indicated with circle. The types of devices that can be used are as indicated below: Link direct device *4 *6 Intelligent Internal Devices File function (System, User) Index register Setting Data Register Constant *5...
Page 143 SEQUENCE INSTRUCTIONS Reference Category Processing Details Section Contact instruction Operation start, series connection, parallel connection Section 5.1 Ladder block connection, creation of pulses from operation Section 5.2 Association instruction results, store/read operation results Output instruction Bit device output, pulse output, output reversal Section 5.3 Section 5.4 Shift instruction...
Page 144: Contact Instructions
LD,LDI,AND,ANI,OR,ORI Contact Instructions 5.1.1 Operation start, series connection, parallel connection (LD,LDI,AND,ANI,OR,ORI) LD,LDI,AND,ANI,OR,ORI High Basic Process Redundant Universal LCPU performance Bit device number / Word device bit designation ( X1/D0.1 X1/D0.1 X2/D0.2 X2/D0.2 X3/D0.3 X3/D0.3 : Devices used as contacts (bits) Internal Devices Setting Other...
Page 145 LD,LDI,AND,ANI,OR,ORI AND, ANI (1) AND is the A contact series connection instruction, and ANI is the B contact series connection instruction. They read the ON/OFF data of the designated bit device* , perform an AND operation on that data and the operation result to that point, and take this value as the operation result.
Page 146 LD,LDI,AND,ANI,OR,ORI Operation Error (1) There are no operation errors with LD, LDI, AND, ANI, OR, or ORI instruction. Program Example (1) A program using the LD, AND, OR, and ORI instructions. [Ladder Mode] [List Mode] Instruction Step Device Bit designated for word device (2) A program linking contacts using the ANB and ORB instructions.
Page 147: Pulse Operation Start, Pulse Series Connection, Pulse Parallel Connection
LDP,LDF,ANDP,ANDF,ORP,ORF 5.1.2 Pulse operation start, pulse series connection, pulse parallel connection (LDP,LDF,ANDP,ANDF,ORP,ORF) LDP,LDF,ANDP,ANDF,ORP,ORF High Basic Process Redundant Universal LCPU performance Bit device number / Word device bit designation X1/D0.1 X1/D0.1 X2/D0.2 ANDP X2/D0.2 ANDF X3/D0.3 X3/D0.3 : Devices used as contacts (bits) Internal Devices Setting Other...
Page 148 LDP,LDF,ANDP,ANDF,ORP,ORF (2) LDF is the trailing edge pulse operation start instruction, and is ON only at the trailing edge of the designated bit device (when it goes from ON to OFF). If a word device has been designated, it is ON only when the designated bit changes from 1 to 0.
Page 149: Pulse Not Operation Start, Pulse Not Series Connection, Pulse Not Parallel Connection (Ldpi,Ldfi,Andpi,Andfi,Orpi,Orfi)
LDPI,LDFI,ANDPI,ANDFI,ORPI,ORFI 5.1.3 Pulse NOT operation start, pulse NOT series connection, pulse NOT parallel connection (LDPI,LDFI,ANDPI,ANDFI,ORPI,ORFI) LDPI,LDFI,ANDPI,ANDFI,ORPI,ORFI Ver. High Basic Process Redundant Universal LCPU performance • QnU(D)(H)CPU: The serial number (first five digits) is "10102" or later. • QnUDE(H)CPU: The serial number (first five digits) is "10102" or later. Bit device number / Bit device number / Word device bit designation...
Page 150 LDPI,LDFI,ANDPI,ANDFI,ORPI,ORFI (2) LDFI is the trailing edge pulse NOT operation start instruction that is on only at the trailing edge of the specified bit device (when the bit device goes from off to on) or when the bit device is on or off. If a word device has been specified, LDFI is on only when the specified bit is 0, 1, or changes from 0 to 1.
Page 151 LDPI,LDFI,ANDPI,ANDFI,ORPI,ORFI Program Example (1) The following program stores 0 into D0 when X0 is on, off, or turns from on to off, or M0 is on, off, or turns from off to on. [Ladder Mode] [List Mode] Step Instruction Device (2) The following program stores 0 into D0 when X0 is on and b10 (bit 11) of D0 is on, off, or turns from on to off.
Page 152: Association Instructions
ANB,ORB Association Instructions 5.2.1 Ladder block series connection and parallel connection (ANB,ORB) ANB,ORB High Basic Process Redundant Universal LCPU performance Block A Block B Block A Block B For parallel connection of 1 contact, OR or ORI is used. Internal Devices Setting R, ZR Constants...
Page 153 ANB,ORB Operation Error (1) There are no operation errors associated with ANB or ORB instruction. Program Example (1) A program using the ANB and ORB instructions. [Ladder Mode] [List Mode] Step Instruction Device 5-11...
Page 154: Operation Results Push,Read,Pop (Mps,Mrd,Mpp)
MPS,MRD,MPP 5.2.2 Operation results push,read,pop (MPS,MRD,MPP) MPS,MRD,MPP High Basic Process Redundant Universal LCPU performance In the ladder display, MPS, MRD and MPP are not displayed. Command Command Command Command Internal Devices Setting R, ZR Constants Other Data Word Word –– ––...
Page 155 MPS,MRD,MPP 1. The following shows ladders both using and not using the MPS, MRD, and MPP instructions. Ladder Using the MPS, MRD and MPP Instruction Ladder not Using MPS, MRD, and MPP Instructions 2. The MPS and MPP instructions must be used the same number of times. Failure to observe this will not correctly display the ladder in the ladder mode of the peripheral device.
Page 156 MPS,MRD,MPP (2) A program using the MPS and MPP instructions successively. [Ladder Mode] [List Mode] Instruction Device Step 5-14...
Page 157: Operation Results Inversion (Inv)
5.2.3 Operation results inversion (INV) High Basic Process Redundant Universal LCPU performance Command Internal Devices Setting R, ZR Constants Other Data Word Word –– –– Function Inverts the operation result immediately prior to the INV instruction. Operation Result Immediately Prior to the Operation Result Following the Execution of INV Instruction the INV Instruction...
Page 158 1. The INV instruction operates based on the results of calculation made until the INV instruction is given. Accordingly, use it in the same position as that of the AND instruction. The INV instruction cannot be used at the LD and OR positions. 2.
Page 159: Operation Result Conversions (Mep,Mef)
MEP,MEF 5.2.4 Operation result conversions (MEP,MEF) MEP,MEF High Basic Process Redundant Universal LCPU performance Command Command Internal Devices Setting R, ZR Constants Other Data Word Word –– –– Function (1) If operation results up to the MEP instruction are leading edge (from OFF to ON), goes ON (continuity status).
Page 160: Pulse Conversions Of Edge Relay Operation Results (Egp,Egf)
EGP,EGF 5.2.5 Pulse conversions of edge relay operation results (EGP,EGF) EGP,EGF High Basic Process Redundant Universal LCPU performance Command Command : Edge relay number where operation results are stored (bits) Internal Devices Setting Other R, ZR Constants Data Word Word ––...
Page 161 EGP,EGF Program Example (1) A program using the EGP instruction in the subroutine program using the EGD instruction [Ladder Mode] [List Mode] Step Instruction Device [Operation] END processing Turns OFF as X0 remains ON. Turns ON at the leading Turns OFF as X1 remains ON. edge of X0.
Page 162: Output Instructions
Output Instructions 5.3.1 Out instruction (excluding timers, counters, and annunciators) (OUT) High Basic Process Redundant Universal LCPU performance Bit device number ( Command Word device bit designation ( Command D0.5 : Number of the device to be turned ON and OFF (bits) Internal Devices Setting Other...
Page 163 Program Example (1) When using bit devices [Ladder Mode] [List Mode] Instruction Device Step (2) When bit designation has been made for word device [Ladder Mode] [List Mode] Step Instruction Device Remark The number of basic steps for the OUT instructions is as follows: •...
Page 164: Timers (Out T,Outh T)
OUT T,OUTH T 5.3.2 Timers (OUT T,OUTH T) OUT T,OUTH T High Basic Process Redundant Universal LCPU performance Command Set value Setting in the range from 1 to 32767 is valid. OUT T Command (Low-speed timer) Set value Data register value in the range from 1 to 32767 is valid.
Page 165 OUT T,OUTH T (2) The contact responds as follows when the operation result up to the OUT instruction is a change from ON to OFF: Prior to Time Up After Time Up Present Value of Type of Timer Timer Coil Timer A Contact B Contact...
Page 166 OUT T,OUTH T Caution (1) When creating a program in which the operation the timer contact triggers the operation of other timer, create the program for the timer that operates later first. In the following cases, all timers go ON at the same scan if the program is created in the order the timers operate.
Page 167 OUT T,OUTH T Program Example (1) The following program turns Y10 and Y14 ON 10 seconds after X0 has gone ON. [Ladder Mode] [List Mode] Step Instruction Device *3: The setting value of the low-speed timer indicates its default time limit (100 ms). (2) The following program uses the BCD data at X10 to X1F as the timer's set value.
Page 168: Counter (Out C)
OUT C 5.3.3 Counter (OUT C) OUT C High Basic Process Redundant Universal LCPU performance Set value Command Setting in the range from 1 to 32767 is valid. OUT C Set value Command Data register value in the range from 1 to 32767 is valid.
Page 169 OUT C Operation Error (1) There are no operation errors associated with the OUT C instruction. Program Example (1) The following program turns Y30 ON after X0 has gone ON 10 times, and resets the counter when X1 goes ON. [Ladder Mode] [List Mode] Step...
Page 170: Annunciator Output (Out F)
OUT F 5.3.4 Annunciator output (OUT F) OUT F High Basic Process Redundant Universal LCPU performance Annunciator number Command OUT F : Number of the annunciator to be turned ON (bits) Internal Devices Setting R, ZR Constants Other Data Word Word ––...
Page 171 OUT F Operation Error (1) There are no operation errors associated with the OUT F instruction. Remark 1. For details of annunciators, refer to the User's Manual (Functions Explanation, Program Fundamentals) for the CPU module used. 2. The number of basic steps for the OUT module F instruction is 2.
Page 172: Setting Devices (Except For Annunciators) (Set)
5.3.5 Setting devices (except for annunciators) (SET) High Basic Process Redundant Universal LCPU performance Command : Bit device number to be set (ON)/Word device bit designation (bits) Internal Devices Setting Other R, ZR Constants Data BL, DY Word Word –– (Other than T, C) Function (1) When the execution command is turned ON, the status of the designated devices becomes...
Page 173 Operation Error (1) There are no operation errors associated with the SET instruction. Program Example (1) The following program sets Y8B (ON) when X8 goes ON, and resets Y8B (OFF) when X9 goes ON. [Ladder Mode] [List Mode] Step Instruction Device (2) The following program sets the value of D0 bit 5 (b5) to 1 when X8 goes ON, and set the bit value to 0 when X9 goes ON.
Page 174: Resetting Devices (Except For Annunciators) (Rst)
5.3.6 Resetting devices (except for annunciators) (RST) High Basic Process Redundant Universal LCPU performance Command : Bit device number to be reset/ Word device bit designation (bits) Word device number to be reset (BIN 16 bits) Internal Devices Setting Other R, ZR Constants Data...
Page 175 Operation Error (1) There are no operation errors associated with the RST instruction. Remark The basic number of steps of the RST instruction is as follows. a) For bit processing • Internal device (bit to be specified by bit device or word device) : 1 •...
Page 176 (2) The following program resets the 100 ms retentive timer and counter. [Ladder Mode] When ST225 is set as retentive timer, it is turned ON when X4 ON time reaches 30 min. Counts the number of times ST225 was turned ON. Resets the coil, contact and present value of ST225 when the contact of ST225 is turned ON.
Page 177: Setting And Resetting The Annunciators (Set F,Rst F)
SET F,RST F 5.3.7 Setting and resetting the annunciators (SET F,RST F) SET F,RST F High Basic Process Redundant Universal LCPU performance Command Command : Number of the annunciator to be set (F number) (bits) : Number of the annunciator to be reset (F number) (bits) Internal Devices Setting R, ZR...
Page 178 SET F,RST F (3) When the value of SD63 is "16", the annunciator numbers are deleted from SD64 to SD79 by the use of the RST instruction. If the annunciators whose numbers are not registered in SD64 to SD79 are ON, these numbers will be registered. If all annunciator numbers from SD64 to SD79 are turned OFF, the LED display device on the front of the CPU module, or the "USER"...
Page 179: Leading Edge And Trailing Edge Outputs (Pls,Plf)
PLS,PLF 5.3.8 Leading edge and trailing edge outputs (PLS,PLF) PLS,PLF High Basic Process Redundant Universal LCPU performance Command Command : Pulse conversion device (bits) Internal Devices Setting Other R, ZR Constants Data Word Word –– Function (1) Turns ON the designated device when the execution command is turned OFF ON, and turns OFF the device in any other case the execution command is turned OFF ON (i.e., at ON, ON...
Page 180 PLS,PLF (3) When designating a latch relay (L) for the execution command and turning the power supply OFF to ON with the latch relay ON, the execution command turns OFF to ON at the first scan, executing the PLS instruction and turning ON the designated device. The device turned ON at the first scan after power-ON turns OFF at the next PLS instruction.
Page 181 PLS,PLF (2) The following program executes the PLF instruction when X9 goes OFF. [Ladder Mode] [List Mode] Step Instruction Device [Timing Chart] X9 OFF M9 OFF 1 scan 5-39...
Page 182: Bit Device Output Reverse (Ff)
5.3.9 Bit device output reverse (FF) High Basic Process Redundant Universal LCPU performance Command : Device number of the device to be reversed (bits) Internal Devices Setting Other R, ZR Constants Data Word Word –– Function (1) Reverses the output status of the device designated by when the execution command is turned OFF ON.
Page 183 (2) The following program reverses b10 (bit 10) of D10 when X0 goes ON. [Ladder Mode] [List Mode] Instruction Device Step [Timing Chart] D10 of b10 5-41...
Page 184: Pulse Conversions Of Direct Outputs (Delta(P))
DELTA(P) 5.3.10 Pulse conversions of direct outputs (DELTA(P)) DELTA(P) High Basic Process Redundant Universal LCPU performance Command DELTA DELTA Command DELTAP DELTAP : Bit for which pulse conversion is to be conducted (bits) Internal Devices Setting Other R, ZR Constants Data Word Word...
Page 185 DELTA(P) Program Example (1) The following program presets CH1 of the AD61 mounted at slot 0 of the main base unit, when X20 goes ON. [Ladder Mode] Stores preset value (0) at addresses 1 and 2 of the AD61 buffer memory. Outputs the preset command.
Page 186: Shift Instructions
SFT(P) Shift Instructions 5.4.1 Bit device shifts (SFT(P)) SFT(P) High Basic Process Redundant Universal LCPU performance Command Command SFTP SFTP : Device number to shift (bits) Internal Devices Setting Other R, ZR Constants Data Word Word –– (Other than T, C) Function (1) When bit device is used (a) Shifts to a device designated by...
Page 187 SFT(P) (2) When word device bit designation is used (a) Shifts to a bit in the device designated by the 1/0 status of the bit immediately prior to the one designated by , and turns the prior bit to 0. For example, if D0.5 (bit 5 [b5] of D0) has been designated by the SFT instruction, when the SFT instruction is executed, it will shift the 1/0 status of b4 of D0 to b5, and turn b4 to 0.
Page 188 SFT(P) Program Example (1) The following program shifts Y57 to Y5B when X8 goes ON. [Ladder Mode] Executes shift for Y57 to Y5B when X8 goes Start programming from the device having a large number. Turns Y57 ON when X7 goes ON. [Timing Chart] [List Mode] Step...
Page 189: Master Control Instructions
MC,MCR Master Control Instructions 5.5.1 Setting and resetting the master control (MC,MCR) MC,MCR High Basic Process Redundant Universal LCPU performance Command Master control ladder : Nesting (N0 to N14) (Nesting) : Device number to be turned ON (bits) Internal Devices Other Setting R, ZR...
Page 190 MC,MCR (1) If the execution command of the MC instruction is ON when master control is started, the result of the operation from the MC instruction to the MCR instruction will be exactly as the instruction (ladder) shows. If the execution command of the MC instruction is OFF, the result of the operation from the MC instruction to the MCR instruction will be as shown below: Device Device Status...
Page 191 MC,MCR Program Example The master control instruction can be used in nesting. The different master control regions are distinguished by nesting (N). Nesting can be performed from N0 to N14. The use of nesting enables the creation of ladders which successively limit the execution condition of the program.
Page 192 MC,MCR Cautions when Using Nesting Architecture (1) Nesting can be used up to 15 times (N0 to N14) When using nesting, nests should be inserted from the lower to higher nesting number (N) with the MC instruction, and from the higher to the lower order with the MCR instruction. If this order is reversed, there will be no nesting architecture, and the CPU module will not be capable of performing correct operations.
Page 193: Termination Instructions
FEND Termination Instructions 5.6.1 End main routine program (FEND) FEND High Basic Process Redundant Universal LCPU performance FEND FEND Internal Devices Setting R, ZR Constants Other Data Word Word –– –– Function (1) The FEND instruction is used in cases where the CJ instruction or other instructions are used to cause a branch in the sequence program operations, and in cases where the main routine program is to be split from a subroutine program or an interrupt program.
Page 194 FEND Operation Error (1) In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and an error code is stored into SD0. • The FEND instruction is executed after the execution of the CALL, FCALL, ECALL, or EFCALL instruction, and before the execution of the RET instruction.
Page 195: End Sequence Program (End)
5.6.2 End sequence program (END) High Basic Process Redundant Universal LCPU performance Internal Devices Setting R, ZR Constants Other Data Word Word –– –– Function (1) Indicates termination of programs, including main routine program, subroutine program, and interrupt programs. Execution of the END instruction will cause the CPU module to terminate the program that was being executed.
Page 196 (4) The use of the END and FEND instructions is broken down as follows for main routine programs, subroutine programs, and interrupt programs: Main routine program FEND (FEND instruction is necessary.) Subroutine program Main sequence program area Interrupt program (END instruction is necessary.) Operation Error (1) In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and an error code is stored into SD0.
Page 197: Other Instructions
STOP Other instructions 5.7.1 Sequence program stop (STOP) STOP High Basic Process Redundant Universal LCPU performance Command STOP STOP Internal Devices Setting R, ZR Constants Other Data Word Word –– –– Function (1) Resets the output (Y) and stops the CPU module operation when the execution command is turned ON.
Page 198 STOP Operation Error (1) In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and an error code is stored into SD0. • The STOP instruction was executed before the execution of the RET instruction and after the execution of the CALL/FCALL/ECALL/EFCALL/XCALL instruction.
Page 199: No Operations (Nop,Noplf
NOP,NOPLF,PAGE n 5.7.2 No operations (NOP,NOPLF,PAGE n) NOP,NOPLF,PAGE n High Basic Process Redundant Universal LCPU performance In the ladder display, NOP is not displayed. Command NOPLF NOPLF PAGE n PAGE n Internal Devices Setting R, ZR Constants Other Data Word Word ––...
Page 200 NOP,NOPLF,PAGE n PAGE n (1) This is a no operation instruction that has no impact on any operations up to that point. (2) No processing is performed at peripheral devices with this instruction. Operation Error (1) There are no errors associated with the NOP, NOPLF, or PAGE instruction. Program Example (1) Contact closed..
Page 201 NOP,NOPLF,PAGE n [Ladder Mode] [List Mode] Before change Instruction Device Step Changing to LD T3 Changing to NOP After change Instruction Device Step NOPLF [Ladder Mode] [List Mode] Instruction Device Step 5-59...
Page 202 NOP,NOPLF,PAGE n • Printing the ladder will result in the following: NOPLF instruction, inserted as a delimiter NOPLF of ladder blocks, causes print out page to be changed forcibly. • Printing an instruction list with the NOPLF instruction will result in the following: NOPLF Changes print output page after printing NOPLF.
Page 203 BASIC INSTRUCTIONS Reference Category Processing Details Section Comparison operation Compares data to data. Section 6.1 instruction Adds, subtracts, multiplies, divides, increments, or Arithmetic operation instruction Section 6.2 decrements data with other data. Section 6.3 Data conversion instructions Converts data types. Section 6.4 Data transfer instruction Transmits designated data.
Page 204: Comparison Operation Instructions
=,<>,>,<=,<,>= Comparison Operation Instructions 6.1.1 BIN 16-bit data comparisons (=,<>,>,<=,<,>=) =,<>,>,<=,<,>= High Basic Process Redundant Universal LCPU performance indicates an instruction symbol of Command Command Command : Data for comparison or head number of the devices where the data for comparison is stored (BIN 16 bits) Internal Devices Setting Constants...
Page 205 =,<>,>,<=,<,>= Operation Error (1) There are no operation errors associated with the , or instruction. Program Example (1) The following program compares the data at X0 to XF with the data at D3, and turns Y33 ON if the data is identical. [Ladder Mode] [List Mode] Instruction...
Page 206: Bin 32-Bit Data Comparisons (D=,D<>,D>,D<=,D<,D>=)
D=,D<>,D>,D<=,D<,D>= 6.1.2 BIN 32-bit data comparisons (D=,D<>,D>,D<=,D<,D>=) D=,D<>,D>,D<=,D<,D>= High Basic Process Redundant Universal LCPU performance indicates an instruction symbol of Command Command Command : Data for comparison or head number of the devices where the data for comparison is stored (BIN 32 bits) Internal Devices Setting Constants...
Page 207 D=,D<>,D>,D<=,D<,D>= Operation Error (1) There are no operation errors associated with the D , D , D , D or D instruction. Program Example (1) The following program compares the data at X0 to X1F with the data at D3 and D4, and turns Y33 ON, if the data at X0 to X1F and the data at D3 and D4 match.
Page 208: Floating Decimal Point Data Comparisons (Single Precision)
E=,E<>,E>,E<=,E<,E>= 6.1.3 Floating decimal point data comparisons (Single precision) (E=,E<>,E>,E<=,E<,E>=) E=,E<>,E>,E<=,E<,E>= Ver. High Basic Process Redundant Universal LCPU performance Basic model QCPU: The upper five digits of the serial No. are "04122" or larger. indicates an instruction symbol of Command Command Command : Data for comparison or head number of the devices where the data for comparison is stored (real number)
Page 209 E=,E<>,E>,E<=,E<,E>= Operation Error (1) In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and an error code is stored into SD0. • The value of the specified device is (For the Basic model QCPU, High Performance model QCPU, Process CPU, Redundant CPU) (Error code: 4100) *1: There are CPU modules that will not result in an operation error if...
Page 210: (Ed=,Ed<>,Ed>,Ed<=,Ed<,Ed>=)
ED=,ED<>,ED>,ED<=,ED<,ED>= 6.1.4 Floating decimal point data comparisons (Double precision) (ED=,ED<>,ED>,ED<=,ED<,ED>=) ED=,ED<>,ED>,ED<=,ED<,ED>= High Basic Process Redundant Universal LCPU performance indicates an instruction symbol of ED Command Command Command : Data for comparison or head number of the devices where the data for comparison is stored (real number) Internal Devices Setting...
Page 211 ED=,ED<>,ED>,ED<=,ED<,ED>= Operation Error (1) In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and an error code is stored into SD0. • The value of the specified device is not in the following range: (Error code: 4140) -1022 1024...
Page 212 ED=,ED<>,ED>,ED<=,ED<,ED>= Caution (1) Since the number of digits of the real number that can be input by Programing Tool is up to 15 digits, the comparison with the real number whose number of significant digits is 16 or more cannot be made by the instruction shown in this section. When judging match/mismatch with the real number whose significant digits is 16 or more by the instruction in this section, compare it with the approximate values of the real number to be compared and judge by the sizes.
Page 213: Character String Data Comparisons ($=,$<>,$>,$<=,$<,$>=)
$=,$<>,$>,$<=,$<,$>= 6.1.5 Character string data comparisons ($=,$<>,$>,$<=,$<,$>=) $=,$<>,$>,$<=,$<,$>= High Basic Process Redundant Universal LCPU performance indicates an instruction symbol of Command Command Command : Data for comparison or head number of the devices where the data for comparison is stored (character string) Internal Devices Setting...
Page 214 $=,$<>,$>,$<=,$<,$>= (b) If the character strings are different, the character string with the larger character code will be the larger. "ABCDF" "ABCDE" Comparison Operation Comparison Operation Instruction Symbol in Instruction Symbol in Result Result Non-continuity $<= Non-continuity $<> Continuity $< Non-continuity $>...
Page 215 $=,$<>,$>,$<=,$<,$>= Operation Error (1) In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and an error code is stored into SD0. • The code "00 " does not exist within the range of the relevant device, starting from the device number designated by (Error code: 4101) •...
Page 216 $=,$<>,$>,$<=,$<,$>= (3) The following program compares the character string stored following D10 with the character string stored following D100. [Ladder Mode] [List Mode] Instruction Device Step (4) The following program compares the character string stored following D200 with the character string "12345". [Ladder Mode] [List Mode] Instruction...
Page 217: Bkcmp P)
BKCMP ,BKCMP 6.1.6 BIN block data comparisons (BKCMP ,BKCMP BKCMP ,BKCMP High Basic Process Redundant Universal LCPU performance indicates an instruction symbol of Command BKCMP BKCMP Command BKCMP BKCMP : Data to be compared or head number of the devices where the data to be compared is stored (BIN 16 bits) : Head number of the devices where the comparison data is stored (BIN 16 bits) : Head number of the devices where the comparison operation result will be stored (bits) : Number of comparison data blocks (BIN 16 bits)
Page 218 BKCMP ,BKCMP (4) The results of the comparison operations for the individual instructions are as follows: Instruction Comparison Instruction Comparison Condition Condition Symbols Operation Result Symbols Operation Result BKCMP= BKCMP= BKCMP<> BKCMP<> BKCMP> BKCMP> > ON (1) OFF (0) BKCMP<= BKCMP<= >...
Page 219 BKCMP ,BKCMP (2) The following program compares, when X1C is turned ON, the constant K1000 with the data stored at D10 to D13, and stores the operation result at b4 to b7 in D0. [Ladder Mode] [List Mode] Device Step Instruction [Operation] 2000 (BIN)
Page 220: Dbkcmp P)
DBKCMP ,DBKCMP 6.1.7 BIN 32-bit block data comparisons (DBKCMP ,DBKCMP DBKCMP ,DBKCMP Ver. High Basic Process Redundant Universal LCPU performance QnU(D)(H)CPU: The serial number (first five digits) is "10102" or later. QnUDE(H)CPU: The serial number (first five digits) is "10102" or later. indicates an instruction symbol of Command DBKCMP...
Page 221 DBKCMP ,DBKCMP (2) The comparison operation is executed in 32-bit units. (3) The constant in the device specified by can be between 2147483648 and 2147483647 (BIN 32-bit data). Operation result ＋1, 32700 (BIN) ＋3, ＋2 40000 (BIN) ＋1 32800 (BIN) ＋5, ＋4 32800...
Page 222 DBKCMP ,DBKCMP Operation Error (1) In any of the following cases, an operation error occurs, the error flag (SM0) turns on, and an error code is stored into SD0. • A negative value is specified for n. (Error code: 4100) •...
Page 223 DBKCMP ,DBKCMP When certain bits are specified in a word device, bits other than the certain bits that store the operation result do not change. D10.F D10.0 Before execution D10.F D10.0 After execution No change No change (3) The following program compares the value data stored at D0 to D5 with the value data stored at D10 to D15, and then stores the operation result into M20 to M22, when M0 is turned on.
Page 224: Arithmetic Operation Instructions
+(P),-(P) Arithmetic Operation Instructions 6.2.1 BIN 16-bit addition and subtraction operations (+(P),-(P)) +(P),-(P) High Basic Process Redundant Universal LCPU performance When two data are set ( indicates an instruction symbol of Command Command +P, P : Data for additing/subtracting or head number of the devices where the data for additing/subtracting is stored (BIN 16 bits) : Head number of the devices where the data to be added to/subtracted from is stored (BIN 16 bits) S1 D...
Page 225 +(P),-(P) – (1) Subtracts 16-bit BIN data designated by from 16-bit BIN data designated by stores the result of the subtraction at the device designated by 5678 (BIN) 1234 (BIN) 4444 (BIN) (2) Values for can be designated between 32768 and 32767 (BIN, 16 bits). (3) The judgment of whether data is positive or negative is made by the most significant bit (b15).
Page 226 +(P),-(P) When three data are set ( indicates an instruction symbol of Command Command +P, P : Data to be added to/subtracted from or head number of the devices where the data to be added to/subtracted from is stored (BIN 16 bits) : Data for additing/subtracting or head number of the devices where the data for additing/subtracting is stored (BIN 16 bits) : Head number of the devices where the addition/subtraction operation result will be stored (BIN 16 bits)
Page 227 +(P),-(P) – (1) Subtracts 16-bit BIN data designated by from 16-bit BIN data designated by stores the result of the subtraction at the device designated by 5678 (BIN) 1234 (BIN) 4444 (BIN) (2) Values for and can be designated between 32768 and 32767 (BIN, 16 bits).
Page 228: Bin 32-Bit Addition And Subtraction Operations (D+(P),D-(P))
D+(P),D-(P) 6.2.2 BIN 32-bit addition and subtraction operations (D+(P),D-(P)) D+(P),D-(P) High Basic Process Redundant Universal LCPU performance When two data are set (( ), ( indicates an instruction symbol of Command D+, D Command D+P, D P : Data for additing/subtracting or head number of the devices where the data for additing/subtracting is stored (BIN 32 bits) : Head number of the devices where the data to be added to/subtracted from is stored (BIN 32 bits) Internal Devices...
Page 229 D+(P),D-(P) (1) Subtracts 32-bit BIN data designated by from 32-bit BIN data designated by stores the result of the subtraction at the device designated by D +1 b16 b15 b16 b15 b16 b15 567890 (BIN) 123456 (BIN) 444434 (BIN) (2) The values for can be designated at between 2147483648 and 2147483647 (BIN 32 bits).
Page 230 D+(P),D-(P) When three data are set (( ), ( indicates an instruction symbol of D+/ D Command D+, D Command D+P, D P : Data to be added to/subtracted from or head number of the devices where the data to be added to/subtracted from is stored (BIN 32 bits) : Data for additing/subtracting or head number of the devices where the data for additing/subtracting is stored (BIN 32 bits)
Page 231 D+(P),D-(P) (1) Subtracts 32-bit BIN data designated by from 32-bit BIN data designated by stores the result of the subtraction at the device designated by b16 b15 b16 b15 b16 b15 567890 (BIN) 123456 (BIN) 444434 (BIN) (2) The values for can be designated at between 2147483648 and 2147483647 (BIN 32 bits).
Page 232: Bin 16-Bit Multiplication And Division Operations (*(P),/(P))
*(P),/(P) 6.2.3 BIN 16-bit multiplication and division operations (*(P),/(P)) *(P),/(P) High Basic Process Redundant Universal LCPU performance indicates an instruction symbol of * Command *, / Command *P, / P : Data to be multiplied/divided or head number of the devices where the data to be multiplied/divided is stored (BIN 16 bits) : Data for multiplying/dividing or head number of the devices where the data for multiplying/dividing is stored (BIN 16 bits)
Page 233 *(P),/(P) (1) Divides BIN 16-bit data designated by and BIN 16-bit data designated by , and stores the result in the device designated by Quotient Remainder 5678 (BIN) 1234 (BIN) 4 (BIN) 742 (BIN) (2) If a word device has been used, the result of the division operation is stored as 32 bits, and both the quotient and remainder are stored;...
Page 234: Bin 32-Bit Multiplication And Division Operations (D*(P),D/(P))
D*(P),D/(P) 6.2.4 BIN 32-bit multiplication and division operations (D*(P),D/(P)) D*(P),D/(P) High Basic Process Redundant Universal LCPU performance indicates an instruction symbol of Command , D/ Command P,D/P : Data to be multiplied/divided or head number of the devices where the data to be multiplied/divided is stored (BIN 32 bits) : Data for multiplying/dividing or head number of the devices where the data for multiplying/dividing is stored (BIN 32 bits)
Page 235 D*(P),D/(P) (1) Divides BIN 32-bit data designated by and BIN 32-bit data designated by , and stores the result in the device designated by b31 b16 b31 b16 b31 b16 567890 (BIN) 123456 (BIN) 4 (BIN) 74066 (BIN) (2) With a word device, the division operation result is stored in 64 bits and both the quotient and remainder are stored.
Page 236: Bcd 4-Digit Addition And Subtraction Operations (B+(P),B-(P))
B+(P),B-(P) 6.2.5 BCD 4-digit addition and subtraction operations (B+(P),B-(P)) B+(P),B-(P) B+(P), B-(P) High Basic Process Redundant Universal LCPU performance When two data are set ( indicates an instruction symbol of B+/B Command B+, B Command B+P, B P : Data for adding/subtracting or head number of the devices where the data for adding/subtracting is stored (BCD 4 digits) : Head number of the devices where the data to be added to/subtracted from is stored (BCD 4 digits) Internal Devices...
Page 237 B+(P), B-(P) (3) The following will result if an underflow is generated by the subtraction operation: The carry flag in this case does not go ON. Operation Error (1) In the following case, an operation error occurs, the error flag (SM0) turns ON, and an error code is stored into SD0.
Page 238 B+(P), B-(P) When three data are set ( indicates an instruction symbol of B+/B- Command B+, B- Command B+P,B-P : Data to be added to/subtracted from or head number of the devices where the data to be added to/subtracted from is stored (BCD 4 digits) : Data for adding/subtracting or head number of the devices where the data for adding/subtracting is stored (BCD 4 digits) : Head number of the devices where the addition/subtraction operation result will be stored (BCD 4 digits)
Page 239 B+(P), B-(P) (3) The following will result if an underflow is generated by the subtraction operation: The carry flag in this case does not go ON. Operation Error (1) In the following case, an operation error occurs, the error flag (SM0) turns ON, and an error code is stored into SD0.
Page 240: Bcd 8-Digit Addition And Subtraction Operations (Db+(P),Db-(P))
DB+(P),DB-(P) 6.2.6 BCD 8-digit addition and subtraction operations (DB+(P),DB-(P)) DB+(P),DB-(P) High Basic Process Redundant Universal LCPU performance When two data are set (( ), ( indicates an instruction symbol of DB+/DB- Command DB+, DB- Command DB+P. DB-P : Data for adding/subtracting or head number of the devices where the data for adding/subtracting is stored (BCD 8 digits) : Head number of the devices where the data to be added to/subtracted from is stored (BCD 8 digits) Internal Devices...
Page 241 DB+(P),DB-(P) (2) 0 to 99999999 (BCD 8 digits) can be assigned to (3) The following will result if an underflow is generated by the subtraction operation: The carry flag in this case does not go ON. 3 4 5 6 7 8 3 4 5 6 7 9 9 9 9 9 9 9 Operation Error...
Page 242 DB+(P),DB-(P) When three data are set (( ), ( indicates an instruction symbol of DB+/ DB Command DB+, DB- Command DB+P, DB-P : Data to be added to/subtracted from or head number of the devices where the data to be added to/subtracted from is stored (BCD 8 digits) : Data for adding/subtracting or head number of the devices where the data for adding/subtracting is stored (BCD 8 digits)
Page 243 DB+(P),DB-(P) (1) Subtracts the BCD 8-digit data designated by and the BCD 8-digit data designated by and stores the result of the subtraction at the device designated by (Upper 4 digits) (Lower 4 digits) (Upper 4 digits) (Lower 4 digits) (Upper 4 digits) (Lower 4 digits) 7 8 9 1 2 3 2 3 4 5 6 7...
Page 244: Bcd 4-Digit Multiplication And Division Operations (B*(P),B/(P))
B*(P),B/(P) 6.2.7 BCD 4-digit multiplication and division operations (B*(P),B/(P)) B*(P),B/(P) High Basic Process Redundant Universal LCPU performance indicates an instruction symbol of B ,B/ Command , B/ Command P, B/P : Data to be multiplied/divided or head number of the devices where the data to be multiplied/divided is stored (BCD 4 digits) : Data for multiplying/dividing or head number of the devices where the data for multiplying/dividing is stored (BCD 4 digits)
Page 245 B*(P),B/(P) Operation Error (1) In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and an error code is stored into SD0. • The BCD data is outside the 0 to 9999 range. (Error code: 4100) •...
Page 246: Bcd 8-Digit Multiplication And Division Operations (Db*(P),Db/(P))
DB*(P),DB/(P) 6.2.8 BCD 8-digit multiplication and division operations (DB*(P),DB/(P)) DB*(P),DB/(P) High Basic Process Redundant Universal LCPU performance indicates an instruction symbol of DB ,DB/ Command DB , DB/ Command DB P, DB/P : Data to be multiplied/divided or head number of the devices where the data to be multiplied/divided is stored (BCD 8 digits) : Data for multiplying/dividing or head number of the devices where the data for multiplying/dividing is stored (BCD 8 digits)
Page 247 DB*(P),DB/(P) (2) 64 bits are used for the result of the division operation, and stored as quotient and remainder. Quotient (BCD 8 digits) :Stored at the lower 32 bits. Remainder (BCD 8 digits) :Stored at the upper 32 bits. (3) If has been designated as a bit device, the remainder of the operation will not be stored.
Page 248: Addition And Subtraction Of Floating Decimal Point Data
E+(P),E-(P) 6.2.9 Addition and subtraction of floating decimal point data (Single precision) (E+(P),E-(P)) E+(P),E-(P) Ver. High Basic Process Redundant Universal LCPU performance Basic model QCPU: The upper five digits of the serial No. are "04122" or larger. When two data are set (( ), ( indicates an instruction symbol of E+/E-...
Page 249 E+(P),E-(P) (2) Values which can be designated at and which can be stored, are as follows: -126 0, 2 | Designated value (stored value) | < 2 Operation Error (1) In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and an error code is stored into SD0.
Page 250 E+(P),E-(P) When three data are set (( ), ( indicates an instruction symbol of E+/E-. Command E+, E- Command E+P, E-P : Data to be added to/subtracted from or head number of the devices where the data to be added to/subtracted from is stored (real number) : Data for adding/subtracting or head number of the devices where the data for adding/subtracting is stored (real number)
Page 251 E+(P),E-(P) Operation Error (1) In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and an error code is stored into SD0. • The contents of the designated device or the result of the addition are not "0", or not within the following range: -126 0, 2...
Page 252: Addition And Subtraction Of Floating Decimal Point Data (Double Precision) (Ed+(P),Ed-(P))
ED+(P),ED-(P) 6.2.10 Addition and subtraction of floating decimal point data (Double precision) (ED+(P),ED-(P)) ED+(P),ED-(P) High Basic Process Redundant Universal LCPU performance When two data are set (( indicates an instruction symbol of ED+/ED-. Command ED+, ED- Command ED+P, ED-P : Data for adding/subtracting or head number of the devices where the data for adding/subtracting is stored (real number) : Head number of the devices where the data to be added to/subtracted from is stored (real number) Internal Devices...
Page 253 ED+(P),ED-(P) (1) Subtracts a 64-bit floating decimal point type real number designated by and a 64-bit floating decimal point type real number designated by , and stores the result at a device designated by 64-bit floating-point 64-bit floating-point 64-bit floating-point real number real number real number...
Page 254 ED+(P),ED-(P) When three data are set(( indicates an instruction symbol of ED+/ED-. Command ED+, ED- Command ED+P, ED-P : Data to be added to/subtracted from or head number of the devices where the data to be added to/subtracted from is stored (real number) : Data for adding/subtracting or head number of the devices where the data for adding/subtracting is stored (real number) : Head number of the devices where the addition/subtraction operation result is stored (real number)
Page 255 ED+(P),ED-(P) Operation Error (1) In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and an error code is stored into SD0. • The contents of the designated device or the result of the addition are not "0", or not within the following range: (Error code: 4140) -1022...
Page 256: Multiplication And Division Of Floating Decimal Point Data
E*(P),E/(P) 6.2.11 Multiplication and division of floating decimal point data (Single precision) (E*(P),E/(P)) E*(P),E/(P) Ver. High Basic Process Redundant Universal LCPU performance Basic model QCPU: The upper five digits of the serial No. are "04122" or larger. indicates an instruction symbol of E* , E/ Command E* , E/...
Page 257 E*(P),E/(P) (2) Values which can be designated at and which can be stored, are as follows: -126 0, 2 | Designated value (stored value) | < 2 Operation Error (1) In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and an error code is stored into SD0.
Page 258: Multiplication And Division Of Floating Decimal Point Data (Double Precision) (Ed*(P),Ed/(P))
ED*(P),ED/(P) 6.2.12 Multiplication and division of floating decimal point data (Double precision) (ED*(P),ED/(P)) ED*(P),ED/(P) High Basic Process Redundant Universal LCPU performance indicates an instruction symbol of ED*, ED/. Command ED*, ED/ Command ED* P, ED/P : Data to be multiplied/divided or head number of the devices where the data to be multiplied/divided is stored (real number) : Data for multiplying/dividing or head number of the devices where the data for multiplying/dividing is stored (real number)
Page 259 ED*(P),ED/(P) (1) Divides the 64-bit floating decimal point real number designated by by the 64-bit floating decimal point real number designated by and stores the operation result at the device designated by 64-bit floating-point 64-bit floating-point 64-bit floating-point real number real number real number (2) Values which can be designated at...
Page 260 ED*(P),ED/(P) (2) The following program divides the 64-bit floating decimal point real numbers at D10 to D13 by the 64-bit floating decimal point real numbers at D20 to D23, and stores the result at D30 to D33. [Ladder Mode] [List Mode] Step Instruction Device...
Page 261: Block Addition And Subtraction (Bk+(P),Bk-(P))
BK+(P),BK-(P) 6.2.13 Block addition and subtraction (BK+(P),BK-(P)) BK+(P),BK-(P) High Basic Process Redundant Universal LCPU performance indicates an instruction symbol of BK+, BK- . Command BK+, BK- Command BK+P, BK-P : Head number of the devices where the data to be added to/subtracted from is stored (BIN 16 bits) : Data for additing/subtracting or head number of the devices where the data for additing/subtracting is stored (BIN 16 bits) : Head number of the devices where the operation result will be stored (BIN 16 bits)
Page 262 BK+(P),BK-(P) (4) The following will happen when an underflow or overflow is generated in an operation result: The carry flag in this case does not go ON. K32767 K 32767 (7FFF (0002 (8001 K 32767 K32767 +K 2 (8001 (FFFE (7FFF (1) Subtracts n points of BIN data from the device designated by and n-points of BIN data...
Page 263 BK+(P),BK-(P) Program Example (1) The following program adds, when X20 is turned ON, the data stored at D100 to D103 to the data stored at R0 to R3 and stores the operation result into the area starting from D200. [Ladder Mode] [List Mode] Step Instruction...
Page 264: Bin 32-Bit Data Block Addition And Subtraction Operations (Dbk+(P),Dbk-(P))
DBK+(P),DBK-(P) 6.2.14 BIN 32-bit data block addition and subtraction operations (DBK+(P),DBK-(P)) DBK+(P),DBK-(P) Ver. High Basic Process Redundant Universal LCPU performance QnU(D)(H)CPU: The serial number (first five digits) is "10102" or later. QnUDE(H)CPU: The serial number (first five digits) is "10102" or later. indicates an instruction symbol of DBK+, DBK- .
Page 265 DBK+(P),DBK-(P) When a constant is specified for (BIN) 20000 (BIN) ＋1, -30000 ＋1, 90000 ＋3, ＋2 40000 (BIN) ＋3, ＋2 (BIN) ＋＋5, ＋4 -50000 (BIN) ＋1, 50000 (BIN) ＋5, ＋4 (BIN) ＋n 1, ＋n 2 60000 (BIN) ＋n 1, ＋n 2 110000 (BIN)
Page 266 DBK+(P),DBK-(P) (6) The following will happen if an overflow occurs in an operation result: The carry flag in this case is not turned on. −K−2 ・ K2147483647 ) ( 80000001 (00000002 (7FFFFFFF K2147483647 ・ K 2147483647 −K2 ( FFFFFFFE ) ( 7FFFFFFF (80000001 Operation Error (1) In any of the following cases, an operation error occurs, the error flag (SM0) turns on, and an...
Page 267 DBK+(P),DBK-(P) Program Example (1) The following program adds the value data stored at R0 to R5 to the constant, and then stores the operation result into D30 to D35, when M0 is turned on. [Ladder Mode] [List Mode] Step Instruction Device [Operation] 600000...
Page 268: Linking Character Strings ($+(P))
$+(P) 6.2.15 Linking character strings ($+(P)) $+(P) High Basic Process Redundant Universal LCPU performance When two data are set ( Command Command : Data for linking or head number of the devices where the data for linking is stored (character string) : Head number of the devices where the data to be linked is stored (character string) Internal Devices Setting...
Page 269 $+(P) Operation Error (1) In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and an error code is stored into SD0. • The entire character string linked from the device number designated by to the final device number of the relevant device cannot be stored.
Page 270 $+(P) When three data are set ( Command Command : Data for linking or head number of the devices where the data for linking is stored (character string) : Data to be linked or head number of the devices where the data to be linked is stored (character string) : Head number of the devices where the linking result will be stored (character string) Internal Devices Setting...
Page 271 $+(P) Operation Error (1) In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and an error code is stored into SD0. • The entire character string linked from the device number designated by to the final device number of the relevant device cannot be stored.
Page 272: Incrementing And Decrementing 16-Bit Bin Data (Inc(P),Dec(P))
INC(P),DEC(P) 6.2.16 Incrementing and decrementing 16-bit BIN data (INC(P),DEC(P)) INC(P),DEC(P) High Basic Process Redundant Universal LCPU performance indicates an instruction symbol of INC/DEC. Command INC, DEC Command INCP, DECP : Head number of devices for INC (+1)/DEC ( 1) operation (BIN 16 bits) Internal Devices Setting R, ZR...
Page 273 INC(P),DEC(P) Program Example (1) The following program outputs the present value at the counter C0 to C20 to the area Y30 to Y3F in BCD, every time X8 is turned ON. (When present value is less than 9999) [Ladder Mode] Outputs the present value of (0+Z1) to Y30 to Y3F in BCD.
Page 274: Incrementing And Decrementing 32-Bit Bin Data (Dinc(P),Ddec(P))
DINC(P),DDEC(P) 6.2.17 Incrementing and decrementing 32-bit BIN data (DINC(P),DDEC(P)) DINC(P),DDEC(P) High Basic Process Redundant Universal LCPU performance indicates an instruction symbol of DINC/DDEC. Command DINC, DDEC Command DINCP, DDECP : Head number of devices for DINC(+1) or DDEC(-1) operation (BIN 32 bits) Internal Devices Setting R, ZR...
Page 275 DINC(P),DDEC(P) Program Example (1) The following program adds 1 to the data at D0 and D1 when X0 is ON. [Ladder Mode] [List Mode] Step Instruction Device (2) The following program adds 1 to the data set at X10 to X27 when X0 goes ON, and stores the result at D3 and D4.
Page 276: Data Conversion Instructions
BCD(P),DBCD(P) Data conversion instructions 6.3.1 Conversion from BIN data to 4-digit and 8-digit BCD (BCD(P),DBCD(P)) BCD(P),DBCD(P) BCD(P), DBCD(P) High Basic Process Redundant Universal LCPU performance indicates an instruction symbol of BCD/DBCD. Command BCD, DBCD Command BCDP, DBCDP : BIN data or head number of the devices where the BIN data is stored (BIN 16/32 bits) : Head number of the devices where BCD data will be stored (BCD 4/8 digits) Internal Devices Setting...
Page 277 BCD(P), DBCD(P) Operation Error (1) In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and an error code is stored into SD0. • The data of is other than 0 to 9999 at BCD instruction. (Error code: 4100) •...
Page 278: Conversion From Bcd 4-Digit And 8-Digit Data To Bin Data (Bin(P),Dbin(P))
BIN(P),DBIN(P) 6.3.2 Conversion from BCD 4-digit and 8-digit data to BIN data (BIN(P),DBIN(P)) BIN(P),DBIN(P) High Basic Process Redundant Universal LCPU performance indicates an instruction symbol of BIN/DBIN. Command BIN, DBIN Command BINP, DBINP : BCD data or head number of the devices where the BCD data is stored (BCD 4/8 digits) : Head number of the devices where BIN data will be stored (BIN 16/32 bits) Internal Devices Setting...
Page 279 BIN(P),DBIN(P) Operation Error (1) In the following case, an operation error occurs, the error flag (SM0) turns ON, and an error code is stored into SD0. • When values other than 0 to 9 are designated to any digits of (Error code: 4100) The error above can be suppressed by turning ON SM722.
Page 280 BIN(P),DBIN(P) (2) The following program converts the BCD data at X10 to X37 to BIN when X8 is ON, and stores it at D0 and D1. (Addition of the BIN data converted from BCD at X20 to X37 and the BIN data converted from BCD at X10 to X1F) BCD digital switch Input power supply...
Page 281: Conversion From Bin 16 And 32-Bit Data To Floating Decimal Point (Single Precision) (Flt(P),Dflt(P))
FLT(P),DFLT(P) 6.3.3 Conversion from BIN 16 and 32-bit data to floating decimal point (Single precision) (FLT(P),DFLT(P)) FLT(P),DFLT(P) Ver. High Basic Process Redundant Universal LCPU performance Basic model QCPU: The upper five digits of the serial No. are "04122" or larger. indicates an instruction symbol of FLT/DFLT.
Page 282 FLT(P),DFLT(P) (3) Due to the fact that 32-bit floating decimal point type real numbers are processed by simple 32-bit processing, the number of significant digits is 24 bits if the display is binary and approximately 7 digits if the display is decimal. For this reason, if the integer exceeds the range of 16777216 to 16777215 (24-bit BIN value), errors can be generated in the conversion value.
Page 283 FLT(P),DFLT(P) Program Example (1) The following program converts the BIN 16-bit data at D20 to a 32-bit floating decimal point type real number and stores the result at D0 and D1. [Ladder Mode] [List Mode] Instruction Device Step [Operation] Integer conversion 15923 15923...
Page 284: Conversion From Bin 16 And 32-Bit Data To Floating Decimal Point (Double Precision) (Fltd(P),Dfltd(P))
FLTD(P),DFLTD(P) 6.3.4 Conversion from BIN 16 and 32-bit data to floating decimal point (Double precision) (FLTD(P),DFLTD(P)) FLTD(P),DFLTD(P) High Basic Process Redundant Universal LCPU performance indicates an instruction symbol of FLTD/DFLTD. Command FLTD, DFLTD Command FLTDP, DFLTDP : Integer data to be converted to 64-bit floating decimal point data or head number of the devices where the integer data is stored (BIN 16/32 bits) : Head number of the devices where the converted 64-bit floating decimal point data will be stored (real number)
Page 285 FLTD(P),DFLTD(P) Operation Error (1) There are no errors associated with the FLTD,DFLTD instruction. Program Example (1) The following program converts the BIN 16-bit data at D20 to a 64-bit floating decimal point type real number and stores the result at D0 to D3. [Ladder Mode] [List Mode] Device...
Page 286: Conversion From Floating Decimal Point Data To Bin16- And 32-Bit Data (Single Precision) (Int(P),Dint(P))
INT(P),DINT(P) 6.3.5 Conversion from floating decimal point data to BIN16- and 32-bit data (Single precision) (INT(P),DINT(P)) INT(P),DINT(P) Ver. High Basic Process Redundant Universal LCPU performance Basic model QCPU: The upper five digits of the serial No. are "04122" or larger. indicates an instruction symbol of INT/DINT.
Page 287 INT(P),DINT(P) (3) The integer value stored at +1 and is stored as BIN 32 bits. (4) After conversion, the first digit after the decimal point of the real number is rounded off. Operation Error (1) In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and an error code is stored into SD0.
Page 288 INT(P),DINT(P) (2) The following program converts the 32-bit floating decimal point type real number at D20 and D21 to BIN 32-bit data and stores the result at D0 and D1. [Ladder Mode] [List Mode] Instruction Device Step [Operation] Integer conversion -574968.321 -574968 BIN value...
Page 289: Conversion From Floating Decimal Point Data To Bin16- And 32-Bit Data (Double Precision) (Intd(P),Dintd(P))
INTD(P),DINTD(P) 6.3.6 Conversion from floating decimal point data to BIN16- and 32-bit data (Double precision) (INTD(P),DINTD(P)) INTD(P),DINTD(P) High Basic Process Redundant Universal LCPU performance indicates an instruction symbol of INTD/DINTD. Command INTD, DINTD Command INTDP, DINTDP : 64-bit floating decimal point data to be converted to BIN value or head number of the devices where the floating decimal point data is stored (real number) : Head number of the devices where the converted BIN value will be stored (BIN 16/32 bits) Internal Devices...
Page 290 INTD(P),DINTD(P) (2) The range of 64-bit floating decimal point type real numbers that can be designated at +1 or is from 2147483648 to 2147483647. (3) The integer value stored at +1 and is stored as BIN 32 bits. (4) The converted data is the value rounded 64-bit floating-point real number to the first digit after the decimal point.
Page 291: Conversion From Bin 16-Bit To Bin 32-Bit Data (Dbl(P))
DBL(P) 6.3.7 Conversion from BIN 16-bit to BIN 32-bit data (DBL(P)) DBL(P) High Basic Process Redundant Universal LCPU performance Command Command DBLP DBLP : BIN 16-bit data or head number of the devices where the BIN 16-bit data is stored (BIN 16 bits) : Head number of the devices where the converted BIN 32-bit data will be stored (BIN 32 bits) Internal Devices Setting...
Page 292: Conversion From Bin 32-Bit To Bin 16-Bit Data (Word(P))
WORD(P) 6.3.8 Conversion from BIN 32-bit to BIN 16-bit data (WORD(P)) WORD(P) High Basic Process Redundant Universal LCPU performance Command WORD WORD Command WORDP WORDP : BIN 32-bit data or head number of the devices where the BIN 32-bit data is stored (BIN 32 bits) : Head number of the devices where the converted BIN 16-bit data will be stored (BIN 16 bits) Internal Devices Setting...
Page 293: Conversion From Bin 16 And 32-Bit Data To Gray Code (Gry(P),Dgry(P))
GRY(P),DGRY(P) 6.3.9 Conversion from BIN 16 and 32-bit data to Gray code (GRY(P),DGRY(P)) GRY(P),DGRY(P) High Basic Process Redundant Universal LCPU performance indicates an instruction symbol of GRY, DGRY. Command GRY, DGRY Command GRYP, DGRYP : BIN data or head number of the devices where the BIN data is stored (BIN 16/32 bits) : Head number of the devices where the converted Gray code will be stored (BIN 16/32 bits) Internal Devices Setting...
Page 294 GRY(P),DGRY(P) Operation Error (1) In the following case, an operation error occurs, the error flag (SM0) turns ON, and an error code is stored into SD0. • The data at is a negative number. (Error code: 4100) Program Example (1) The following program converts the BIN data at D100 to Gray code when X10 is ON, and stores result at D200.
Page 295: Conversion Of Gray Code To Bin 16 And 32-Bit Data (Gbin(P),Dgbin(P))
GBIN(P),DGBIN(P) 6.3.10 Conversion of Gray code to BIN 16 and 32-bit data (GBIN(P),DGBIN(P)) GBIN(P),DGBIN(P) High Basic Process Redundant Universal LCPU performance indicates an instruction symbol of GBIN/DGBIN. Command GBIN, DGBIN Command GBINP, DGBINP : Gray code data or head number of the devices where the Gray code data is stored (BIN 16/32 bits) : Head number of the devices where the converted BIN data will be stored (BIN 16/32 bits) Internal Devices Setting...
Page 296 GBIN(P),DGBIN(P) Operation Error (1) In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and an error code is stored into SD0. • Data at when the GBIN instruction was issued is outside the 0 to 32767 range. (Error code: 4100) •...
Page 297: Complement Of 2 Of Bin 16- And 32-Bit Data (Sign Reversal) (Neg(P),Dneg(P))
NEG(P),DNEG(P) 6.3.11 Complement of 2 of BIN 16- and 32-bit data (sign reversal) (NEG(P),DNEG(P)) NEG(P),DNEG(P) High Basic Process Redundant Universal LCPU performance indicates an instruction symbol of NEG/DNEG. Command NEG, DNEG Command NEGP, DNEGP : Head number of the devices where the data for which complement of 2 is performed is stored (BIN 16/32 bits) Internal Devices Setting...
Page 298 NEG(P),DNEG(P) DNEG (1) Reverses the sign of the 32-bit device designated by and stores at the device designated 32 bit Before execution -218460 Sign conversion - After 218460 execution (2) Used when reversing positive and negative signs. Operation Error (1) There are no operation errors associated with the NEG(P) or DNEG(P) instruction. Program Example (1) The following program calculates a total for the data at D10 through D20 when XA goes ON, and seeks an absolute value if the result is negative.
Page 299: Floating-Point Sign Invertion (Single Precision) (Eneg(P))
ENEG(P) 6.3.12 Floating-point sign invertion (Single precision) (ENEG(P)) ENEG(P) Ver. High Basic Process Redundant Universal LCPU performance Basic model QCPU: The upper five digits of the serial No. are "04122" or larger. Command ENEG ENEG Command ENEGP ENEGP : Head number of the devices where the 32-bit floating decimal point data whose sign is to be reversed is stored (real number) Internal Devices Setting...
Page 300: Floating-Point Sign Invertion (Double Precision) (Edneg(P))
EDNEG(P) 6.3.13 Floating-point sign invertion (Double precision) (EDNEG(P)) EDNEG(P) High Basic Process Redundant Universal LCPU performance Command EDNEG EDNEG Command EDNEGP EDNEGP : Head number of the devices where the 64-bit floating decimal point data whose sign is to be reversed is stored (real number) Internal Devices Setting...
Page 301: Conversion From Block Bin 16-Bit Data To Bcd 4-Digit Data (Bkbcd(P))
BKBCD(P) 6.3.14 Conversion from block BIN 16-bit data to BCD 4-digit data (BKBCD(P)) BKBCD(P) High Basic Process Redundant Universal LCPU performance Command BKBCD BKBCD Command BKBCDP BKBCDP : Head number of the devices where BIN data is stored (BIN 16 bits) : Head number of the devices where the converted BCD data will be stored (BCD 4 digits) n : Number of variable data blocks (BIN 16 bits) Internal Devices...
Page 302 BKBCD(P) Operation Error (1) In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and an error code is stored into SD0. • The range of the device n points from a device designated by or exceeds the relevant device.
Page 303: Conversion From Block Bcd 4-Digit Data To Block Bin 16-Bit Data (Bkbin(P))
BKBIN(P) 6.3.15 Conversion from block BCD 4-digit data to block BIN 16-bit data (BKBIN(P)) BKBIN(P) High Basic Process Redundant Universal LCPU performance Command BKBIN BKBIN Command BKBINP BKBINP : Head number of the devices where BCD data is stored (BCD 4 digits) : Head number of the devices where the converted BIN data will be stored (BIN 16 bits) n : Number of variable data blocks (BIN 16 bits) Internal Devices...
Page 304 BKBIN(P) Operation Error (1) In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and an error code is stored into SD0. • The n-bit range from the , or device exceeds the range of that device. (Error code: 4101) •...
Page 305: Single Precision To Double Precision Conversion (Econ(P))
ECON(P) 6.3.16 Single precision to Double precision conversion (ECON(P)) ECON(P) High Basic Process Redundant Universal LCPU performance Command ECON ECON Command ECONP ECONP : Conversion source data, or head number of the device where conversion source data is stored (Real number (single precision)) : Head number of the device where the converted data is stored (Real number (double precision)) Internal Devices Setting...
Page 306 ECON(P) Program Example (1) The program which converts 32-bit floating-point real number of the devices, D10 to D11, into 64-bit floating-point real number when X0 turns ON, and outputs the conversion result to the devices, D0 to D3. [Ladder Mode] [List Mode] Instruction Device...
Page 307: Double Precision To Single Precision Conversion (Edcon(P))
EDCON(P) 6.3.17 Double precision to Single precision conversion (EDCON(P)) EDCON(P) High Basic Process Redundant Universal LCPU performance Command EDCON EDCON Command EDCONP EDCONP : Conversion source data, or head number of the device where conversion source data is stored (Real number (double precision)) : Head number of the device where the converted data is stored (Real number (single precision)) Internal Devices Setting...
Page 308 EDCON(P) Program Example (1) The program which converts 64-bit floating-point real number of the devices, D10 to D13, into 32-bit floating-point real number when X0 turns ON, and outputs the conversion result to the devices, D0 to D1. [Ladder Mode] [List Mode] Instruction Device...
Page 309: Data Transfer Instructions
MOV(P),DMOV(P) Data Transfer Instructions 6.4.1 16-bit and 32-bit data transfers (MOV(P),DMOV(P)) MOV(P),DMOV(P) High Basic Process Redundant Universal LCPU performance indicates an instruction symbol of MOV/DMOV. Command MOV, DMOV Command MOVP, DMOVP : Data to be transferred or the number of the device where the data to be transferred is stored (BIN 16/32 bits) : Number of the device where the data will be transferred (BIN 16/32 bits) Internal Devices Setting...
Page 310 MOV(P),DMOV(P) Program Example (1) The following program stores input data from X0 to XB at D8. [Ladder Mode] [List Mode] Instruction Device Step (2) The following program stores the constant K155 at D8 when X8 goes ON. [Ladder Mode] [List Mode] Instruction Device Step...
Page 311 EMOV(P) 6.4.2 Floating-point data transfer (Single precision) (EMOV(P)) EMOV(P) Ver. High Basic Process Redundant Universal LCPU performance Basic model QCPU: The upper five digits of the serial No. are "04122" or larger. Command EMOV EMOV Command EMOVP EMOVP : Data to be transferred or number of the device to which the data to be transferred is stored (real number) : The number of the device to which the transferred data will be stored (real number) Internal Devices Setting...
Page 312 EMOV(P) Program Example (1) The following program stores the real numbers at D10 and D11 at D0 and D1. [Ladder Mode] [List Mode] Instruction Device Step [Operation] 36.475 36.475 (2) The following program stores the real number 1.23 at D10 and D11 when X8 is ON. [Ladder Mode] [List Mode] Step...
Page 313 EDMOV(P) 6.4.3 Floating-point data transfer (Double precision) (EDMOV(P)) EDMOV(P) High Basic Process Redundant Universal LCPU performance Command EDMOV EDMOV Command EDMOVP EDMOVP : Data to be transferred or number of the device to which the data to be transferred is stored (real number) : The number of the device to which the transferred data will be stored (real number) Internal Devices Setting...
Page 314 EDMOV(P) Program Example (1) The following program stores the 64-bit floating decimal point type real number at D10 to D13 at D0 to D3. [Ladder Mode] [List Mode] Device Step Instruction [Operation] D13 D12 D3 D2 36.475 36.475 (2) The following program stores the real number 1.23 at D10 to D13 when X8 is ON.
Page 315 $MOV(P) 6.4.4 Character string transfers ($MOV(P)) $MOV(P) High Basic Process Redundant Universal LCPU performance Command $MOV $MOV Command $MOVP $MOVP : Character string to be transferred (maximum string length: 32 characters) or head number of the devices where the character string to be transferred is stored (character string) : Head number of the devices where the transferred character string will be stored (character string) Internal Devices...
Page 316 $MOV(P) (3) If the "00 " code is being stored at lower bytes of +n, "00 " will be stored at both the higher bytes and the lower bytes of b8 b7 b8 b7 At the upper byte position, Upper byte is not transferred. "00 "...
Page 317 CML(P),DCML(P) 6.4.5 16-bit and 32-bit negation transfers (CML(P),DCML(P)) CML(P),DCML(P) High Basic Process Redundant Universal LCPU performance indicates an instruction symbol of CML, DCML. Command CML, DCML Command CMLP, DCMLP : Data to be reversed or the number of the device where data to be reversed is stored (BIN 16/32 bits) : Number of the device where the reversing result will be stored (BIN 16/32 bits) Internal Devices Setting...
Page 318 CML(P),DCML(P) Program Example (1) The following program inverts the data from X0 to X7, and transfers result to D0. [Ladder Mode] [List Mode] Instruction Device Step [Operation] If "Number of bits of < Number of bits of " These bits are all regarded as 0. 1 1 0 1 0 0 0 0 0 0 1 0 1 1 1 1 (2) The following program inverts the data at M16 to M23, and transfers the result to Y40 to...
Page 319 CML(P),DCML(P) (4) The following program inverts the data at X0 to X1F, and transfers results to D0 and D1. [Ladder Mode] [List Mode] Instruction Device Step [Operation] If "Number of bits of < Number of bits of " X8 X7 These bits are all regarded as 0.
Page 320 BMOV(P) 6.4.6 Block 16-bit data transfers (BMOV(P)) BMOV(P) High Basic Process Redundant Universal LCPU performance Command BMOV BMOV Command BMOVP BMOVP : Head number of the devices where the data to be transferred is stored (BIN 16 bits) : Head number of the devices of transfer destination (BIN 16 bits) n : Number of transfers (BIN 16 bits) Internal Devices Setting...
Page 321 BMOV(P) Example Transfer ranges of ZR and R overlap when transferring 10000 blocks of data from ZR30000 (source) to R10 (block No.1 of the destination). • ZR transfer range (30000) to (30000+10000-1) (30000) to (39999) • R transfer range (10+(1 32768)) to (10+(1 32768)+10000-1) (32778) to (42777) Therefore, the range 32778 to 39999 overlaps and the data is not correctly transferred.
Page 322 BMOV(P) Caution While SM237 is on, do not make the following access. • The indexing target exceeds the device range. • The value obtained from " + (n) - 1" is over the boundaries of the device ranges. • Accessing the file register with file register not set. •...
Page 323 BMOV(P) Program Example (1) The following program outputs the lower 4 bits of data at D66 to D69 to Y30 to Y3F in 4-point units. [Ladder Mode] [List Mode] Instruction Device Step [Operation] Before execution (source of transfer) After execution (destination of transfer) 1 1 0 1 Y33 to Y30 0 0 0 0...
Page 324 FMOV(P) 6.4.7 Identical 16-bit data block transfers (FMOV(P)) FMOV(P) High Basic Process Redundant Universal LCPU performance Command FMOV FMOV Command FMOVP FMOVP : Data to be transferred or the head number of the devices where the data to be transferred is stored (BIN 16 bits) : Head number of the devices of transfer destination (BIN 16 bits) n : Number of transfers (BIN 16 bits)
Page 325 FMOV(P) (4) Selection whether to check a device range Whether to check a device range during execution of the FMOV instruction can be selected with the device range check inhibit flag (SM237) (only when the conditions for subset processing are established). While SM237 is ON, whether + (n) - 1 is within the device range or not is not checked.
Page 326 FMOV(P) Program Example (1) The following program outputs the lower 4 bits of D0 when XA goes ON to Y10 to Y23 in 4-bit units. [Ladder Mode] [List Mode] Device Step Instruction [Operation] b2 b1 1 0 1 1 1 0 0 1 1 0 1 1 Y13 to Y10 Ignored...
Page 327 DFMOV(P) 6.4.8 Identical 32-bit data block transfers (DFMOV(P)) DFMOV(P) Ver. High Basic Process Redundant Universal LCPU performance QnU(D)(H)CPU: The serial number (first five digits) is "10102" or later. QnUDE(H)CPU: The serial number (first five digits) is "10102" or later. Command DFMOV DFMOV Command...
Page 328 DFMOV(P) (3) If specifies data of a device with digit specification, the amount of data stored in the device specified by will be transferred. If K5Y0 is specified by , the lower 20 bits of the word device specified by will be the object.
Page 329 XCH(P),DXCH(P) 6.4.9 16-bit and 32-bit data exchanges (XCH(P),DXCH(P)) XCH(P),DXCH(P) High Basic Process Redundant Universal LCPU performance indicates an instruction symbol of XCH, DXCH. Command XCH, DXCH Command XCHP, DXCHP : Head number of the devices where the data to be exchanged is stored (BIN 16/32 bits) Internal Devices Setting R, ZR...
Page 330 XCH(P),DXCH(P) Operation Error (1) There are no errors associated with the XCH (P) and DXCH (P) instruction. Program Example (1) The following program exchanges the present value of T0 with the contents of D0 when X8 goes ON. [Ladder Mode] [List Mode] Instruction Device...
Page 331: Block 16-Bit Data Exchanges (Bxch(P))
BXCH(P) 6.4.10 Block 16-bit data exchanges (BXCH(P)) BXCH(P) High Basic Process Redundant Universal LCPU performance Command BXCH BXCH Command BXCHP BXCHP : Head number of the devices where the data to be exchanged is stored (BIN 16 bits) : Number of exchanges (BIN 16 bits) Internal Devices Setting Constants...
Page 332 BXCH(P) Operation Error (1) In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and an error code is stored into SD0. • The range of the device of n points from a device designated by or exceeds the relevant device.
Page 333: Upper And Lower Byte Exchanges (Swap(P))
SWAP(P) 6.4.11 Upper and lower byte exchanges (SWAP(P)) SWAP(P) High Basic Process Redundant Universal LCPU performance Command SWAP SWAP Command SWAPP SWAPP : Head number of the devices where the data is stored (BIN 16 bits) Internal Devices Setting R, ZR Constants Other Data...
Page 334 CJ,SCJ,JMP Program Branch Instructions 6.5.1 Pointer branch instructions (CJ,SCJ,JMP) CJ,SCJ,JMP High Basic Process Redundant Universal LCPU performance Command Command Label Command P** : Pointer number of jump destination (Device name) Internal Devices Setting Other R, ZR Constants Data Word Word ––...
Page 335 CJ,SCJ,JMP (1) Unconditionally executes program of designated pointer number within the same program file. Note the following points when using the jump instruction. 1. After the timer coil has gone ON, accurate measurements cannot be made if there is an attempt to jump the timer of a coil that has been turned ON using the CJ, SCJ or JMP instructions.
Page 336 CJ,SCJ,JMP Operation Error (1) In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and an error code is stored into SD0. • The pointer number designated does not come prior to the END instruction. (Error code: 4210) •...
Page 337 GOEND 6.5.2 Jump to END (GOEND) GOEND High Basic Process Redundant Universal LCPU performance Command GOEND GOEND Internal Devices Setting R, ZR Constants Other Data Word Word –– –– Function (1) Jumps to the FEND or END instruction in the same program file. Operation Error (1) In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and an error code is stored into SD0.
Page 338 DI,EI,IMASK Program Execution Control Instructions 6.6.1 Interrupt disable/enable instructions, interrupt program mask (DI,EI,IMASK) DI,EI,IMASK High Basic Process Redundant Universal LCPU performance When the Basic model QCPU is used Sequence program IMASK IMASK : Interrupt mask data or head number of the devices where the interrupt mask data is stored (BIN 16 bits) Internal Devices Setting R, ZR...
Page 339 DI,EI,IMASK IMASK (1) Enables/disables the execution of the interrupt program marked by the designated interrupt pointer by using the bit pattern of 8 points from the device designated by • 1(ON)..Interrupt program execution enabled • 0(OFF)..Interrupt program execution disabled (2) The interrupt pointer numbers corresponding to the individual bits are as shown below: b14 b13 b12 b11 b10 b9 I15 I14...
Page 340 DI,EI,IMASK Operation Error (1) There are no operation errors associated with the DI, EI or IMASK instruction. Program Example (1) The following program is designed to enable the execution of only the interrupt programs having the interrupt pointer numbers I1 and I3 while X0 is ON. [Ladder Mode] [List Mode] Device...
Page 341 DI,EI,IMASK When the High Performance model QCPU/Process CPU/Redundant CPU/Universal model QCPU or LCPU is used Sequence program IMASK IMASK : Head number of the devices where the interrupt mask data is stored (BIN 16 bits) Internal Devices Setting R, ZR Constants Other Data...
Page 342 DI,EI,IMASK IMASK (1) Enables/disables the execution of the interrupt program marked by the designated interrupt pointer by using the bit pattern of 16 points from the device designated by • 1(ON)..Interrupt program execution enabled • 0(OFF) ..Interrupt program execution disabled (2) The interrupt pointer numbers corresponding to the individual bits are as shown below: b14 b13 b12 b11 b10 b9 I15 I14...
Page 343 DI,EI,IMASK 1. An interrupt pointer occupies 1 step. Stored at step 50 IRET • For the information on interrupt conditions, link direct devices, refer to the QnUCPU User’s Manual(Function Explanation, Program Fundamentals) or Qn(H)/QnPH/QnPRHCPU User’s Manuall(Function Explanation, Program Fundamentals) 2. The DI state (interrupt disabled) is active during the execution of an interrupt program.
Page 344 DI,EI,IMASK Operation Error (1) In the following case, an operation error occurs, the error flag (SM0) turns ON, and an error code is stored into SD0. • The device specified by exceeds the range of the corresponding device. (For the Universal model QCPU, LCPU.) (Error code: 4101) Program Example (1) The following program creates an execution enabled state for the interrupt program marked...
Page 345 IRET 6.6.2 Recovery from interrupt programs (IRET) IRET High Basic Process Redundant Universal LCPU performance IRET IRET Internal Devices Setting R, ZR Constants Other Data Word Word –– –– Function (1) Indicates the completion of interrupt program processing. (2) Returns to sequence program processing following the execution of the IRET instruction. Operation Error (1) In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and an error code is stored into SD0.
Page 346 IRET Program Example (1) The following program adds 1 to D0 if M0 is ON when the number 3 interrupt is generated. [Ladder Mode] [List Mode] Device Step Instruction 6-144...
Page 347 RFS(P) I/O Refresh Instructions 6.7.1 I/O refresh (RFS(P)) RFS(P) High Basic Process Redundant Universal LCPU performance Command Command RFSP RFSP : Head number of the devices to be refreshed (bits) n : Number of refreshes (BIN 16 bits) Internal Devices Setting Constants R, ZR...
Page 348 RFS(P) Operation Error (1) In the following case, an operation error occurs, the error flag (SM0) turns ON, and an error code is stored into SD0. • The range n points from the device designated by exceeds the proximate I/O range. (Error code: 4101) Program Example (1) The following program refreshes X100 to X11F and Y200 to Y23F when M0 goes ON.
Page 349 UDCNT1 Other Convenient Instructions 6.8.1 Counter 1-phase input up or down (UDCNT1) UDCNT1 High Basic Process Redundant Universal LCPU performance Command UDCNT1 UDCNT1 + 0: Input number for count input (bits) + 1: For setting count up/down (bits) •OFF: Count up (add numbers when counting) •ON: Count down (subtract numbers when counting) : Number of the counter to be enabled to start counting with the UDCNT1 instruction (Device name) n : Value to set (BIN 16 bits)
Page 350 UDCNT1 • The counter designated at is a ring counter. If it is counting up when the present value is 32767, the present value will become 32768. Further, if it is counting down when the present value is 32768, the present value will become 32767. The count processing performed on the present value is as shown below: 32768 32767...
Page 351 UDCNT1 Program Example (1) This program uses C0 (Up/Down counter) to count the number of times X0 goes from OFF to ON after X20 has gone ON. [Ladder Mode] [List Mode] Instruction Device Step [Operation] Down C0 present value 0 1 2 3 4 5 6 7 6 5 4 3 2 1 0 1 2 3 2 1 0 - - - - - C0 contact 6-149...
Page 352 UDCNT2 6.8.2 Counter 2-phase input up or down (UDCNT2) UDCNT2 High Basic Process Redundant Universal LCPU performance Command UDCNT2 UDCNT2 + 0: Input number for count input (A phase pulse) (bits) + 1: Input number for count input (B phase pulse) (bits) : Number of the counter to be enabled to start counting with the UDCNT2 instruction (Device name) n : Value to set (BIN 16 bits) Internal Devices...
Page 353 UDCNT2 • The counter designated at is a ring counter. If it is counting up when the present value is 32767, the present value will become 32768. Further, if it is counting down when the present value is 32768, the present value will become 32767. The count processing performed on the present value is as shown below: 32768 32767...
Page 354 UDCNT2 Program Example (1) The following program performs a count operation as instructed by C0 (count up or down) on the status of X0 and X1 after X20 has gone ON. [Ladder Mode] [List Mode] Step Instruction Device [Operation] COM present value C0 contact 6-152...
Page 355 TTMR 6.8.3 Teaching timer (TTMR) TTMR High Basic Process Redundant Universal LCPU performance Command TTMR TTMR + 0: The device where measurement value is stored (BIN 16 bit) + 1: For CPU module system use (BIN 16 bit) n : Measurement value multiplier (BIN 16 bits) Internal Devices Setting Constants...
Page 356 TTMR Operation Error (1) In the following case, an operation error occurs, the error flag (SM0) turns ON, and an error code is stored into SD0. • The device specified by exceeds the range of the corresponding device. (For the Universal model QCPU, LCPU.) (Error code: 4101) Program Example (1) The following program stores the amount of time that X0 is ON at D0.
Page 357 STMR 6.8.4 Special function timer (STMR) STMR High Basic Process Redundant Universal LCPU performance Command STMR STMR : Timer number (word) n : Value to set (BIN 16 bits). + 0: Off delay timer output (bits) + 1: One shot timer output after OFF (bits) + 2: One shot timer output after ON (bits) + 3: ON delay and Off delay timer output (bits) Internal Devices...
Page 358 STMR (3) The timer contact goes ON at the leading edge of the command for the STMR instruction, and after the trailing edge is reached, the timer coil goes OFF at the trailing edge of the STMR instruction command. The timer contact is used by the CPU module system, and cannot be used by the user. Command for STMR instruction (Coil)
Page 359 STMR Program Example (1) The following program turns Y0 and Y1 ON and OFF once each second (flicker) when X20 is ON. (Uses 100 ms timer) [Ladder Mode] [List Mode] Step Instruction Device [Timing Chart] M1, Y0 M2, Y1 1 sec 1 sec 6-157...
Page 360 ROTC 6.8.5 Rotary table shortest direction control (ROTC) ROTC High Basic Process Redundant Universal LCPU performance Command ROTC ROTC : Measures the number of table rotations (for system use) (BIN 16 bits) : Call station number (BIN 16 bits) : Call item number (BIN 16 bits) n1 : Number of divisions of table (2 to 32767) (BIN 16 bits) n2 : Number of low-speed sections (value from 0 to less than n1) (BIN 16 bits) : A phase input signal (bits)
Page 361 ROTC +2 is the 0 point detection output signal that goes ON when item number 0 has arrived at the No. 0 station. When the device designated by +2 goes ON while the ROTC instruction is being executed, +0 is cleared. It is best to perform this clear operation first, then to begin shortest direction control with the ROTC instruction.
Page 362 ROTC Program Example (1) The following program deposits the item at section D2 on a 10-division rotary table at the station at section D1, and the two sections ahead and behind this determine the rotation direction and control speed of the motor when the table is being rotated at low speed. [Ladder Mode] [List Mode] Device...
Page 363 RAMP 6.8.6 Ramp signal (RAMP) RAMP High Basic Process Redundant Universal LCPU performance Command RAMP RAMP n1 : Initial value (BIN 16 bits) n2 : Final value (BIN 16 bits) : Present value (BIN 16 bits) : Number of executions (BIN 16 bits) n3 : Number of shifts (BIN 16 bits) + 0 : Completion device (bits) + 1 : Bit for selecting data retaining at completion (bit)
Page 364 RAMP (2) If the scan is performed for the number of moves specified by n3, the complete device specified by +0 is turned ON. The ON/OFF status of the completion device and the contents of +0 are determined by the ON/OFF status of the device designated by •...
Page 365 RAMP Program Example (1) The following program changes the contents of D0 from 10 to 100 in a total of 6 scans, and saves the contents of D0 when the move has been completed. [Ladder Mode] [List Mode] Instruction Device Step [Timing Chart] 1scan...
Page 366 6.8.7 Pulse density measurement (SPD) High Basic Process Redundant Universal LCPU performance Command : Pulse input (bits) n : Measurement time (unit: ms) (BIN 16 bits) : Head number of the devices where the measurement result will be stored (BIN 16 bits) Internal Devices Setting Constants...
Page 367 1. With the SPD instruction, the argument device data is registered in the work area of the CPU module and counting operation is processed as a system interrupt. (The device data registered in the work area is cleared by turning the execution command OFF, or turning the STOP/RUN switch STOP RUN.) For this reason, the pulses that can be counted must have longer ON and OFF times than the interrupt interval of the CPU module.
Page 368 PLSY 6.8.8 Fixed cycle pulse output (PLSY) PLSY High Basic Process Redundant Universal LCPU performance Command PLSY PLSY n1 : Frequency or the number of the device where frequency is stored (BIN 16 bits) n2 : Outputs count or the number of the device where the outputs count is stored (BIN 16 bits) : Number of the device to which pulses are output (bits) Internal Devices Setting...
Page 369 PLSY 1. With the PLSY instruction, the argument device data is registered in the work area of the CPU module and counting operation is processed as a system interrupt. (The device data registered in the work area is cleared by turning the execution command OFF, or turning the STOP/RUN switch STOP RUN.) For this reason, the pulses that can be output must have longer ON and OFF times than the interrupt interval of the CPU module.
Page 370: Pulse Width Modulation (Pwm)
6.8.9 Pulse width modulation (PWM) High Basic Process Redundant Universal LCPU performance Command n1 : ON time or the number of the device where the ON time is stored (BIN 16 bits) n2 : Frequency or the number of the device where the frequency is stored (BIN 16 bits) : Number of the device to which pulses are output (bits) Internal Devices Setting...
Page 371 1. With the PWM instruction, the argument device data is registered in the work area of the CPU module and counting operation is processed as a system interrupt. (The device data registered in the work area is cleared by turning the execution command OFF, or turning the STOP/RUN switch STOP RUN.) The interrupt interval of individual modules is shown below: CPU Module Type Name...
Page 372: Matrix Input (Mtr)
6.8.10 Matrix input (MTR) High Basic Process Redundant Universal LCPU performance Command : Head input device (bits) : Head output device (bits) : Head number of the devices where matrix input data will be stored (bits) n : Number of input rows (BIN 16 bit) Internal Devices Setting Constants...
Page 373 Operation Error (1) In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and an error code is stored into SD0. • The device other than the input (X) was specified at (Error code: 4101) •...
Page 374 MEMO 6-172...
Page 375: Application Instructions
APPLICATION INSTRUCTIONS Reference Category Processing Details section Logical operations such as logical sum, logical product, Section 7.1 Logical operation instructions etc. Rotation instruction Rotation of designated data Section 7.2 Section 7.3 Shift instruction Shift of designated data Section 7.4 Bit processing instructions Sets and resets bit data;...
Page 376: Logical Operation Instructions
Logical operation instructions (1) The logical operation instructions perform logical sum, logical product or other logical operations in 1-bit units. Example Formula for Category Processing Details Operation Logical product Becomes 1 only when both input A and A · B (AND) input B are 1;...
Page 377 WAND(P),DAND(P) 7.1.1 Logical products with 16-bit and 32-bit data (WAND(P),DAND(P)) WAND(P),DAND(P) High Basic Process Redundant Universal LCPU performance When two data are set ( indicates an instruction symbol of WAND/DAND. Command WAND,DAND Command WANDP,DANDP : Data for a logical product operation or the head number of the devices where the data is stored (BIN 16/32 bits) : Head number of the devices where the logical product operation result will be stored (BIN 16/32 bits) Internal Devices Setting...
Page 378 WAND(P),DAND(P) DAND (1) Conducts a logical product operation on each bit of the 32-bit data for the device designated and the 32-bit data for the device designated by , and stores the results at the device designated by (2) When bit devices are designated, the bit devices below the points designated as digits are regarded as "0"...
Page 379 WAND(P),DAND(P) (2) The following program performs a logical product operation on the data at D99 and D100, and the 24-bit data between X30 and X47 when X8 is ON, and stores the results at D99 and D100. [Ladder Mode] [List Mode] Step Instruction Device...
Page 380 WAND(P),DAND(P) When three data are set ( indicates an instruction symbol of WAND/DAND. Command WAND,DAND Command WANDP,DANDP : Data for a logical product operation or the head number of the devices where the data is stored (BIN 16/32 bits) : Head number of the devices where the logical product operation result will be stored (BIN 16/32 bits) Internal Devices Setting Constants...
Page 381 WAND(P),DAND(P) as "0" in the operation. (See Program Example (3)) Operation Error (1) There are no operation errors associated with the WAND(P) or DAND(P) instruction. Program Example (1) The following program performs a logical product operation on the data from X10 to X1B and the data at D33 when XA is ON, and stores the results at D40.
Page 382 WAND(P),DAND(P) (3) The following program masks the digit in the hundred-thousands place of the 8-digit BCD value at D10 and D11 (sixth digit from the end) to 0 when XA is ON, and outputs the results to from Y10 to Y2B. [Ladder Mode] [List Mode] Step...
Page 383: Block Logical Products (Bkand(P))
BKAND(P) 7.1.2 Block logical products (BKAND(P)) BKAND(P) High Basic Process Redundant Universal LCPU performance Command BKAND BKAND Command BKANDP BKANDP : Head number of the devices where data on which a logical operation will be conducted is stored (BIN 16 bits) : Data for a logical operation or head number of the devices where the data for the logical operation is stored (BIN 16 bits) : Head number of the devices where the operation result will be stored (BIN 16 bits)
Page 384 BKAND(P) (2) The constant designated by can be between -32768 and 32767 (BIN 16-bit data). 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 b8b7 BKAND...
Page 385: Logical Sums Of 16-Bit And 32-Bit Data (Wor(P),Dor(P))
WOR(P),DOR(P) 7.1.3 Logical sums of 16-bit and 32-bit data (WOR(P),DOR(P)) WOR(P),DOR(P) High Basic Process Redundant Universal LCPU performance When two data are set ( indicates an instruction symbol of WOR/DOR. Command WOR, DOR Command WORP, DORP : Data for a logical sum operation or head number of the devices where the data is stored (BIN 16/32 bits) : Head number of the devices where the logical sum operation result will be stored (BIN 16/32 bits) Internal Devices Setting...
Page 386 WOR(P),DOR(P) (1) Conducts a logical sum operation on each bit of the 32-bit data of the device designated by and the 32-bit data of the device designated by , and stores the results at the device designated by (2) For bit devices, the bit devices after the points designated by digit specification are regarded as "0"...
Page 387 WOR(P),DOR(P) (2) The following program performs a logical sum operation on the 32-bit data from X0 to X1F, and on the hexadecimal value FF00FF00 when XB is turned ON, and stores the results at D66 and D67. [Ladder Mode] [List Mode] Step Instruction Device...
Page 388 WOR(P),DOR(P) When three data are set ( indicates an instruction symbol of WOR/DOR. Command WOR, DOR Command WORP, DORP : Data for a logical sum operation or head number of the devices where the data is stored (BIN 16/32 bits) : Head number of the devices where the logical sum operation result will be stored (BIN 16/32 bits) Internal Devices Setting...
Page 389 WOR(P),DOR(P) (1) Conducts a logical sum operation on each bit of the 32-bit data of the device designated by and the 32-bit data of the device designated by , and stores the results at the device designated by (2) When bit devices are designated, the bit devices below the points designated as digits are regarded as "0"...
Page 390 WOR(P),DOR(P) (2) The following program performs a logical sum operation on the 32-bit data at D0 and D1, and the 24-bit data from X20 to X37, and stores the results at D23 and D24 when M8 is ON. [Ladder Mode] [List Mode] Step Instruction...
Page 391: Block Logical Sum Operations (Bkor(P))
BKOR(P) 7.1.4 Block logical sum operations (BKOR(P)) BKOR(P) High Basic Process Redundant Universal LCPU performance Command BKOR BKOR Command BKORP BKORP *1 : Head number of the devices where data on which a logical operation will be conducted is stored (BIN 16 bits) *1 : Data for a logical operation or head number of the devices where the data for the logical operation is stored (BIN 16 bits)
Page 392 BKOR(P) (2) The constant designated by can be between 32768 and 32767 (BIN 16-bit data). 0 0 1 1 1 1 0 0 1 1 0 0 0 0 1 1 0 0 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 1 0 1 0 1 1 0 1...
Page 393: 16-Bit And 32-Bit Exclusive Or Operations (Wxor(P),Dxor(P))
WXOR(P),DXOR(P) 7.1.5 16-bit and 32-bit exclusive OR operations (WXOR(P),DXOR(P)) WXOR(P),DXOR(P) High Basic Process Redundant Universal LCPU performance When two data are set indicates an instruction symbol of WXOR/DXOR. Command WXOR, DXOR Command WXORP, DXOR : Data for an exclusive OR operation or head number of the devices where the data is stored (BIN 16/32 bits) : Head number of the devices where the exclusive OR operation result will be stored (BIN 16/32 bits) Internal Devices Setting...
Page 394 WXOR(P),DXOR(P) DXOR (1) Conducts an exclusive OR operation on each bit of the 32-bit data of the device designated and the 32-bit data of the device designated by , and stores the results at the device designated by D + 1 (2) For bit devices, the bit devices after the points designated by digit specification are regarded as "0"...
Page 395 WXOR(P),DXOR(P) (2) The following program compares the bit pattern of the 32-bit data from X20 to X3F with the bit pattern of the data at D9 and D10 when X6 is ON, and stores the number of differing bits at D16. [Ladder Mode] [List Mode] Step...
Page 396 WXOR(P),DXOR(P) When three data are set indicates an instruction symbol of WXOR/DXOR. Command WXOR, DXOR Command WXORP, DXORP : Data for an exclusive OR operation or head number of the devices where the data is stored (BIN 16/32 bits) : Head number of the devices where the exclusive OR operation result will be stored (BIN 16/32 bits) Internal Devices Setting Constants...
Page 397 WXOR(P),DXOR(P) DXOR (1) Conducts an exclusive OR operation on each bit of the 32-bit data of the device designated and the 32-bit data of the device designated by , and stores the results at the device designated by (2) For bit devices, the bit devices after the points designated by digit specification are regarded as "0"...
Page 398 WXOR(P),DXOR(P) (2) The following program conducts an exclusive OR operation on the data at D20 and D21, and the data at D30 and D31 when X10 is turned ON, and stores the results at D40 and D41. [Ladder Mode] [List Mode] Step Instruction Device...
Page 399: Block Exclusive Or Operations (Bkxor(P))
BKXOR(P) 7.1.6 Block exclusive OR operations (BKXOR(P)) BKXOR(P) High Basic Process Redundant Universal LCPU performance Command BKXOR BKXOR Command BKXORP BKXORP *1 : Head number of the devices where data on which a logical operation will be conducted is stored (BIN 16 bits) *1 : Data for a logical operation or head number of the devices where the data for the logical operation is stored (BIN 16 bits) *1 : Head number of the devices where the operation result will be stored (BIN 16 bits)
Page 400 BKXOR(P) (2) The constant designated by can be between 32768 and 32767 (BIN 16-bit data). 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 b8 b7 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1...
Page 401: 16-Bit And 32-Bit Data Exclusive Nor Operations (Wxnr(P),Dxnr(P))
WXNR(P),DXNR(P) 7.1.7 16-bit and 32-bit data exclusive NOR operations (WXNR(P),DXNR(P)) WXNR(P),DXNR(P) High Basic Process Redundant Universal LCPU performance When two data are set ( indicates an instruction symbol of WXNR/DXNR. Command WXNR, DXNR Command WXNRP, DXNRP : Data for an exclusive NOR operation or head number of the devices where the data is stored (BIN 16/32 bits) : Head number of the devices where the exclusive NOR operation result will be stored (BIN 16/32 bits) Internal Devices Setting...
Page 402 WXNR(P),DXNR(P) DXNR (1) Conducts an exclusive NOR operation on the 32-bit data of the device designated by the 32-bit data of the device designated by , and stores the results at the device designated by (2) For bit devices, the bit devices after the points designated by digit specification are regarded as "0"...
Page 403 WXNR(P),DXNR(P) (2) The following program compares the bit patterns of the 32-bit data located from X20 to X3F with the bit patterns of the data at D16 and D17 when X6 is ON, and stores the number of identical bit patterns at D18. [Ladder Mode] [List Mode] Step...
Page 404 WXNR(P),DXNR(P) When three data are set ( indicates an instruction symbol of WXNR/DXNR. Command WXNR, DXNR Command WXNRP, DXNRP : Data for an exclusive NOR operation or head number of the devices where the data is stored (BIN 16/32 bits) : Head number of the devices where the exclusive NOR operation result will be stored (BIN 16/32 bits) Internal Devices Setting...
Page 405 WXNR(P),DXNR(P) DXNR (1) Conducts an exclusive NOR operation on the 32-bit data of the device designated by the 32-bit data of the device designated by , and stores the results at the device designated by (2) For bit devices, the bit devices after the points designated by digit specification are regarded as "0"...
Page 406 WXNR(P),DXNR(P) (2) The following program performs an exclusive NOR operation on the 32-bit data at D20 and D21 and the data at D10 and D11 when X10 is turned ON, and stores the result to D40 and D41. [Ladder Mode] [List Mode] Step Instruction...
Page 407: Block Exclusive Nor Operations (Bkxnr(P))
BKXNR(P) 7.1.8 Block exclusive NOR operations (BKXNR(P)) BKXNR(P) High Basic Process Redundant Universal LCPU performance Command BKXNR BKXNR Command BKXNRP BKXNRP *1 : Head number of the devices where data on which a logical operation will be conducted is stored (BIN 16 bits) *1 : Data for a logical operation or head number of the devices where the data for the logical operation is stored (BIN 16 bits) *1 : Head number of the devices where the operation result will be stored (BIN 16 bits) : Number of operation data blocks (BIN 16 bits)
Page 408 BKXNR(P) (2) The constant designated by can be between 32768 and 32767 (BIN 16-bit data). 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 b8b7 1 1 0 0 1 1 0 0 0 0 1 1 0 0 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0...
Page 409: Rotation Instruction
ROR(P),RCR(P) Rotation instruction 7.2.1 Right rotation of 16-bit data (ROR(P),RCR(P)) ROR(P),RCR(P) High Basic Process Redundant Universal LCPU performance indicates an instruction symbol of ROR/RCR. Command ROR, RCR Command RORP, RCRP : Head number of the devices to rotate (BIN 16 bits) : Number of rotations (0 to 15) (BIN 16 bits) Internal Devices Setting...
Page 410 ROR(P),RCR(P) (2) When a bit device is designated for , a rotation is performed within the device range specified by digit specification. The number of bits by which a rotation is carried out is the remainder of n/(specified number of bits). For example, when n 15 and (specified number of bits) 12 bits, the remainder of 15/12...
Page 411 ROR(P),RCR(P) Operation Error (1) There are no operation errors associated with the ROR(P) or RCR(P) instructions. Program Example (1) The following program rotates the contents of D0, not including the carry flag, 3 bits to the right when XC is turned ON. [Ladder Mode] [List Mode] Step...
Page 412 ROL(P),RCL(P) 7.2.2 Left rotation of 16-bit data (ROL(P),RCL(P)) ROL(P),RCL(P) High Basic Process Redundant Universal LCPU performance indicates an instruction symbol of ROL/RCL. Command ROL, RCL Command ROLP, RCLP : Head number of the devices to rotate (BIN 16 bits) : Number of rotations (0 to 15) (BIN 32 bits) Internal Devices Setting Constants...
Page 413 ROL(P),RCL(P) (2) When a bit device is designated for , a rotation is performed within the device range specified by digit specification. The number of bits by which a rotation is executed is the remainder of n/(specified number of bits). For example, when n 15 and (specified number of bits) 12 bits, the remainder of 15/12...
Page 414 ROL(P),RCL(P) Operation Error (1) There are no operation errors associated with the ROL(P) or RCL(P) instructions. Program Example (1) The following program rotates the contents of D0, not including the carry flag, 3 bits to the left when XC is turned ON. [Ladder Mode] [List Mode] Step...
Page 415: Right Rotation Of 32-Bit Data (Dror(P),Drcr(P))
DROR(P),DRCR(P) 7.2.3 Right rotation of 32-bit data (DROR(P),DRCR(P)) DROR(P),DRCR(P) High Basic Process Redundant Universal LCPU performance indicates an instruction symbol of DROR/DRCR. Command DROR, DRCR Command DRORP, DRCRP : Head number of the devices to rotate (BIN 32 bits) : Number of rotations (0 to 31) (BIN 16 bits) Internal Devices Setting Constants...
Page 416 DROR(P),DRCR(P) DRCR (1) Rotates 32-bit data, including carry flag, at device designated by n bits to the right. The carry flag goes ON or OFF depending on its status prior to the execution of the DRCR instruction. Carry flag (SM700) b30 b29 b28 b27 b15b14 b5 b4 b3...
Page 417 DROR(P),DRCR(P) (2) The following program rotates the contents of D0 and D1, including the carry flag, 4 bits to the right when XC is ON. [Ladder Mode] [List Mode] Step Instruction Device [Operation] Carry flag (SM700) b28b27 b24b23 b20b19 b12b11 b8b7 b4b3 D0, D1 0...
Page 418: Left Rotation Of 32-Bit Data (Drol(P),Drcl(P))
DROL(P),DRCL(P) 7.2.4 Left rotation of 32-bit data (DROL(P),DRCL(P)) DROL(P),DRCL(P) High Basic Process Redundant Universal LCPU performance indicates an instruction symbol of DROL/DRCL. Command DROL, DRCL Command DROLP, DRCLP : Head number of the devices to rotate (BIN 32 bits) : Number of rotations (0 to 31) (BIN 16 bits) Internal Devices Setting Constants...
Page 419 DROL(P),DRCL(P) (2) When a bit device is designated for , a rotation is performed within the device range specified by digit specification. The number of bits by which a rotation is executed is the remainder of n /(specified number of bits). For example, when n 31 and (specified number of bits) 24 bits, the remainder of 31/24...
Page 420: Shift Instruction
SFR(P),SFL(P) Shift instruction 7.3.1 n-bit shift to right or left of 16-bit data (SFR(P),SFL(P)) SFR(P),SFL(P) High Basic Process Redundant Universal LCPU performance indicates an instruction symbol of SFR/SFL. Command SFR, SFL Command SFRP, SFLP : Head number of the devices where shift data is stored (BIN 16 bits) : Number of shifts (0 to 15) (BIN 16 bits) Internal Devices Setting...
Page 421 SFR(P),SFL(P) The number of bits by which a shift is executed is the remainder of n/(specified number of bits). For example, when n 15 and (specified number of bits) 8 bits, the remainder of 15/8 1 is "7", and the data is shifted 7 bits. (3) Specify any of 0 to 15 as n.
Page 422 SFR(P),SFL(P) Program Example (1) The following program shifts the data of D0 to the right by the number of bits designated by D100 when X20 is turned ON. [Ladder Mode] [List Mode] Step Instruction Device [Operation] b14 b13b12 b11b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 D100 Carry flag b14 b13b12 b11b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0...
Page 423: 1-Bit Shift To Right Or Left Of N-Bit Data (Bsfr(P),Bsfl(P))
BSFR(P),BSFL(P) 7.3.2 1-bit shift to right or left of n-bit data (BSFR(P),BSFL(P)) BSFR(P),BSFL(P) High Basic Process Redundant Universal LCPU performance indicates an instruction symbol of BSFR/BSFL. Command BSFR, BSFL Command BSFRP, BSFLP : Head number of the devices to be shifted (bits) : Number of devices to which shift is executed (BIN 16 bits) Internal Devices Setting...
Page 424 BSFR(P),BSFL(P) Operation Error (1) In the following case, an operation error occurs, the error flag (SM0) turns ON, and an error code is stored into SD0. • The range of the device n points from a device designated by , or exceeds the relevant device.
Page 425: N-Bit Shift To Right Or Left Of N-Bit Data (Sftbr(P),Sftbl(P))
SFTBR(P),SFTBL(P) 7.3.3 n-bit shift to right or left of n-bit data (SFTBR(P),SFTBL(P)) SFTBR(P),SFTBL(P) Ver. High Basic Process Redundant Universal LCPU performance QnU(D)(H)CPU: The serial number (first five digits) is "10102" or later. QnUDE(H)CPU: The serial number (first five digits) is "10102" or later. indicates an instruction symbol of SFTBR/SFTBL.
Page 426 SFTBR(P),SFTBL(P) SFTBL(P) (1) This instruction shifts the n1 bits data in the devices starting from the device specified by to the left by n2 bits. n1=10, n2=4 ＋8 ＋7 ＋6 ＋5 ＋4 ＋3 ＋2 ＋1 Carry flag ＋8 ＋7 ＋6 ＋5 ＋4 ＋3...
Page 427 SFTBR(P),SFTBL(P) Program Example (1) The following program shifts the data of Y10 to Y17 (8 bits) specified by to the right by 2 bits (n2), when M0 is turned on. [Ladder Mode] [List Mode] Instruction Device Step [Operation] Carry flag (SM700) (2) The following program shifts the data of Y21 to Y2C (12 bits) specified by to the left by 5...
Page 428: 1-Word Shift To Right Or Left Of N-Word Data (Dsfr(P),Dsfl(P))
DSFR(P),DSFL(P) 7.3.4 1-word shift to right or left of n-word data (DSFR(P),DSFL(P)) DSFR(P),DSFL(P) High Basic Process Redundant Universal LCPU performance indicates an instruction symbol of DSFR/DSFL. Command DSFR, DSFL Command DSFRP, DSFLP : Head number of the devices to be shifted (BIN 16 bits) : Number of devices to which shift is executed (BIN 16 bits) Internal Devices Setting...
Page 429 DSFR(P),DSFL(P) Operation Error (1) In the following case, an operation error occurs, the error flag (SM0) turns ON, and an error code is stored into SD0. • The range of the device n points from a device designated by , or exceeds the relevant device.
Page 430: N-Bit Shift To Right Or Left Of N-Word Data (Sftwr(P),Sftwl(P))
SFTWR(P),SFTWL(P) 7.3.5 n-bit shift to right or left of n-word data (SFTWR(P),SFTWL(P)) SFTWR(P),SFTWL(P) Ver. High Basic Process Redundant Universal LCPU performance QnU(D)(H)CPU: The serial number (first five digits) is "10102" or later. QnUDE(H)CPU: The serial number (first five digits) is "10102" or later. indicates an instruction symbol of SFTWR/SFTWL.
Page 431 SFTWR(P),SFTWL(P) SFTWL(P) (1) This instruction shifts the n1 words data in the devices starting from the device specified by to the left by n2 words. n1=9, n2=4 ＋8 ＋7 ＋6 ＋5 ＋4 ＋3 ＋2 ＋1 ＋8 ＋7 ＋6 ＋5 ＋4 ＋3 ＋2 ＋1...
Page 432 SFTWR(P),SFTWL(P) (2) The following program shifts the 12 words (n1) data in the devices starting from D21 specified by to the left by 5 words (n2), when M0 is turned on. [Ladder Mode] [List Mode] Instruction Device Step [Operation] × ×...
Page 433: Bit Processing Instructions
BSET(P),BRST(P) Bit processing instructions 7.4.1 Bit set and reset for word devices (BSET(P),BRST(P)) BSET(P),BRST(P) High Basic Process Redundant Universal LCPU performance indicates an instruction symbol of BSET/BRST. Command BSET, BRST Command BSETP, BRSTP : Number of the device whose bits are set/reset (BIN 16 bits) : Number of the bit to be set/reset (0 to 15) (BIN 16 bits) Internal Devices Setting...
Page 434 BSET(P),BRST(P) Operation Error (1) There are no operation errors associated with the BSET(P) or BRST(P) instructions. Program Example (1) The following program resets the 8th bit of D8 (b8) to 0 when XB is OFF, and sets the 3rd bit of D8 (b3) to 1 when XB is ON.
Page 435: Bit Tests (Test(P),Dtest(P))
TEST(P),DTEST(P) 7.4.2 Bit tests (TEST(P),DTEST(P)) High Basic Process Redundant Universal LCPU performance TEST(P),DTEST(P) indicates an instruction symbol of TEST/DTEST. Command TEST, DTEST Command TESTP, DTESTP : Number of the device where bit data to be extracted is stored (BIN 16 bits) : Location of the bit data to be extracted (0 to 15 (TEST)/0 to 31 (DTEST)) (BIN 16/32 bits) : Number of the bit device where the extracted data will be stored (bits) Internal Devices...
Page 436 TEST(P),DTEST(P) (3) The position designated by indicates the position of an individual bit in a 2-word data block (0 to 31). When 32 or more is designated at , the target is the bit data at the position indicated by the remainder of n / 32. For example, when n 34, the target is the data at b2 since the remainder of 34 / 32 1 is "2".
Page 437 TEST(P),DTEST(P) (2) The following program turns Y40 ON or OFF, depending on the status of the 19th bit of the 2-word data (W0 and W1). [Ladder Mode] [List Mode] Step Instruction Device [Operation] 1 0 1 1 0 0 1 0 1 0 1 1 0 0 0 0 1 0 1 1 0 1 1 1 0 1 1 1 0 1 1 0 Turns Y40 OFF since b19 is "0."...
Page 438: Batch Reset Of Bit Devices (Bkrst(P))
BKRST(P) 7.4.3 Batch reset of bit devices (BKRST(P)) BKRST(P) High Basic Process Redundant Universal LCPU performance Command BKRST BKRST Command BKRSTP BKRSTP : Head number of the devices to be reset (bits) : Number of the devices to be reset (BIN 16 bits) Internal Devices Setting Constants...
Page 439 BKRST(P) Program Example (1) The following program turns OFF devices from M0 to M7 when X0 is turned ON. [Ladder Mode] [List Mode] Step Instruction Device [Operation] 1 0 0 1 1 1 0 0 0 0 0 0 0 0 0 0 Not changed (2) The following program sets data from 2nd bit (b2) of D10 to 1st bit (b1) of D11 to 0 when X20 is turned ON.
Page 440: Data Processing Instructions
SER(P),DSER(P) Data processing instructions 7.5.1 16-bit and 32-bit data searches (SER(P),DSER(P)) SER(P),DSER(P) High Basic Process Redundant Universal LCPU performance Command SER, DSER Command SERP, DSERP : Search data or head number of the devices where the search data is stored (BIN 16/32 bits) : Data to be searched or head number of the devices where the data to be searched is stored (BIN 16 bits) : Head number of the devices where the search result will be stored (BIN 16 bits) : Number of searches (BIN 16 bits)
Page 441 SER(P),DSER(P) DSER (1) Searches n points from the device designated by in 32-bit units (2 n points in 16-bit units.) regarding 32-bit data of the device designated by +1 and as a keyword. Then, the number of matches with the keyword is stored at the device designated by +1, and the first matched device number (in the relative number from ) is stored at the device...
Page 442 SER(P),DSER(P) Program Example (1) The following program searches D100 to D105 for the contents of D0 when X20 is ON, and stores the search results at W0 and W1. [Ladder Mode] [List Mode] Step Instruction Device [Operation] Search data Data to be searched D100 Search results D101...
Page 443: Bit And 32-Bit Data Checks (Sum(P),Dsum(P))
SUM(P),DSUM(P) 7.5.2 16-bit and 32-bit data checks (SUM(P),DSUM(P)) SUM(P),DSUM(P) High Basic Process Redundant Universal LCPU performance indicates an instruction symbol of SUM/DSUM. Command SUM, DSUM Command SUMP, DSUMP : Head number of the devices where the total number of bits of "1" is counted (BIN 16/32 bits) : Head number of the devices where the total number of the bits will be stored (BIN 16/32 bits) Internal Devices Setting...
Page 444 SUM(P),DSUM(P) Operation Error (1) There are no operation errors associated with the SUM(P) or DSUM(P) instructions. Program Example (1) The following program stores the number of bits which are ON from X8 to X17 into D0 when X10 is turned ON. [Ladder Mode] [List Mode] Step...
Page 445: Decoding From 8 To 256 Bits (Deco(P))
DECO(P) 7.5.3 Decoding from 8 to 256 bits (DECO(P)) DECO(P) High Basic Process Redundant Universal LCPU performance Command DECO DECO Command DECOP DECOP : Data to be decoded or the number of the device where the data to be decoded is stored (BIN 16 bits) : Head number of the devices where the decoding result will be stored (Device name) : Valid bit length (1 to 8), 0: No processing (BIN 16 bits) Internal Devices...
Page 446 DECO(P) Operation Error (1) In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and an error code is stored into SD0. • The value of n is not in the 0 to 8 range. (Error code: 4100) •...
Page 447: Encoding From 256 To 8 Bits (Enco(P))
ENCO(P) 7.5.4 Encoding from 256 to 8 bits (ENCO(P)) ENCO(P) High Basic Process Redundant Universal LCPU performance Command ENCO ENCO Command ENCOP ENCOP : Head number of the device where the data to be encoded is stored (Device name) : Number of the device where the encoding result will be stored (BIN 16 bits) : Valid bit length (1 to 8), 0: No processing (BIN 16 bits) Internal Devices Setting...
Page 448 ENCO(P) Operation Error (1) In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and an error code is stored into SD0. • The value of n is not in the 0 to 8 range. (Error code: 4100) •...
Page 449: Segment Decode (Seg(P))
SEG(P) 7.5.5 7-segment decode (SEG(P)) SEG(P) High Basic Process Redundant Universal LCPU performance Command Command SEGP SEGP : Data to be decoded or head number of the devices where the data to be decoded is stored (BIN 16 bits) : Head number of the devices where the decoding result will be stored (BIN 16 bits) Internal Devices Setting Constants...
Page 450 SEG(P) 7-segment decode display Configuration of 7 Display Data Hexa- Segments Bit Pattern decimal 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 Head number of bit device Lowest bit of word device Program Example (1) The following program converts the data from XC to XF to 7-segment display data and outputs it to Y38 to Y3F when X0 is turned ON.
Page 451: Bit Dissociation Of 16-Bit Data (Dis(P))
DIS(P) 7.5.6 4-bit dissociation of 16-bit data (DIS(P)) DIS(P) High Basic Process Redundant Universal LCPU performance Command Command DISP DISP : Head number of the devices where data to be dissociated is stored (BIN 16 bits) : Head number of the devices where the dissociated data will be stored (BIN 16 bits) : Number of dissociations (1 to 4), 0: No processing (BIN 16 bits) Internal Devices Setting...
Page 452 DIS(P) Operation Error (1) In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and an error code is stored into SD0. • The range n-points from exceeds the relevant device. (Error code: 4101) •...
Page 453: Bit Linking Of 16-Bit Data (Uni(P))
UNI(P) 7.5.7 4-bit linking of 16-bit data (UNI(P)) UNI(P) High Basic Process Redundant Universal LCPU performance Command Command UNIP UNIP : Head number of the devices where data to be linked is stored (BIN 16 bits) : Head number of the devices where the linked data will be stored (BIN 16 bits) : Number of links (1 to 4), 0: No processing (BIN 16 bits) Internal Devices Setting...
Page 454 UNI(P) Operation Error (1) In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and an error code is stored into SD0. • The range n-points from exceeds the relevant device. (Error code: 4101) •...
Page 455: Dissociation Or Linking Of Random Data (Ndis(P),Nuni(P))
NDIS(P),NUNI(P) 7.5.8 Dissociation or linking of random data (NDIS(P),NUNI(P)) NDIS(P),NUNI(P) High Basic Process Redundant Universal LCPU performance indicates an instruction symbol of NDIS/NUNI. Command NDIS, NUNI Command NDISP, NUNIP : Head number of the devices where data to be dissociated/linked is stored (BIN 16 bits) : Head number of the devices where the dissociated/linked data will be stored (BIN 16 bits) : Head number of the devices where the units of dissociation/linking will be stored (BIN 16 bits) Internal Devices...
Page 456 NDIS(P),NUNI(P) (2) The number of dissociated bits designated at can be designated within a range of 1 to 16 bits. (3) Bits from the device number designated at to the device number where "0" is stored are processed as dissociated bits. (4) Do not overlap the device range for data to be dissociated( to end range of ) with the...
Page 457 NDIS(P),NUNI(P) Operation Error (1) In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and an error code is stored into SD0. • The number of bits to be dissociated or linked as specified by , or the device use range specified by exceeds the final device number of their respective devices.
Page 458 NDIS(P),NUNI(P) (2) The following program links the lower 4 bits of data from D10, the lower 3 bits of data from D11, and the lower 6 bits of data from D12, and stores at D0. [Ladder Mode] [List Mode] Device Step Instruction [Operation]...
Page 459: Data Dissociation And Linking In Byte Units (Wtob(P),Btow(P))
WTOB(P),BTOW(P) 7.5.9 Data dissociation and linking in byte units (WTOB(P),BTOW(P)) WTOB(P),BTOW(P) High Basic Process Redundant Universal LCPU performance indicates an instruction symbol of WTOB/BTOW. Command WTOB, BTOW Command WTOBP, BTOWP : Head number of the devices where data to be dissociated/linked in byte units is stored (BIN 16 bits) : Head number of the devices where the result of dissociated/linking in byte units will be stored (BIN 16 bits) : Number of byte data to be dissociated/linked (BIN 16 bits) Internal Devices...
Page 460 WTOB(P),BTOW(P) (2) Setting the number of bytes with n automatically determines the range of the 16-bit data designated by and the range of the devices to store the byte data designated by (3) No processing will be conducted when the number of bytes designated by n is "0". (4) The "00 "...
Page 461 WTOB(P),BTOW(P) (4) The upper 8 bits of the byte storage device designated by are ignored, and the lower 8 bits are used. (5) Linking is correctly processed even when the device range ( +(n-1)) where the data to be linked is stored overlaps with the device range ( -1)) where the linked data will be stored.
Page 462 WTOB(P),BTOW(P) (2) The following program links the lower 8 bits of data from D20 through D25 and stores the result at D10 to D12 when X0 is turned ON. [Ladder Mode] [List Mode] Instruction Device Step [Operation] 6 bytes Upper byte is ignored. 7-88...
Page 463: Maximum Value Search For 16- And 32-Bit Data (Max(P),Dmax(P))
MAX(P),DMAX(P) 7.5.10 Maximum value search for 16- and 32-bit data (MAX(P),DMAX(P)) MAX(P),DMAX(P) High Basic Process Redundant Universal LCPU performance indicates an instruction symbol of MAX/DMAX. Command MAX, DMAX Command MAXP ,DMAXP : Head number of the devices where a maximum value is searched (BIN 16/32 bits) : Head number of the devices where the maximum value search result will be stored (BIN 16/32 bits) : Number of data blocks to be searched (BIN 16 bits) Internal Devices...
Page 464 MAX(P),DMAX(P) DMAX (1) Searches in the n points of 32-bit BIN data, from the device designated by , for the maximum value and stores the searched maximum value at the device designated by Starts the search from the device designated by and stores the location, specified in the number of points counted from , of the device where the maximum value is found first at...
Page 465 MAX(P),DMAX(P) (2) The following program searches for the maximum value from the32-bit data at D0 to D7, and stores it at D100 to D103 when X20 is turned ON. [Ladder Mode] [List Mode] Step Instruction Device [Operation] D1, D0 3786213 (BIN) D101, D100 8744740 D3, D2...
Page 466: Minimum Value Search For 16- And 32-Bit Data (Min(P),Dmin(P))
MIN(P),DMIN(P) 7.5.11 Minimum value search for 16- and 32-bit data (MIN(P),DMIN(P)) MIN(P),DMIN(P) High Basic Process Redundant Universal LCPU performance indicates an instruction symbol of MIN/DMIN. Command MIN, DMIN Command MINP, DMINP : Head number of the devices where a minimum value is searched (BIN 16/32 bits) : Head number of the devices where the minimum value search result will be stored (BIN 16/32 bits) : Number of data blocks to be searched (BIN 16 bits) Internal Devices...
Page 467 MIN(P),DMIN(P) DMIN (1) Searches in the n points of 32-bit BIN data, from the device designated by , for the minimum value and stores searched minimum value at the devices designated by Starts the search from the device designated by and stores the location, specified in the number of points counted from , of the device where the minimum value is found first at...
Page 468 MIN(P),DMIN(P) (2) The following program, when X20 is turned ON, searches for the minimum value from the 32-bit data contained from D0 to D7, and stores it from D100 to D103. [Ladder Mode] [List Mode] Step Instruction Device [Operation] D1,D0 57020175 (BIN) D101,D100 69386...
Page 469: Bin 16 And 32 Bits Data Sort Operations (Sort,Dsort)
SORT,DSORT 7.5.12 BIN 16 and 32 bits data sort operations (SORT,DSORT) SORT,DSORT High Basic Process Redundant Universal LCPU performance indicates an instruction symbol of SORT/DSORT. Command SORT, DSORT : Head device number in the table to be sorted (BIN 16/32 bits) : Number of data blocks to be sorted (BIN 16 bits) : Number of data blocks to be compared in one sort operation (BIN 16 bits) : Number of the bit device to be turned ON at the completion of the sort operation (bits)
Page 470 SORT,DSORT (2) Several scans are required for sorts performed by the SORT instruction. The number of scans executed until completion is the value obtained by dividing the maximum number of times executed until the completion of the sort by the number of data blocks compared at one execution designated by .
Page 471 SORT,DSORT (2) Several scans are required for sorts performed by the DSORT instruction. The number of scans executed until completion is the value obtained by dividing the maximum number of times executed until the completion of the sort by the number of data blocks compared at one execution designated by .
Page 472 SORT,DSORT Program Example (1) The following program sorts the BIN 16-bit data in 10 points from D0 in the ascending/ descending order when X10 is turned ON. [Ladder Mode] [List Mode] Step Instruction Device [Operation] Data after sort -999 Data before sort 12345 12345 -999...
Page 473: Calculation Of Totals For 16-Bit Data (Wsum(P))
WSUM(P) 7.5.13 Calculation of totals for 16-bit data (WSUM(P)) WSUM(P) High Basic Process Redundant Universal LCPU performance Command WSUM WSUM Command WSUMP WSUMP : Head number of the devices where data to be summed are stored (BIN 16 bits) : Head number of the devices where the sum will be stored (BIN 32 bits) : Number of data blocks (BIN 16 bits) Internal Devices Setting...
Page 474 WSUM(P) Program Example (1) The following program adds the 16-bit BIN data from D10 to D14, and stores it in D100 and D101 when X1C is turned ON. [Ladder Mode] [List Mode] Step Instruction Device [Operation] 4500 (BIN) 2500 (BIN) 3276 (BIN) 14948 (BIN) D101,D100...
Page 475: Calculation Of Totals For 32-Bit Data (Dwsum(P))
DWSUM(P) 7.5.14 Calculation of totals for 32-bit data (DWSUM(P)) DWSUM(P) High Basic Process Redundant Universal LCPU performance Command DWSUM DWSUM Command DWSUMP DWSUMP : Head number of the devices where data to be summed are stored (BIN 32 bits) : Head number of the devices where the sum will be stored (BIN 64 bits) : Number of data blocks (BIN 16 bits) Internal Devices Setting...
Page 476 DWSUM(P) Program Example (1) The following program adds the 32-bit BIN data at D100 to D107, and stores the result at D10 and D13 when X20 is turned ON. [Ladder Mode] [List Mode] Device Step Instruction [Operation] D101,D100 11245600 (BIN) D103,D102 27543200 (BIN) D13 to...
Page 477: Calculation Of Averages For 16-Bit Or 32-Bit Data (Mean(P),Dmean(P))
MEAN(P),DMEAN(P) 7.5.15 Calculation of averages for 16-bit or 32-bit data (MEAN(P),DMEAN(P)) MEAN(P),DMEAN(P) Ver. High Basic Process Redundant Universal LCPU performance • QnU(D)(H)CPU: The serial number (first five digits) is "10102" or later. • QnUDE(H)CPU: The serial number (first five digits) is "10102" or later. indicates an instruction symbol of MEAN/DMEAN.
Page 478 MEAN(P),DMEAN(P) Operation Error (1) In any of the following cases, an operation error occurs, the error flag (SM0) turns on, and an error code is stored into SD0. • The value specified by n is other than 0 to 32767. (Error code: 4100) •...
Page 479: Structure Creation Instructions
FOR,NEXT Structure creation instructions 7.6.1 FOR to NEXT instruction loop (FOR,NEXT) FOR,NEXT High Basic Process Redundant Universal LCPU performance Repeat program NEXT NEXT n : Number of repetitions of FOR to NEXT loop (1 to 32767) (BIN 16 bits) Internal Devices Setting Constants R, ZR...
Page 480 FOR,NEXT Operation Error (1) In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and an error code is stored into SD0. • An END, FEND or GOEND instruction was executed before the execution of a NEXT instruction and after the execution of a FOR instruction.
Page 481 FOR,NEXT Remark 1. To force an end to the repetitious execution of the FOR to NEXT loop during the execution of the loop, insert a BREAK instruction. See 7.6.2 for details concerning the use of the BREAK instruction. 2. Use the EGP/EGF instruction to perform the pulse operation of an index-modified program between the FOR and NEXT instructions.
Page 482: Forced End Of For To Next Instruction Loop (Break(P))
BREAK(P) 7.6.2 Forced end of FOR to NEXT instruction loop (BREAK(P)) BREAK(P) High Basic Process Redundant Universal LCPU performance Command BREAK BREAK Command BREAKP BREAKP : Number of the device where the remaining number of loops will be stored (BIN 16 bits) Pn : Number of the pointer (device name (pointer)) where the program is branched at the forced end of a loop.
Page 483 BREAK(P) Operation Error (1) In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and an error code is stored into SD0. • The BREAK instruction is used in a case other than with the FOR to NEXT instruction loop.
Page 484: Subroutine Program Calls (Call(P))
CALL(P) 7.6.3 Subroutine program calls (CALL(P)) CALL(P) High Basic Process Redundant Universal LCPU performance Command CALL CALL Command CALLP CALLP Command CALL CALL Command CALLP CALLP : Head pointer number of a subroutine program (Device name) : Number of the device to be passed as an argument to a subroutine program (bits, BIN 16 bits, BIN 32 bits) Internal Devices Setting Constants...
Page 485 CALL(P) (2) When function devices (FX, FY, FD) are used by a subroutine program, specify a device with corresponding to the function device. The contents to the devices specified by are as indicated below. (a) Prior to execution of the subroutine program, bit data is transmitted to FX, and word data is transmitted to FD.
Page 486 CALL(P) (6) The device used in the argument of the CALL (P) instruction should not be used in a subroutine program. If used, it will not be possible to obtain accurate calculations. (Refer to the following program example.) (7) When the device, either timer or counter, is used in the argument of the CALL(P) instruction, only the current value is transmitted/received.
Page 487 CALL(P) Correct operation example The following example shows the operation performed when D0 is specified for FD0 in the subroutine program and D4 is used in the subroutine program. [Program example] [Operation performed after subroutine program execution] Immediately after the At the time of Before the execution execution of CALL...
Page 488 CALL(P) Operation Error (1) In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and an error code is stored into SD0. • The device specified for the argument cannot be secured for the data size. (Error code: 4101) •...
Page 489: Return From Subroutine Programs (Ret)
7.6.4 Return from subroutine programs (RET) High Basic Process Redundant Universal LCPU performance Internal Devices Setting R, ZR Constants Other Data Word Word –– –– Function (1) Indicates end of subroutine program (2) When the RET instruction is executed, returns to the step following the CALL (P), FCALL (P), ECALL (P), EFCALL (P) or XCALL instruction which called the subroutine program.
Page 490: Subroutine Program Output Off Calls (Fcall(P))
FCALL(P) 7.6.5 Subroutine program output OFF calls (FCALL(P)) FCALL(P) High Basic Process Redundant Universal LCPU performance Command FCALL FCALL Command FCALLP FCALLP Command FCALL FCALL Command FCALLP FCALLP : Head pointer number of a subroutine program (Device name) : Number of the device to be passed as an argument to a subroutine program (bits, BIN 16 bits, BIN 32 bits) Internal Devices Setting Other...
Page 491 FCALL(P) (b) The operation results for the individual coil instructions following non-execution processing will be as follows, regardless of the ON/OFF status of the individual contacts: OUT instruction ..Forced OFF SET instruction RST instruction SFT instruction ..Maintains status Basic instructions Application instructions PLS instruction...
Page 492 FCALL(P) (4) When function devices (FX, FY, FD) are used by a subroutine program, specify a device with corresponding to the function device. The contents to the devices specified by are as indicated below. (a) Prior to execution of the subroutine program, bit data is transmitted to FX, and word data is transmitted to FD.
Page 493 FCALL(P) (6) Up to 16 nesting levels are possible with the FCALL(P) instruction. However, this 16 levels is the total number of levels in the CALL(P), FCALL(P), ECALL(P), EFCALL(P), and XCALL instructions. CALL FCALL CALL CALL FCALL P10 FCALL P20 FEND Operation Error (1) In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and...
Page 494: Subroutine Calls Between Program Files (Ecall(P))
ECALL(P) 7.6.6 Subroutine calls between program files (ECALL(P)) ECALL(P) High Basic Process Redundant Universal LCPU performance Command ECALL ECALL File name Command ECALLP ECALLP File name Command ECALL ECALL File name Command ECALLP File name ECALLP File name : Name of the program file to be called (character string) : Head pointer number of a subroutine program (Device name) : Number of the device to be passed as an argument to a subroutine program (bits, BIN 16 bits, BIN 32 bits) Internal Devices...
Page 495 ECALL(P) (2) Only the file name of a program file stored in the drive 0 (program memory/internal RAM) can be designated for a file name. (3) It is not necessary to designate the extension (.QPG) with the file name. (Only .QPG files will be acted on.) (4) When function devices (FX, FY, FD) are used by a subroutine program, specify a device corresponding to the function device with .
Page 496 ECALL(P) (5) From can be used by the ECALL instruction. (6) The device used in the argument of the ECALL instruction should not be used in a subroutine program. If used, it will not be possible to obtain accurate calculations. (Refer to the following program example.) Incorrect operation example The following example shows the operation performed when D0 is specified for FD0 in the...
Page 497 ECALL(P) Correct operation example The following example shows the operation performed when D0 is specified for FD0 in the subroutine program and D4 is used in the subroutine program. [Program example] [MAIN] [ABC] [Operation performed after subroutine program execution] Immediately after the At the time of Before the execution execution of ECALL...
Page 498 ECALL(P) Operation Error (1) In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and an error code is stored into SD0. • The device specified for the argument cannot be secured for the data size. (Error code: 4101) •...
Page 499: Subroutine Output Off Calls Between Program Files (Efcall(P))
EFCALL(P) 7.6.7 Subroutine output OFF calls between program files (EFCALL(P)) EFCALL(P) High Basic Process Redundant Universal LCPU performance Command EFCALL EFCALL File name Command EFCALLP EFCALLP File name Command EFCALL EFCALL File name Command EFCALLP File name EFCALLP File name : Name of the program file to be called (character string) : Head pointer number of a subroutine program (Device name) : Number of the device to be passed as an argument to a subroutine program (bits, BIN 16 bits, BIN 32 bits)
Page 500 EFCALL(P) (b) The operation results for the individual coil instructions following non-execution processing will be as follows, regardless of the ON/OFF status of the individual contacts: OUT instruction ..Forced OFF SET instruction RST instruction SFT instruction ..Maintains status Basic instructions Application instructions PLS instruction...
Page 501 EFCALL(P) (4) Only the file name of a program file stored in the drive 0 (program memory/internal RAM) can be designated for a file name. (5) It is not necessary to designate the extension (.QPG) with the file name. (Only .QPG files will be acted on.) (6) When function devices (FX, FY, FD) are used by a subroutine program, specify a device corresponding to the function device with [MAIN]...
Page 502 EFCALL(P) can be used with the EFCALL (P) instruction. (8) The number of function devices used by subroutine programs must be identical to the number of arguments used by the EFCALL (P) instruction. Further, the function devices should be identical to the types of arguments used by the EFCALL (P) instruction. (9) Up to 16 levels of nesting can be used with the EFCALL (P) instruction.
Page 503: Subroutine Program Call (Xcall)
XCALL 7.6.8 Subroutine program call (XCALL) XCALL Ver. High Basic Process Redundant Universal LCPU performance Basic model QCPU: The upper five digits of the serial No. are "04122" or larger. Command XCALL XCALL : Head pointer number of a subroutine program (Device name) : Number of the device to be passed as an argument to a subroutine program (bits, BIN 16 bits, BIN 32 bits) Internal Devices Setting...
Page 504 XCALL (2) Operation of XCALL instruction varies according to the CPU module type. The following program example shows the operation of XCALL instruction for each CPU module. [Program example] Subroutine program (P1) call by XCALL instruction P1 subroutine program [ON/OFF timing of X0] (1) Turning X0 ON (3) Turning X0 OFF (OFF...
Page 505 XCALL (3) When function devices (FX, FY, FD) are used by a subroutine program, specify a device with corresponding to the function device. The contents to the devices specified by are as indicated below. (a) Prior to execution of the subroutine program, bit data is transmitted to FX, and word data is transmitted to FD.
Page 506 XCALL (7) Up to 16 nesting levels can be used with the XCALL instruction. However, this 16 levels is the total number of levels in the CALL(P), FCALL(P), ECALL(P), EFCALL(P), and XCALL instructions. XCALL P0 X0 XCALL P10 X10 XCALL P20 X20 FEND (8) The device used for the argument of the XCALL instruction must not be used in a subroutine...
Page 507 XCALL Operation Error (1) In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and an error code is stored into SD0. • The device specified for the argument cannot be secured for the data size. (Error code: 4101) •...
Page 508: Refresh Instruction (Com)
7.6.9 Refresh instruction (COM) High Basic Process Redundant Universal LCPU performance Refer to Section 7.6.10 for the COM instruction of the following CPU modules. • Basic model QCPU of serial No. 04122 or later • High Performance model QCPU of serial No. 04012 or later •...
Page 509 (3) At the point of the execution of the COM instruction, the CPU module temporarily stops the processing of the sequence program, and performs the same operation as ordinary data processing as well as auto refresh of intelligent function modules (including link refreshes) at the END processing.
Page 510 (6) If the scan time from the linked station is longer than the sequence program scan time at the host station, designating the COM instruction at the host station will not increase the speed of data communications. Sequence program 0 COM END 0 COM Link scan The programs in which the COM instruction cannot be used are shown below:...
Page 511: Select Refresh Instruction (Com)
7.6.10 Select Refresh Instruction (COM) Refer to Section 7.6.9. for the COM instruction of the following CPU modules. • Basic model QCPU of serial No. 04121 or later • High Performance model QCPU of serial No. 04011 or later • Process CPU of serial No. 07031 or later Ver.
Page 512 (3) When selecting refresh items (a) Select refresh items by SD778, and set SM775 to ON. The following table shows the refresh items that can be designated by turning SM775 ON/OFF and with SD778. QCPU LCPU Refresh Item When SM775 When SM775 When SM775 When SM775...
Page 513 Refresh between the multiple CPUs by the COM instruction is performed under the following condition. • Receiving operation from other CPUs : When b4 of SD778 (auto refresh in the CPU shared memory) is 1. • Sending operation from host CPU : When b15 of SD778 (communication with peripheral device is executed/not executed) is 0.
Page 514 (4) Upon the execution of the COM instruction, the CPU module suspends the processing of the sequence program, and refreshes the designated refresh item. Execution of COM Execution of COM instruction instruction Refreshes the designated Refreshes the designated refresh items refresh items (5) The COM instruction can be used in a sequence program any number of times.
Page 515 1. The COM instruction cannot be used in low speed execution type programs, fixed scan execution type programs or interrupt programs. 2. For the redundant CPU, there are restrictions on use of the COM instruction. Refer to the manual below for details. •...
Page 516: Select Refresh Instruction (Ccom(P))
CCOM 7.6.11 Select Refresh Instruction (CCOM(P)) CCOM Ver. High Basic Process Redundant Universal LCPU performance QnU(D)(H)CPU: The serial number (first five digits) is "10102" or later. QnUDE(H)CPU: The serial number (first five digits) is "10102" or later. Command CCOM CCOM Command CCOMP CCOMP...
Page 517: Index Modification Of Entire Ladder (Ix,Ixend)
IX,IXEND 7.6.12 Index modification of entire ladder (IX,IXEND) IX,IXEND High Basic Process Redundant Universal LCPU performance Ladder where index modification is performed IXEND I X END : Head number of the devices where index modification data is stored (BIN 16 bits) Internal Devices Setting R, ZR...
Page 518 IX,IXEND (2) Index modification for device numbers is accomplished in the manner as below: By setting a modification value to each of the devices, the set modification values are added to the all device numbers of the devices used in the ladder between the IX and IXEND instructions. The program is executed using the index modified device numbers.
Page 519 IX,IXEND (8) Whether the program will be expanded or a user needs to create the program is depending on your GPP function software package. The index register should be added to the index modification ladder established with the IX and IXEND instructions. * D100 X1Z2 M62Z4 Y24Z3...
Page 520 IX,IXEND Operation Error (1) In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and an error code is stored into SD0. • The IX and IXEND instructions are not used together. (Error code: 4231) •...
Page 521 IXDEV,IXSET 7.6.13 Designation of modification values in index modification of entire ladders (IXDEV,IXSET) IXDEV,IXSET High Basic Process Redundant Universal LCPU performance IXDEV IXDEV IXSET IXSET Dummy contact Offset designation sections : Head number of the devices where index modification data is stored (pointer only) P (Pointer) : Head number of the devices where index modification data will be stored (except a pointer) (BIN 16 bits) Internal Devices...
Page 522 IXDEV,IXSET (6) If two offsets for two identical types of device have been set in the offset designation area, the last value set will be valid. (7) The IXDEV and IXSET instructions should be treated as a pair. (8) Any value from 0 to 32767 is valid for ZR. (The offset value will be the remainder of the quotient of the designated device number divided by 32768.) (9) The dummy contacts in the offset specifying part are valid for only LD and AND located within the range of the IXDEV-IXSET instructions.
Page 523 IXDEV,IXSET Program Example (1) The following program changes the modification values for input (X), output (Y), data register (D) and pointer (P). When using a basic model QCPU, the devices R, U/G, J, ZR and P cannot be used. [Ladder Mode] [List Mode] Device Step...
Page 524: Data Table Operation Instructions
FIFW(P) Data Table Operation Instructions 7.7.1 Writing data to the data table (FIFW(P)) FIFW(P) High Basic Process Redundant Universal LCPU performance Command FIFW FIFW Command FIFWP FIFWP : Data to be written into the table or the number of the device where the data is stored (BIN 16 bits) : Head number of the table (BIN 16 bits) Internal Devices Setting...
Page 525 FIFW(P) Operation Error (1) In the following case, an operation error occurs, the error flag (SM0) turns ON, and an error code is stored into SD0. • The data table range exceeds the relevant device range when the FIFW instruction is executed.
Page 526: Reading Oldest Data From Tables (Fifr(P))
FIFR(P) 7.7.2 Reading oldest data from tables (FIFR(P)) FIFR(P) High Basic Process Redundant Universal LCPU performance Command FIFR FIFR Command FIFRP FIFRP : Head number of the devices where the data read from the table will be stored (BIN 16 bits) : Head number of the table (BIN 16 bits) Internal Devices Setting...
Page 527 FIFR(P) Program Example (1) The following program stores the R1 data from the table R0 to R7 at D0 when X10 is turned [Ladder Mode] [List Mode] Step Instruction Device [Operation] Data table Data table Number of stored data blocks Number of stored data blocks 4321 4321...
Page 528: Reading Newest Data From Data Tables (Fpop(P))
FPOP(P) 7.7.3 Reading newest data from data tables (FPOP(P)) FPOP(P) High Basic Process Redundant Universal LCPU performance Command FPOP FPOP Command FPOPP FPOPP : Head number of the devices where the data read from the table will be stored (BIN 16 bits) : Head number of the table (BIN 16 bits) Internal Devices Setting...
Page 529 FPOP(P) Program Example (1) The following program stores the data stored last in the data table R0 to R7 at D0 when X10 is turned ON. [Ladder Mode] [List Mode] Step Instruction Device [Operation] Data table Data table -123 -123 1400 1400 1234...
Page 530: Deleting And Inserting Data From And In Data Tables (Fdel(P),Fins(P))
FDEL(P),FINS(P) 7.7.4 Deleting and inserting data from and in data tables (FDEL(P),FINS(P)) FDEL(P),FINS(P) High Basic Process Redundant Universal LCPU performance indicates an instruction symbol of FDEL/FINS. Command FDEL, FINS Command FDELP, FINSP : Head number of the devices where data to be inserted is stored (BIN 16 bits) Head number of the devices where the data to be deleted will be stored (BIN 16 bits) : Head number of the table (BIN 16 bits) : Location on the table where data is inserted/deleted (BIN 16 bits)
Page 531 FDEL(P),FINS(P) FINS (1) Inserts the 16-bit data designated by at the nth block of the data table designated by After the execution of the FINS instruction, the data in the table following the inserted block is all dropped one position. Data table Data table Number of stored...
Page 532 FDEL(P),FINS(P) Program Example (1) The following program deletes the second data from the table R0 to R7 and stores the deleted data at D0 when X10 is turned ON. [Ladder Mode] [List Mode] Step Instruction Device [Operation] Data table Data table X10:ON -123 -123...
Page 533: Buffer Memory Access Instruction
FROM(P),DFRO(P) Buffer memory access instruction 7.8.1 Reading 1-/2-word data from the intelligent function module (FROM(P),DFRO(P)) FROM(P),DFRO(P) Ver. High Basic Process Redundant Universal LCPU performance Universal model QCPU: Other than Q00UJCPU indicates an instruction symbol of FROM/DFRO. Command FROM, DFRO Command FROMP, DFROP n1 : Head I/O number of an intelligent function module (BIN 16 bits) n2 : Head address of data to be read (BIN 16 bits)
Page 534 FROM(P),DFRO(P) DFRO (1) Reads the data in (n3 2) words from the buffer memory address designated by n2 of the the intelligent function module designated by n1, and stores the data into the area starting from the device designated by Intelligent function module buffer memory CPU module...
Page 535 FROM(P),DFRO(P) Program Example (1) The following program reads the digital value of CH1 of the A68AD mounted at I/O numbers 040 to 05F into D0 when X0 is turned ON. (Reads 1 word of data from address 10 of the buffer memory.) [Ladder Mode] [List Mode]...
Page 536: Writing 1-/2-Word Data To Intelligent Function Module (To(P),Dto(P))
TO(P),DTO(P) 7.8.2 Writing 1-/2-word data to intelligent function module (TO(P),DTO(P)) TO(P),DTO(P) High Basic Process Redundant Universal LCPU performance indicates an instruction symbol of TO/DTO. Command TO, DTO Command TOP, DTOP n1 : Head I/O number of an intelligent function module (BIN 16 bits) n2 : Head address of the area where data is written (BIN 16 bits) : Data to be written or head number of the devices where the data to be written is stored (BIN 16/32 bits) n3 : Number of data blocks to be written (BIN 16 bits)
Page 537 TO(P),DTO(P) Writes the data stored in n3 2 points starting from the device designated by into the area starting from buffer memory address designated by n2 of the intelligent function module designated by n1. Intelligent function module buffer memory CPU module Device designated by S n2+1...
Page 538 TO(P),DTO(P) Program Example (1) The following program sets the CH1 and CH2 of the Q68ADV mounted at the I/O numbers 040 to 04F to the "A/D conversion" mode, when X0 is turned ON. (Writes 3 into the buffer memory address 0.) [Ladder Mode] [List Mode] Device...
Page 539: Display Instructions
Display instructions 7.9.1 Print ASCII code instruction (PR) High Basic Process Redundant Universal LCPU performance Command : ASCII code or head number of the devices where the ASCII code is stored (character string) : Head number of the output module to which the ASCII code will be output (bits) Internal Devices Setting Constants...
Page 540 (b) If SM701 is OFF, everything from the device designated by to the 00 code will be the target of the operation. Device where ASCII code is stored Upper 8 bits Lower 8 bits Output Y b8 b7 Head of output ASCII code output Scheduled Printer or...
Page 541 Operation Error (1) In the following case, an operation error occurs, the error flag (SM0) turns ON, and an error code is stored into SD0. • There is no 00 code within the range of the device specified by when SM701 is OFF. (Error code: 4101) Program Example (1) The following program converts the string "ABCDEFGHIJKLMNOP"...
Page 542: Print Comment Instruction (Prc)
7.9.2 Print comment instruction (PRC) High Basic Process Redundant Universal LCPU performance Command : Head number of the device which prints the comment (Device name) : Head number of the output module which outputs the comment (bits) Internal Devices Setting Other R, ZR Constants...
Page 543 [Timing Chart] Y30 to Y37 Preprocessing (several scans) 30 ms (Strobe signal) 30ms x 16 = 480 ms (Flag indicating strobe signal is being output) SM721 (File access in progress flag) PRC instruction cannot be executed again. SM720 (File access completion flag) None of Instructions other than PRC instruction (SP.FREAD,...
Page 544 1. For device comments used with the PRC instruction, use comment files stored in the memory card Standard Rom. Comment files stored in the program memory cannot be used. 2. The comment file used by the PRC instruction is set at the "PLC File Setting" option in the PLC parameter dialog box.
Page 545: Error Display And Annunciator Reset Instruction (Ledr)
LEDR 7.9.3 Error display and annunciator reset instruction (LEDR) LEDR High Basic Process Redundant Universal LCPU performance Command LEDR LEDR Internal Devices Setting R, ZR Constants Other Data Word Word –– –– Function Resets the self-diagnosis error display so that annunciator display or operation can be continued. With one execution of this instruction, either error display or annunciator is reset.
Page 546 LEDR (2) Operations when an annunciator (F) is ON. (a) When the CPU module has no LED display The following operations will be conducted when the LEDR instruction is executed: 1) "USER" LED flickers, and is turned OFF 2) The annunciators (F) stored in SD62 and SD64 are reset, and the F numbers for SD65 to SD79 are moved up.
Page 547 LEDR Remark 1. The defaults for the error item numbers set in special registers SD207 to SD209 and order of priority are given in the table below: Factor number Priority Meaning Remarks (Hexadecimal) Power supply cut AC DOWN Redundant base unit power supply voltage SINGLE PS.DOWN drop (QCPU only) SINGLE PS.ERROR...
Page 548: Debugging And Failure Diagnosis Instructions
CHKST,CHK 7.10 Debugging and failure diagnosis instructions 7.10.1 Special format failure checks (CHKST,CHK) CHKST,CHK High Basic Process Redundant Universal LCPU performance Command CHKST CHKST Check condition (Only a contact is valid; b contact is ignored) Only input (X) can be used Up to 150 contacts can be connected Internal Devices Setting...
Page 549 CHKST,CHK (b) The contact instruction prior to the CHK instruction does not control the execution of the CHK instruction, but rather sets the check conditions. Advance command (X4) Advance operation (Y50) Advance Retract operation (Y51) Retract Advance end sensor (X0) Retract end sensor (X1) turns ON at the detection turns ON at the detection...
Page 550 CHKST,CHK (2) Depending on the designated contact, the CHK instruction undergoes processing identical to that shown for the ladder below: CHKST (Detection by both advance and retraction end sensors during advance operation of the conveyor) Max. 150 contacts X +1 Y SM80 Coil No.
Page 551 CHKST,CHK (7) Place LD and AND instructions prior to the CHK instruction to establish a check condition. Check conditions cannot be set using other contact instructions. If a check condition has been set with LDI or ANI, the processing for the check condition they specify will not be conducted.
Page 552: Changing Check Format Of Chk Instruction (Chkcir,Chkend)
CHKCIR,CHKEND 7.10.2 Changing check format of CHK instruction (CHKCIR,CHKEND) CHKCIR,CHKEND High Basic Process Redundant Universal LCPU performance When the GX Developer is used (High Performance model QCPU/Process CPU/ Redundant CPU) Command CHKST CHKST Refer to Section 7.10.1. SM400 CHKCIR CHKCIR Ladder pattern to be checked Max.
Page 553 CHKCIR,CHKEND (a) The device numbers indicated at check conditions (X2 and X8 in the figure below) will assume index modification values for the individual device numbers (with the exception of annunciators (F)) described in the ladder patterns. Example X10 in the in the figure below would be as follows: When corresponding to check condition X2 Processing performed by ...X12 When corresponding to check condition X8 Processing performed by ...X18...
Page 554 CHKCIR,CHKEND (b) Failure checks check the ON/OFF status of OUT F by using the ladder pattern in the various check conditions. In all check conditions, SM80 will be turned ON if even one of the OUT F is ON in a ladder pattern.
Page 555 CHKCIR,CHKEND (4) The CHKCIR and CHKEND instructions can be written at any step in the program desired. It can be used in up to two locations in all program files being executed. However, the CHKCIR and CHKEND instructions cannot be used in more than 1 location in a single program file.
Page 556: Character String Processing Instructions
BINDA(P),DBINDA(P) 7.11 Character string processing instructions 7.11.1 Conversion from BIN 16-bit or 32-bit to decimal ASCII (BINDA(P),DBINDA(P)) BINDA(P),DBINDA(P) High Basic Process Redundant Universal LCPU performance indicates an instruction symbol of BINDA/DBINDA. Command BINDA, DBINDA Command BINDAP, DBINDAP : BIN data to be converted to ASCII (BIN 16/32 bits) : Head number of the devices where the conversion result will be stored (character string) Internal Devices Setting...
Page 557 BINDA(P),DBINDA(P) (3) The operation results stored at are as follows: (a) The sign "20 " will be stored if the BIN data is positive, and the sign "2D " will be stored if it is negative. (b) The sign "20 "...
Page 558 BINDA(P),DBINDA(P) Operation Error (1) In the following case, an operation error occurs, the error flag (SM0) turns ON, and an error code is stored into SD0. • The device specified by exceeds the range of the corresponding device. (For the Universal model QCPU, LCPU.) (Error code: 4101) Program Example (1) The following example program uses the PR instruction to output the 16-bit BIN data W0...
Page 559: Conversion From Bin 16-Bit Or 32-Bit Data To Hexadecimal Ascii Binha(P),Dbinha(P))
BINHA(P),DBINHA(P) 7.11.2 Conversion from BIN 16-bit or 32-bit data to hexadecimal ASCII (BINHA(P),DBINHA(P)) BINHA(P),DBINHA(P) High Basic Process Redundant Universal LCPU performance indicates an instruction symbol of BINHA/DBINHA. Command BINHA, DBINHA Command BINHAP, DBINHAP : BIN data to be converted to ASCII (BIN 16/32 bits) : Head number of the devices where the conversion result will be stored (character string) Internal Devices Setting...
Page 560 BINHA(P),DBINHA(P) DBINHA (1) Converts the individual digit numbers of hexadecimal notation of the BIN 32-bit data designated by into ASCII codes, and stores the results into the area starting from the device designated by b8b7 ASCII code for the 7th digit ASCII code for the 8th digit ASCII code for the 5th digit ASCII code for the 6th digit...
Page 561 BINHA(P),DBINHA(P) Program Example (1) The following program uses the PR instruction to output the hexadecimal value of the 16-bit BIN data at W0 in ASCII code to Y40 to Y48. [Ladder Mode] [List Mode] Step Instruction Device [Operation] Conducts ASCII output of Y40 to Y48 by using the PR instruction when X0 goes ON. Because SM701 is OFF, The PR instruction will output ASCII code until 00 is encountered.
Page 562: Conversion From Bcd 4-Digit And 8-Digit To Decimal Ascii Data Bcdda(P),Dbcdda(P))
BCDDA(P),DBCDDA(P) 7.11.3 Conversion from BCD 4-digit and 8-digit to decimal ASCII data (BCDDA(P),DBCDDA(P)) BCDDA(P),DBCDDA(P) High Basic Process Redundant Universal LCPU performance indicates an instruction symbol of BCDDA/DBCDDA. Command BCDDA,DBCDDA Command BCDDAP,DBCDDAP : BCD data to be converted to ASCII (BCD 4 digits/8 digits) : Head number of the devices where the conversion result will be stored (character string) Internal Devices Setting...
Page 563 BCDDA(P),DBCDDA(P) (4) The data to be stored at the device designated by +2 differs depending on the ON/OFF status of SM701 (number of characters to output select signal). When SM701 is OFF..Stores "0" When SM701 is ON ..Does not change DBCDDA (1) Converts the individual digit numbers of hexadecimal notation of the BCD 8-digit data designated by...
Page 564 BCDDA(P),DBCDDA(P) Program Example (1) The following program uses the PR instruction to convert BCD 4-digit data (the value at W0) to decimal, and outputs it in ASCII format to Y40 to Y48. [Ladder Mode] [List Mode] Step Instruction Device [Operation] Conducts ASCII output of Y40 to Y48 by using the PR instruction when X0 goes ON.
Page 565: Conversion From Decimal Ascii To Bin 16-Bit And 32-Bit Data Dabin(P),Ddabin(P))
DABIN(P),DDABIN(P) 7.11.4 Conversion from decimal ASCII to BIN 16-bit and 32-bit data (DABIN(P),DDABIN(P)) DABIN(P),DDABIN(P) High Basic Process Redundant Universal LCPU performance indicates an instruction symbol of DABIN/DDABIN. Command DABIN,DDABIN Command DABINP,DDABINP : ASCII data to be converted to BIN value or head number of the devices where the ASCII data is stored (character string) : Head number of the devices where the conversion result will be stored (BIN 16/32 bits) Internal Devices...
Page 566 DABIN(P),DDABIN(P) DDABIN (1) Converts decimal ASCII data stored into the area starting from the device number designated by into BIN 32-bit data, and stores it in the device number designated by b8b7 Sign data ASCII code for billions place ASCII code for ten-millions place ASCII code for hundred-millions place b16b15 ASCII code for hundred-thousands place...
Page 567 DABIN(P),DDABIN(P) Program Example (1) The following program converts the decimal, 5-digit ASCII data and sign set at D20 through D22 to BIN values, and stores the result at D0. [Ladder Mode] [List Mode] Step Instruction Device [Operation] b8b7 (space) (space) (Regarded as -00276) BIN value (2) The following program converts the decimal, 10-digit ASCII data and sign set at D20 through...
Page 568: Conversion From Hexadecimal Ascii To Bin 16-Bit And 32-Bit Data Habin(P),Dhabin(P))
HABIN(P),DHABIN(P) 7.11.5 Conversion from hexadecimal ASCII to BIN 16-bit and 32-bit data (HABIN(P),DHABIN(P)) HABIN(P),DHABIN(P) High Basic Process Redundant Universal LCPU performance indicates an instruction symbol of HABIN/DHABIN. Command HABIN,DHABIN Command HABINP,DHABINP : ASCII data to be converted to BIN value or head number of the devices where the ASCII data is stored (character string) : Head number of the devices where the conversion result will be stored (BIN 16/32 bits) Internal Devices...
Page 569 HABIN(P),DHABIN(P) DHABIN (1) Converts hexadecimal ASCII data stored in the area starting from the device number designated by into BIN 32-bit data, and stores it in the device number designated by b8b7 ASCII code for the 7th digit ASCII code for the 8th digit b16 b15 ASCII code for the 5th digit ASCII code for the 6th digit...
Page 570 HABIN(P),DHABIN(P) Program Example (1) The following program converts the hexadecimal, 4-digit ASCII data set at D20 and D21 to BIN data, and stores the result at D0. [Ladder Mode] [List Mode] Step Instruction Device [Operation] b8b7 22977 Regarded as A63F BIN value A63F (-22977 in decimal...
Page 571: Conversion From Decimal Ascii To Bcd 4-Digit Or 8-Digit Data Dabcd(P),Ddabcd(P))
DABCD(P),DDABCD(P) 7.11.6 Conversion from decimal ASCII to BCD 4-digit or 8-digit data (DABCD(P),DDABCD(P)) DABCD(P),DDABCD(P) High Basic Process Redundant Universal LCPU performance indicates an instruction symbol of DABCD/DDABCD. Command DABCD,DDABCD Command DABCDP,DDABCDP : ASCII data to be converted to BCD value or head number of the devices where the ASCII data is stored (character string) : Head number of the devices where the conversion result will be stored (BCD 4 digits/8 digits) Internal Devices...
Page 572 DABCD(P),DDABCD(P) DDABCD (1) Converts decimal ASCII data stored in the area starting from the device designated by 8-digit BCD data, and stores it into the area starting from the device designated by ASCII code for millions place ASCII code for ten-millions place ASCII code for ten-thousands place ASCII code for hundred-thousands place b31 b28...
Page 573 DABCD(P),DDABCD(P) Program Example (1) The following program converts the decimal ASCII data set from D20 to D22 to BCD 4-digit data, and outputs the results to Y40 to Y4F. [Ladder Mode] Outputs the converted BCD value to a display device. [List Mode] Step Instruction...
Page 574: Reading Device Comment Data (Comrd(P))
COMRD(P) 7.11.7 Reading device comment data (COMRD(P)) COMRD(P) High Basic Process Redundant Universal LCPU performance Command COMRD COMRD Command COMRDP COMRDP : Head number of the devices where a comment to be read is stored (Device name) : Head number of the devices where the read comment will be stored (character string) Other Internal Devices Setting...
Page 575 COMRD(P) (2) If no comment has been registered for the device specified by despite the fact that the comment range setting is made, all of the characters for the comment are processed as "20 " (space). (3) The device number plus 1 where the final character of is stored differs depending on the ON/OFF status of SM701 (number of characters to output select signal).
Page 576 COMRD(P) Program Example (1) The following program stores the comments set at D100 into the area starting from W0 as ASCII when X1C is turned ON. [Ladder Mode] [List Mode] Step Instruction Device [Operation] b8 b7 (space) Comment at D100 (space) LINE A TARGET...
Page 577: Character String Length Detection (Len(P))
LEN(P) 7.11.8 Character string length detection (LEN(P)) LEN(P) High Basic Process Redundant Universal LCPU performance Command Command LENP LENP : Character string or head number of the devices where the character string is stored (character string) : Number of the device where the length of detected character string will be stored (BIN 16 bits) Internal Devices Setting Constants...
Page 578 (1) The following program outputs the length of the character string from D0 to Y40 to Y4F as BCD 4-digit values. [Ladder Mode] Outputs the length of character string to a display device. [List Mode] Step Instruction Device [Operation] b8b7 BCD conversion 0 0 1 0 BCD value "MITSUBISHI" (Characters "ABC" that follow 00 are ignored) 7-204...
Page 579: Conversion From Bin 16-Bit Or 32-Bit To Character String (Str(P),Dstr(P))
STR(P),DSTR(P) 7.11.9 Conversion from BIN 16-bit or 32-bit to character string (STR(P),DSTR(P)) STR(P),DSTR(P) Ver. High Basic Process Redundant Universal LCPU performance Basic model QCPU: The upper five digits of the serial No. are "04122" or larger. indicates an instruction symbol of STR/DSTR. Command STR,DSTR Command...
Page 580 STR(P),DSTR(P) (2) The total number of digits that can be designated by is from 2 to 8. (3) The number of digits that can be designated by +1 as a part of the decimal fraction is from 0 to 5. However, the number of digits following the decimal point must be smaller than or equal to the total number of digits minus 3.
Page 581 STR(P),DSTR(P) DSTR (1) Adds a decimal point to the BIN 32-bit data designated by at the location designated by , converts the data to character string data, and stores it following the device number designated by Total number of digits b8 b7 Number of digits in decimal fraction ASCII code for the...
Page 582 STR(P),DSTR(P) (c) If the total number of digits following the decimal fraction is greater than the number of BIN data digits, a zero will be added automatically and the number converted by shifting to the right, so that it would become "0. ".
Page 583 STR(P),DSTR(P) Program Example (1) The following program converts the BIN 16-bit data stored at D10 when X0 is turned ON in accordance with the digit designation of D0 and D1, and stores the result from D20 to D23. [Ladder Mode] Sets the data.
Page 584 STR(P),DSTR(P) (2) The following program converts the BIN 32-bit data stored at D10 and D11 when X0 is turned ON in accordance with the digit designation of D0 and D1, and stores the result at from D20 to D26. [Ladder Mode] Sets the data.
Page 585: Conversion From Character String To Bin 16-Bit Or 32-Bit Data (Val(P),Dval(P))
VAL(P),DVAL(P) 7.11.10 Conversion from character string to BIN 16-bit or 32-bit data (VAL(P),DVAL(P)) VAL(P),DVAL(P) Ver. High Basic Process Redundant Universal LCPU performance Basic model QCPU: The upper five digits of the serial No. are "04122" or larger (Correspording GX Seveloper :Version 8.00 A or later). indicates an instruction symbol of VAL/DVAL.
Page 586 VAL(P),DVAL(P) For example, if the character string " 123.45" is designated for the area starting from the operation result would be stored at in the following manner: b8 b7 1 2 3 4 5 1 2 3 (2) The total number of characters that can be designated as a character string at is from 2 to 8.
Page 587 VAL(P),DVAL(P) DVAL (1) Converts the character string stored in the area starting from the device designated by BIN 32-bit data, and stores the digits numbers and BIN data in For conversions from character strings to BIN, all data from the device number designated to the device number where "00 "...
Page 588 VAL(P),DVAL(P) (8) In cases where the character string designated by contains "20 " (space) or "30 " (0) between the sign and the first numerical value other than "0", these "20 " and "30 " are ignored in the conversion into a BIN value. Total number of digits Number of digits 6 5 4 3 .
Page 589 VAL(P),DVAL(P) Program Example (1) The following program reads the character string data stored from D20 to D22 as an integer, converts it to a BIN value, and stores it at D0 when X0 is ON. [Ladder Mode] [List Mode] Step Instruction Device [Operation]...
Page 590: Conversion From Floating Decimal Point To Character String Data (Estr(P))
ESTR(P) 7.11.11 Conversion from floating decimal point to character string data (ESTR(P)) ESTR(P) Ver. High Basic Process Redundant Universal LCPU performance Basic model QCPU: The upper five digits of the serial No. are "04122" or larger. Command ESTR ESTR Command ESTRP ESTRP : 32-bit floating decimal point data to be converted or head number of the devices where the data is stored...
Page 591 ESTR(P) When using decimal point format b8 b7 Decimal point format ASCII code for the ASCII code for the sign (total number of digits -1) Total number of digits th digit Number of digits in decimal fraction ASCII code for the ASCII code for the (total number of digits -3) (total number of digits -2)
Page 592 ESTR(P) For example, in a case where there are 8 digits in total, with 3 digits in the decimal fraction part, and the value designated is 1.23456, the operation result would be stored in the area starting from in the following manner: b8 b7 (space) (space)
Page 593 ESTR(P) 4) If the total number of digits, excluding the sign, the decimal point and the decimal fraction part, is greater than the integer part of the 32-bit floating point type real number data, "20 (space)" will be stored between the sign and the integer part. Total number of digits .
Page 594 ESTR(P) (a) The total number of digits that can be designated by +1 is as shown below: When the number of decimal fraction digits is "0" ....Number of digits (max.: 24) When the number of decimal fraction digits is other than "0" ....
Page 595 ESTR(P) 5) The ASCII code "2C " (+) will be stored as the sign for the exponent portion of the value if the exponent is positive in value, and the code "2D " ( ) will be stored if the exponent is a negative value.
Page 596 ESTR(P) Program Example (1) The following program converts the 32-bit floating point type real number data which had been stored at R0 and R1 in accordance with the conversion designation that is being stored at R10 to R12, and stores the result following D0 when X0 goes ON. [Ladder Mode] [List Mode] Step...
Page 597: Conversion From Character String To Floating Decimal Point Data (Eval(P))
EVAL(P) 7.11.12 Conversion from character string to floating decimal point data (EVAL(P)) EVAL(P) Ver. High Basic Process Redundant Universal LCPU performance Basic model QCPU: The upper five digits of the serial No. are "04122" or larger. Command EVAL EVAL Command EVALP EVALP : Character string data to be converted to 32-bit floating decimal point real number data or head number of the...
Page 598 EVAL(P) (b) When using exponent format (space) -1. 320 1E + 10 32-bit floating-point real number . 3 2 0 1 E + 1 0 (3) Excluding the sign, decimal point, and exponent portion of the result, 6 digits of the character string designated by to be converted to a 32-bit floating decimal point type real number will be effective;...
Page 599 EVAL(P) (6) In a case where the ASCII code "20 (space)" or "30 " (0) exists between numbers not including the initial zero in a character string specified by , it will be ignored when the conversion is done. b8b7 (space) -1 .
Page 600 EVAL(P) Program Example (1) The following program converts the character string stored in the area starting from R0 to a 32-bit floating decimal point type real number, and stores the result at D0 and D1 when X20 is turned ON. [Ladder Mode] [List Mode] Step...
Page 601: Conversion From Hexadecimal Bin To Ascii (Asc(P))
ASC(P) 7.11.13 Conversion from hexadecimal BIN to ASCII (ASC(P)) ASC(P) High Basic Process Redundant Universal LCPU performance Command Command ASCP ASCP : Head number of the devices where BIN data to be converted to a character string is stored (BIN 16 bits) : Head number of the devices where the converted character string will be stored (character string) : Number of characters to be stored (BIN 16 bits) Internal Devices...
Page 602 ASC(P) (2) The use of n to set the number of characters causes the BIN data range designated by and the character string storage device range designated by to be set automatically. (3) Processing will be performed accurately even if the device range where BIN data to be converted is being stored overlaps with the device range where the converted ASCII data will be stored.
Page 603: Conversion From Ascii To Hexadecimal Bin (Hex(P))
HEX(P) 7.11.14 Conversion from ASCII to hexadecimal BIN (HEX(P)) HEX(P) High Basic Process Redundant Universal LCPU performance Command Command HEXP HEXP : Head number of the devices where a character string to be converted to BIN data is stored (character string) : Head number of the devices where the converted BIN data will be stored (BIN 16 bits) : Number of characters to be stored (BIN 16 bits) Internal Devices...
Page 604 HEX(P) (3) Accurate processing will be conducted even in cases where the range of devices where the ASCII code to be converted is being stored overlaps with the range of devices that will store the converted BIN data. b8b7 (4) If the number of characters designated by n is not divisible by 4, "0" will be automatically stored after the designated number of characters in the final device number of the devices which are storing the converted BIN values.
Page 605: Extracting Character String Data From The Right Or Left (Right(P),Left(P))
RIGHT(P),LEFT(P) 7.11.15 Extracting character string data from the right or left (RIGHT(P),LEFT(P)) RIGHT(P),LEFT(P) High Basic Process Redundant Universal LCPU performance indicates an instruction symbol of RIGHT/LEFT. Command RIGHT,LEFT Command RIGHTP,LEFTP : Character string or head number of the devices where the character string is stored (character string) : Head number of the devices where the character string consisting of n characters starting from the right or left of will be stored (character string)
Page 606 RIGHT(P),LEFT(P) (2) The NULL code (00 ) indicating the end of the character string is automatically appended at the end of the character string. Refer to 3.2.5 for the format of the character string data. (3) If the number of characters designated by n is "0", the NULL code (00 ) will be stored at LEFT (1) Stores n number of characters from the left side of the character string (the beginning of the...
Page 607 RIGHT(P),LEFT(P) Program Example (1) The following program stores 4 characters of data from the rightmost of the character string stored in the area starting from R0, and stores it into the area starting from D0 when X0 is turned ON. [Ladder Mode] [List Mode] Step...
Page 608: Random Selection From And Replacement In Character Strings Midr(P),Midw(P))
MIDR(P),MIDW(P) 7.11.16 Random selection from and replacement in character strings (MIDR(P),MIDW(P)) MIDR(P),MIDW(P) High Basic Process Redundant Universal LCPU performance indicates an instruction symbol MIDR/MIDW. Command MIDR,MIDW Command MIDRP,MIDWP : Character string or head number of the devices where the character string is stored (character string) : Head number of the devices where a character string data obtained as the result of operation will be stored (character string) : Head number of the devices where the location of the first character and the number of characters will be...
Page 609 MIDR(P),MIDW(P) (2) The NULL code (00 ) indicating the end of the character string is automatically added to the end of the character string. Refer to 3.2.5 for the format of the character string data. (3) No processing will be conducted if the number of characters designated by +1 is "0".
Page 610 MIDR(P),MIDW(P) (4) If the number of characters designated by +1 exceeds the final character from the character string data designated by , data will be stored up to the final character. Before execution b8b7 b8b7 "ABCDEFGHI" After execution "012345678" b8b7 Position counted from the left end of character string data designated by...
Page 611 MIDR(P),MIDW(P) • The +1 value exceeds the number of characters for (Error code: 4101) • The + 0 value is 0. (Error code: 4101) • "00 " does not exist in the specified devices that follow the device specified for (Error code: 4101) Program Example (1) The following program stores the 3rd character through the 6th character from the left of the...
Page 612: Character String Search (Instr(P))
INSTR(P) 7.11.17 Character string search (INSTR(P)) INSTR(P) High Basic Process Redundant Universal LCPU performance Command INSTR INSTR Command INSTRP INSTRP : Character string to be searched or head number of the devices where the character string to be searched is stored (character string) : Character string in which a search is performed or head number of the devices where the character string is stored (character string)
Page 613 INSTR(P) Operation Error (1) In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and an error code is stored into SD0. • The value of n exceeds the number of characters for (Error code: 4100) •...
Page 614: Insertion Of Character String (Strins(P))
STRINS(P) 7.11.18 Insertion of character string (STRINS(P)) STRINS(P) Ver. High Basic Process Redundant Universal LCPU performance QnU(D)(H)CPU: The serial number (first five digits) is "10102" or later. QnUDE(H)CPU: The serial number (first five digits) is "10102" or later. Command STRINS STRINS Command STRINSP...
Page 615 STRINS(P) Operation Error (1) In any of the following cases, an operation error occurs, the error flag (SM0) turns on, and an error code is stored into SD0. • The number of characters in the devices specified by , or the devices specified by ) after the insertion exceeds 16383 characters.
Page 616: Deletion Of Character String (Strdel(P))
STRDEL(P) 7.11.19 Deletion of character string (STRDEL(P)) STRDEL(P) Ver. High Basic Process Redundant Universal LCPU performance QnU(D)(H)CPU: The serial number (first five digits) is "10102" or later. QnUDE(H)CPU: The serial number (first five digits) is "10102" or later. Command STRDEL STRDEL Command STRDELP...
Page 617 STRDEL(P) Operation Error (1) In any of the following cases, an operation error occurs, the error flag (SM0) turns on, and an error code is stored into SD0. • The number of characters in the devices specified by exceeds 16383. (Error code: 4100) •...
Page 618: Floating Decimal Point To Bcd (Emod(P))
EMOD(P) 7.11.20 Floating decimal point to BCD (EMOD(P)) EMOD(P) High Basic Process Redundant Universal LCPU performance Command EMOD EMOD Command EMODP EMODP : 32-bit floating decimal point real number data or head number of the devices where the floating decimal point real number data is stored (real number) : Decimal fraction digits data (BIN 16 bits) : Head number of the devices where the data after break down into BCD will be stored (BIN 16 bits)
Page 619 EMOD(P) 0 . 03542768 3542770 1 . 5 4 3 2 1E + 2 1543210 (2) The 7th digit of the significant digits being stored at +1 and +2 is rounded off to make a 6-digit number. . 2 3456789 1234570 123456789 Rounded off...
Page 620 EMOD(P) Program Example (1) The following program breaks down the 32-bit floating decimal point type real number data stored at D0 and D1 into BCD according to the decimal fraction digits as designated by R10, and stores the results into the area starting from D100 when X0 is turned ON. [Ladder Mode] [List Mode] Step...
Page 621: From Bcd Format Data To Floating Decimal Point (Erexp(P))
EREXP(P) 7.11.21 From BCD format data to floating decimal point (EREXP(P)) EREXP(P) High Basic Process Redundant Universal LCPU performance Command EREXP EREXP Command EREXPP EREXPP : Head number of the devices where BCD type floating point format data is stored (BIN 16 bits) : Decimal fraction digits data (BIN 16 bits) : The device where the converted 32-bit floating point real number data will be stored (real number) Internal Devices...
Page 622 EREXP(P) Operation Error (1) In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and an error code is stored into SD0. • The format designated by was neither 0 nor 1. (Error code: 4100) •...
Page 623: Special Function Instructions
SIN(P) 7.12 Special function instructions 7.12.1 SIN operation on floating-point data (Single precision) (SIN(P)) SIN(P) Ver. High Basic Process Redundant Universal LCPU performance Basic model QCPU: The upper five digits of the serial No. are "04122" or larger. Command Command SINP SINP : Angle data of which the SIN (sine) value is obtained or head number of the devices where the angle data is...
Page 624 SIN(P) Operation Error (1) In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and an error code is stored into SD0. • The value of the specified device is (For the Basic model QCPU, High Performance model QCPU, Process CPU, Redundant CPU) (Error code: 4100) *2: There are CPU modules that will not result in an operation error if...
Page 625: Sin Operation On Floating-Point Data (Double Precision) (Sind(P))
SIND(P) 7.12.2 SIN operation on floating-point data (Double precision) (SIND(P)) SIND(P) High Basic Process Redundant Universal LCPU performance Command SIND SIND Command SINDP SINDP : Angle data of which the SIN (sine) value is obtained or head number of the devices where the angle data is stored (real number) : Head number of the devices where the operation result will be stored (real number) Internal Devices...
Page 626 SIND(P) Program Example (1) The following program conducts a SIN operation on the angles stored in the four BCD digits from X20 to X2F and stores the results at D0 to D3 as 64-bit floating decimal point type real numbers. [Ladder Mode] Inputs an angle used for SIN operation (...
Page 627: Cos Operation On Floating-Point Data (Single Precision) (Cos(P))
COS(P) 7.12.3 COS operation on floating-point data (Single precision) (COS(P)) COS(P) Ver. High Basic Process Redundant Universal LCPU performance Basic model QCPU: The upper five digits of the serial No. are "04122" or larger. Command Command COS P COSP : Angle data of which the COS (cosine) value is obtained or head number of the devices where the angle data is stored (real number) : Head number of the devices where the operation result will be stored (real number) Internal Devices...
Page 628 COS(P) Operation Error (1) In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and an error code is stored into SD0. • The value of the specified device is (For the Basic model QCPU, High Performance model QCPU, Process CPU, Redundant CPU) (Error code: 4100) *2: There are CPU modules that will not result in an operation error if...
Page 629: Cos Operation On Floating-Point Data (Double Precision) (Cosd(P))
COSD(P) 7.12.4 COS operation on floating-point data (Double precision) (COSD(P)) COSD(P) High Basic Process Redundant Universal LCPU performance Command COSD COSD Command COSDP COSDP : Angle data of which the COS (cosine) value is obtained or head number of the devices where the angle data is stored (real number) : Head number of the devices where the operation result will be stored (real number) Internal Devices...
Page 630 COSD(P) Program Example (1) The following program performs a COS operation on the angle data designated by the 4 BCD digits from X20 to X2F, and stores results as 64-bit floating decimal point type real numbers at D0 to D3. [Ladder Mode] Inputs an angle used for COS operation (...
Page 631: Tan Operation On Floating-Point Data (Single Precision) (Tan(P))
TAN(P) 7.12.5 TAN operation on floating-point data (Single precision) (TAN(P)) TAN(P) Ver. High Basic Process Redundant Universal LCPU performance Basic model QCPU: The upper five digits of the serial No. are "04122" or larger. Command Command TANP TANP : Angle data of which the TAN (tangent) value is obtained or head number of the devices where the angle data is stored (real number) : Head number of the devices where the operation result will be stored (real number) Internal Devices...
Page 632 TAN(P) Operation Error (1) In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and an error code is stored into SD0. • Operation results are outside the range shown below: -126 0, 2 |operation result| (For the Basic model QCPU, High Performance model QCPU, Process CPU, Redundant CPU)
Page 633: Tan Operation On Floating-Point Data (Double Precision) (Tand(P))
TAND(P) 7.12.6 TAN operation on floating-point data (Double precision) (TAND(P)) TAND(P) High Basic Process Redundant Universal LCPU performance Command TAND TAND Command TANDP TANDP : Angle data of which the TAN (tangent) value is obtained or head number of the devices where the angle data is stored (real number) : Head number of the devices where the operation result will be stored (real number) Internal Devices...
Page 634 TAND(P) Operation Error (1) In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and an error code is stored into SD0. • The value of the specified device is not in the following range: (Error code: 4140) -1022 1024...
Page 635 ASIN(P) 7.12.7 operation on floating point data (Single precision) (ASIN(P)) ASIN(P) High Basic Process Redundant Universal LCPU performance Command ASIN ASIN Command ASINP ASINP : SIN value of which the SIN (inverse sine) value is obtained or head number of the devices where the SIN value is stored (real number) : Head number of the devices where the operation result will be stored (real number) Internal Devices...
Page 636 ASIN(P) Operation Error (1) In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and an error code is stored into SD0. • The value designated by is outside the range of from 1.0 to 1.0. (Error code: 4100) •...
Page 637 ASIN(P) Program Example (1) The following program seeks the inverse sine of the 32-bit floating decimal point real number at D0 and D1, and outputs the angle to the 4 BCD digits at Y40 to Y4F. [Ladder Mode] Calculates an angle (radian value) by SIN operation ( Converts the radian value...
Page 638 ASIND(P) 7.12.8 operation on floating-point data (Double precision) (ASIND(P)) ASIND(P) High Basic Process Redundant Universal LCPU performance Command ASIND ASIND Command ASINDP ASINDP : SIN value of which the SIN (inverse sine) value is obtained or head number of the devices where the SIN value is stored (real number) : Head number of the devices where the operation result will be stored (real number) Internal Devices...
Page 639 ASIND(P) Operation Error (1) In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and an error code is stored into SD0. • The value of the specified device is not in the following range: (Error code: 4140) -1022 1024...
Page 640 ACOS(P) 7.12.9 operation on floating-point data (Single precision) (ACOS(P)) ACOS(P) High Basic Process Redundant Universal LCPU performance Command ACOS ACOS Command ACOSP ACOSP : COS value of which the COS (inverse cosine) value is obtained or head number of the devices where the COS value is stored (real number) : Head number of the devices where the operation result will be stored (real number) Internal Devices...
Page 641 ACOS(P) Operation Error (1) In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and an error code is stored into SD0. • The value designated by is outside the range of from 1.0 to 1.0. (Error code: 4100) •...
Page 642 ACOSD(P) 7.12.10 operation on floating-point data (Double precision) (ACOSD(P)) ACOSD(P) High Basic Process Redundant Universal LCPU performance Command ACOSD ACOSD Command ACOSDP ACOSDP : COS value of which the COS (inverse cosine) value is obtained or head number of the devices where the COS value is stored (real number) : Head number of the devices where the operation result will be stored (real number) Internal Devices...
Page 643 ACOSD(P) Operation Error (1) In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and an error code is stored into SD0. • The value of the specified device is not in the following range: (Error code: 4140) -1022 1024...
Page 644 ATAN(P) 7.12.11 operation on floating-point data (Single precision) (ATAN(P)) ATAN(P) High Basic Process Redundant Universal LCPU performance Command ATAN ATAN Command ATANP ATANP : TAN value of which the TAN (inverse tangent) value is obtained or head number of the devices where the TAN value is stored (real number) : Head number of the devices where the operation result will be stored (real number) Internal Devices...
Page 645 ATAN(P) Operation Error (1) In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and an error code is stored into SD0. • The contents of the designated device or the result of the addition are not "0", or not within the following range(For the Universal model QCPU, LCPU): (Error code: 4140) -126...
Page 646 ATAND(P) 7.12.12 operation on floating-point data (Double precision) (ATAND(P)) ATAND(P) High Basic Process Redundant Universal LCPU performance Command ATAND ATAND Command ATANDP ATANDP : TAN value of which the TAN (inverse tangent) value is obtained or head number of the devices where the TAN value is stored (real number) : Head number of the devices where the operation result will be stored (real number) Internal Devices...
Page 647 ATAND(P) Program Example (1) The following program seeks the inverse tangent of the 64-bit floating decimal point real number at D0 to D3, and outputs the angle to the 4 BCD digits at Y40 to Y4F. [Ladder Mode] Calculates an angle (radian value) by TAN operation ( Converts the radian value into an angle (...
Page 648: Conversion From Floating-Point Angle To Radian (Single Precision) (Rad(P))
RAD(P) 7.12.13 Conversion from floating-point angle to radian (Single precision) (RAD(P)) RAD(P) Ver. High Basic Process Redundant Universal LCPU performance Basic model QCPU: The upper five digits of the serial No. are "04122" or larger. Command Command RADP RADP : Angle to be converted to radian units or head number of the devices where the angle is stored (real number) : Head number of the devices where the value converted in radian units will be stored (real number) Internal Devices Setting...
Page 649 RAD(P) Operation Error (1) In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and an error code is stored into SD0. • The contents of the designated device or the result of the addition are not "0", or not within the following range(For the Universal model QCPU, LCPU): (Error code: 4140) -126...
Page 650: Conversion From Floating-Point Angle To Radian (Double Precision) (Radd(P))
RADD(P) 7.12.14 Conversion from floating-point angle to radian (Double precision) (RADD(P)) RADD(P) High Basic Process Redundant Universal LCPU performance Command RADD RADD Command RADDP RADDP : Angle to be converted to radian units or head number of the devices where the angle is stored (real number) : Head number of the devices where the value converted in radian units will be stored (real number) Internal Devices Setting...
Page 651 RADD(P) Program Example (1) The following program converts the angle set by the 4 BCD digits at X20 to X2F to radians, and stores results as 64-bit floating decimal point type real number at D20 to D23. [Ladder Mode] Inputs an angle to be converted into a radian value ( Converts the input angle into a 64-bit floating-point real number (...
Page 652: Conversion From Floating-Point Radian To Angle (Single Precision) (Deg(P))
DEG(P) 7.12.15 Conversion from floating-point radian to angle (Single precision) (DEG(P)) DEG(P) Ver. High Basic Process Redundant Universal LCPU performance Basic model QCPU: The upper five digits of the serial No. are "04122" or larger. Command Command DEGP DEGP : Radian angle to be converted to degrees or head number of the devices where the radian angle is stored (real number) : Head number of the devices where the value converted in degrees will be stored (real number) Internal Devices...
Page 653 DEG(P) Operation Error (1) In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and an error code is stored into SD0. • The value of the specified device is (For the Basic model QCPU, High Performance model QCPU, Process CPU, Redundant CPU) (Error code: 4100) *2: There are CPU modules that will not result in an operation error if...
Page 654: Conversion From Floating-Point Radian To Angle (Double Precision) (Degd(P))
DEGD(P) 7.12.16 Conversion from floating-point radian to angle (Double precision) (DEGD(P)) DEGD(P) High Basic Process Redundant Universal LCPU performance Command DEGD DEGD Command DEGDP DEGDP : Radian angle to be converted to degrees or head number of the devices where the radian angle is stored (real number) : Head number of the devices where the value converted in degrees will be stored (real number) Internal Devices...
Page 655 DEGD(P) Program Example (1) The following program converts the radian value set with 64-bit floating decimal point type real number at D20 to D23 to angles, and stores the result as a BCD value at Y40 to Y4F. [Ladder Mode] Converts a radian value into an angle ( Converts the angle in 64-bit floating-point real number into an integer (...
Page 656: Exponentiation Operation On Floating-Point Data (Single Precision) (Pow(P))
POW(P) 7.12.17 Exponentiation operation on floating-point data (Single precision) (POW(P)) POW(P) Ver. High Basic Process Redundant Universal LCPU performance QnU(D)(H)CPU: The serial number (first five digits) is "10102" or later. QnUDE(H)CPU: The serial number (first five digits) is "10102" or later. Command Command POWP...
Page 657 POW(P) Operation Error (1) In any of the following cases, an operation error occurs, the error flag (SM0) turns on, and an error code is stored into SD0. • The values specified by are out of the ranges shown below. (Error code: 4140) -126 0, 2...
Page 658: Exponentiation Operation On Floating-Point Data (Single Precision) (Powd(P))
POWD(P) 7.12.18 Exponentiation operation on floating-point data (Single precision) (POWD(P)) POWD(P) Ver. High Basic Process Redundant Universal LCPU performance QnU(D)(H)CPU: The serial number (first five digits) is "10102" or later. QnUDE(H)CPU: The serial number (first five digits) is "10102" or later. Command POWD POWD...
Page 659 POWD(P) Operation Error (1) In any of the following cases, an operation error occurs, the error flag (SM0) turns on, and an error code is stored into SD0. • The values specified by are out of the range shown below. (Error code: 4140) -1022 1024...
Page 660: Square Root Operation For Floating-Point Data (Single Precision) (Sqr(P))
SQR(P) 7.12.19 Square root operation for floating-point data (Single precision) (SQR(P)) SQR(P) Ver. High Basic Process Redundant Universal LCPU performance Basic model QCPU: The upper five digits of the serial No. are "04122" or larger. Command Command SQRP SQRP : Data of which the square root is obtained or head number of the devices where the data is stored (real number) : Head number of the devices where the operation result will be stored (real number) Internal Devices...
Page 661 SQR(P) Operation Error (1) In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and an error code is stored into SD0. • The value designated by is a negative number. (Error code: 4100) •...
Page 662: Square Root Operation For Floating-Point Data (Double Precision) (Sqrd(P))
SQRD(P) 7.12.20 Square root operation for floating-point data (Double precision) (SQRD(P)) SQRD(P) High Basic Process Redundant Universal LCPU performance Command SQRD SQRD Command SQRDP SQRDP : Data of which the square root is obtained or head number of the devices where the data is stored (real number) : Head number of the devices where the operation result will be stored (real number) Internal Devices...
Page 663 SQRD(P) Program Example (1) The following program seeks the square root of the value set by the 4 BCD digits from X20 to X2F, and stores the result as a 64-bit floating decimal point type real number at D0 to D3. [Ladder Mode] Inputs data used for square root operation (...
Page 664: Exponent Operation On Floating-Point Data (Single Precision) (Exp(P))
EXP(P) 7.12.21 Exponent operation on floating-point data (Single precision) (EXP(P)) EXP(P) Ver. High Basic Process Redundant Universal LCPU performance Basic model QCPU: The upper five digits of the serial No. are "04122" or larger. Command Command EXPP EXPP : Data of which the exponential value is obtained or head number of the devices where the data is stored (real number) : Head number of the devices where the operation result will be stored (real number) Internal Devices...
Page 665 EXP(P) Operation Error (1) In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and an error code is stored into SD0. • Operation results are outside the range shown below: (Error code: 4100) -126 | operation result | (For a High Performance model QCPU)
Page 666 EXP(P) Program Example (1) The following program performs an exponent operation on the value set by the 2 BCD digits at X20 to X27, and stores the results as a 32-bit floating decimal point real number at D0 and [Ladder Mode] Inputs the data used for exponent operation ( Checks the range of the...
Page 667: Exponent Operation On Floating-Point Data (Double Precision) (Expd(P))
EXPD(P) 7.12.22 Exponent operation on floating-point data (Double precision) (EXPD(P)) EXPD(P) High Basic Process Redundant Universal LCPU performance Command EXPD EXPD Command EXPDP EXPDP : Data of which the exponential value is obtained or head number of the devices where the data is stored (real number) : Head number of the devices where the operation result will be stored (real number) Internal Devices...
Page 668 EXPD(P) Program Example (1) The following program performs an exponent operation on the value set by the 2 BCD digits at X20 to X31, and stores the results as a 64-bit floating decimal point real number at D0 to [Ladder Mode] Inputs data used for exponent operation ( Checks the range of the value used...
Page 669: Natural Logarithm Operation On Floating-Point Data (Single Precision) (Log(P))
LOG(P) 7.12.23 Natural logarithm operation on floating-point data (Single precision) (LOG(P)) LOG(P) Ver. High Basic Process Redundant Universal LCPU performance Basic model QCPU: The upper five digits of the serial No. are "04122" or larger. Command Command LOGP LOGP : Data of which the natural logarithm is obtained or head number of the devices where the data is stored (real number) : Head number of the devices where the operation result will be stored (real number) Internal Devices...
Page 670 LOG(P) Operation Error (1) In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and an error code is stored into SD0. • The value designated by is negative. (Error code: 4100) • The value designated by is 0.
Page 671: Natural Logarithm Operation On Floating-Point Data (Double Precision Logd(P))
LOGD(P) 7.12.24 Natural logarithm operation on floating-point data (Double precision) (LOGD(P)) LOGD(P) High Basic Process Redundant Universal LCPU performance Command LOGD LOGD Command LOGDP LOGDP : Data of which the natural logarithm is obtained or head number of the devices where the data is stored (real number) : Head number of the devices where the operation result will be stored (real number) Internal Devices...
Page 672 LOGD(P) Program Example (1) The following program seeks the natural logarithm of the value "10" set by D50, and stores the result at D30 to D33. [Ladder Mode] Sets data used for natural logarithm operation ( Converts the operation data into a 64-bit floating-point real number ( Executes natural logarithm operation ( [List Mode]...
Page 673: Common Logarithm Operation On Floating-Point Data (Single Precision Log10(P))
LOG10(P) 7.12.25 Common logarithm operation on floating-point data (Single precision) (LOG10(P)) LOG10(P) Ver. High Basic Process Redundant Universal LCPU performance QnU(D)(H)CPU: The serial number (first five digits) is "10102" or later. QnUDE(H)CPU: The serial number (first five digits) is "10102" or later. Command LOG10 LOG10...
Page 674 LOG10(P) Operation Error (1) In any of the following cases, an operation error occurs, the error flag (SM0) turns on, and an error code is stored into SD0. • The value specified by is negative. (Error code: 4100) • The value specified by is 0.
Page 675: Common Logarithm Operation On Floating-Point Data (Double Precision Log10D(P))
LOG10D(P) 7.12.26 Common logarithm operation on floating-point data (Double precision) (LOG10D(P)) LOG10D(P) Ver. High Basic Process Redundant Universal LCPU performance QnU(D)(H)CPU: The serial number (first five digits) is "10102" or later. QnUDE(H)CPU: The serial number (first five digits) is "10102" or later. Command LOG10D LOG10D...
Page 676 LOG10D(P) Operation Error (1) In any of the following cases, an operation error occurs, the error flag (SM0) turns on, and an error code is stored into SD0. • The value specified by is negative. (Error code: 4100) • The value specified by is 0.
Page 677: Random Number Generation And Series Updates (Rnd(P),Srnd(P))
RND(P),SRND(P) 7.12.27 Random number generation and series updates (RND(P),SRND(P)) RND(P),SRND(P) Ver. High Basic Process Redundant Universal LCPU performance Basic model QCPU: The upper five digits of the serial No. are "04122" or larger. Command Command RNDP RNDP Command SRND SRND Command SRNDP SRNDP...
Page 678 RND(P),SRND(P) Operation Error (1) There are no operation errors associated with the RND(P) or SRND(P) instructions. Program Example (1) The following program stores random number at D100 when X10 is turned ON. [Ladder Mode] [List Mode] Step Instruction Device (2) The following program updates a random number series according to the contents of D0 when X10 is turned ON.
Page 679: Bcd 4-Digit And 8-Digit Square Roots (Bsqr(P),Bdsqr(P))
BSQR(P),BDSQR(P) 7.12.28 BCD 4-digit and 8-digit square roots (BSQR(P),BDSQR(P)) BSQR(P),BDSQR(P) High Basic Process Redundant Universal LCPU performance BSQR/BDSQR Command BSQR,BDSQR Command BSQRP,BDSQRP : Data of which the square root is obtained or the number of the device where the data is stored (BSQR(P): BCD 4 digits, BDSQR(P): BCD 8 digits) : Head number of the devices where the square root calculation result will be stored (BCD 4 digits) Internal Devices...
Page 680 BSQR(P),BDSQR(P) BDSQR (1) Calculates the square root of the values designated by +1 and stores the results at the device designated by Integer part Decimal fraction part 2-word data (2) BCD value of a maximum of 8 digits (0 to 99999999) can be designated by (3) The operation results of +1 are stored as their respective BCD values of between 0 and 9999.
Page 681 BSQR(P),BDSQR(P) (2) The following program calculates the square root of BCD value 74625813 and outputs the integer part of the result to the 4 BCD digits at Y50 to Y5F, and the decimal fraction part to the 4 BCD digits from Y40 to Y4F. [Ladder Mode] Sets the data (BCD value) used for square root operation (...
Page 682: Bcd Type Sin Operation (Bsin(P))
BSIN(P) 7.12.29 BCD type SIN operation (BSIN(P)) BSIN(P) High Basic Process Redundant Universal LCPU performance Command BSIN BSIN Command BSINP BSINP : Data of which the SIN (sine) value is obtained or the number of the device where the data is stored (BCD 4 digits) : Head number of the devices where the operation result will be stored (BCD 4 digits) Internal Devices...
Page 683 BSIN(P) Program Example (1) The program example below calculates the SIN of 3-digit BCD data designated by X20 to X2B, and outputs a 1-digit BCD part to the integer part from Y50 to Y53, and a 4-digit BCD fraction part from Y40 to Y4F. Y60 is turned ON if the results of the operation are negative.
Page 684: Bcd Type Cos Operations (Bcos(P))
BCOS(P) 7.12.30 BCD type COS operations (BCOS(P)) BCOS(P) High Basic Process Redundant Universal LCPU performance Command BCOS BCOS Command BCOSP BCOSP : Data of which the COS (cosine) value is obtained or head number of the devices where the data is stored (BCD 4 digits) : Head number of the devices where the operation result will be stored (BCD 4 digits) Internal Devices...
Page 685 BCOS(P) Program Example (1) The following program calculates the cosine of the data designated by the 3 BCD digits from X20 to X2B and outputs the integer part of the result to 1 BCD digit from Y50 to Y53, and the decimal fraction part of the result to the 4 BCD digits from Y40 to Y4F.
Page 686: Bcd Type Tan Operation (Btan(P))
BTAN(P) 7.12.31 BCD type TAN operation (BTAN(P)) BTAN(P) High Basic Process Redundant Universal LCPU performance Command BTAN BTAN Command BTANP BTANP : Data of which the TAN (tangent) value is obtained or head number of the devices where the data is stored (BCD 4 digits) : Head number of the devices where the operation result will be stored (BCD 4 digits) Internal Devices...
Page 687 BTAN(P) Program Example (1) The following program calculates the tangent of the data stored in the 3 BCD digits from X20 to X2B, and stores the integer part of the results in the 4 BCD digits from Y50 to Y53, and the decimal fraction part in the 4 BCD digits from Y40 to Y4F.
Page 688 BASIN(P) 7.12.32 BCD type SIN operations (BASIN(P)) BASIN(P) High Basic Process Redundant Universal LCPU performance Command BASIN BASIN Command BASINP BASINP : Number of the device where data of which the SIN (inverse sine) value is obtained is stored (BCD 4 digits) : Head number of the devices where the operation result will be stored (BCD 4 digits) Internal Devices Setting...
Page 689 BASIN(P) Program Example (1) The following program performs a SIN operation on the sign (positive when X0 is OFF, and negative when X0 is ON), the BCD 1-digit integer part from X30 to X33 and the BCD 4-digit decimal fraction part from X20 to X2F, and outputs the calculated angle in 4 BCD digits from Y40 to Y4F.
Page 690 BACOS(P) 7.12.33 BCD type COS operation (BACOS(P)) BACOS(P) High Basic Process Redundant Universal LCPU performance Command BACOS BACOS Command BACOSP BACOSP : Number of the device where data of which the COS-1 (inverse cosine) value is obtained is stored (BCD 4 digits) : Head number of the devices where the operation result will be stored (BCD 4 digits) Internal Devices Setting...
Page 691 BACOS(P) Program Example (1) The following program performs a COS operation on the sign (positive when X0 is OFF, and negative when X0 is ON), the BCD 1-digit integer part from X30 to X33 and the BCD 4-digit decimal fraction part from X20 to X2F, and outputs the calculated angle in 4 BCD digits from Y40 to Y4F.
Page 692 BATAN(P) 7.12.34 BCD type TAN operations (BATAN(P)) BATAN(P) High Basic Process Redundant Universal LCPU performance Command BATAN BATAN Command BATANP BATANP : Number of the device where data of which the TAN-1 (inverse tangent) value is obtained is stored (BCD 4 digits) : Head number of the devices where the operation result will be stored (BCD 4 digits) Internal Devices Setting...
Page 693 BATAN(P) Program Example (1) The following program performs a TAN-1 operation on the sign (positive when X0 is OFF, and negative when X0 is ON), the BCD 4-digit integer part from X20 to X2F and the BCD 4-digit decimal fraction part from X30 to X3F, and outputs the calculated angle in 4 BCD digits from Y40 to Y4F.
Page 694: Data Control Instructions
LIMIT(P),DLIMIT(P) 7.13 Data Control Instructions 7.13.1 Upper and lower limit controls for BIN 16-bit and BIN 32-bit data (LIMIT(P),DLIMIT(P)) LIMIT(P),DLIMIT(P) High Basic Process Redundant Universal LCPU performance indicates an instruction symbol of LIMIT/DLIMIT. Command LIMIT, DLIMIT Command LIMITP, DLIMITP : Lower limit value (minimum output threshold value) (BIN 16/32 bits) : Upper limit value (maximum output threshold value) (BIN 16/32 bits) : Input value to be controlled by the upper and lower limit control (BIN 16/32 bits) : Head number of the devices where the output value controlled by the upper and lower limit control will be...
Page 695 LIMIT(P),DLIMIT(P) (3) When control based only on upper limit values is performed, the lower limit value designated is set at " 32678". (4) When control based only on lower limit values is performed, the upper limit value designated is set at "32767". DLIMIT (1) The function controls the output value to be stored at the device designated by ( +1) by...
Page 696 LIMIT(P),DLIMIT(P) Program Example (1) The following program conducts limit controls from 500 to 5000 on the data set as BCD values from X20 to X2F, and stores the result at D1 when X0 is turned ON. [Ladder Mode] [List Mode] Step Instruction Device...
Page 697: Bin 16-Bit And 32-Bit Dead Band Controls (Band(P),Dband(P))
BAND(P),DBAND(P) 7.13.2 BIN 16-bit and 32-bit dead band controls (BAND(P),DBAND(P)) BAND(P),DBAND(P) High Basic Process Redundant Universal LCPU performance indicates an instruction symbol of BAND/DBAND. Command BAND,DBAND Command BANDP,DBANDP : Lower limit value of dead band (no output band) (BIN 16/32 bits) : Upper limit value of dead band (no output band) (BIN 16/32 bits) : Input value to be controlled by a dead band control (BIN 16/32 bits) : Head number of the devices where the output value controlled by the dead band control will be stored...
Page 698 BAND(P),DBAND(P) (3) The output value stored at is a signed 16-bit BIN value. Therefore, if the operation results exceed the range of from 32768 to 32767, the following will take place: Dead band lower limit value ....10 When : Input value ..........
Page 699 BAND(P),DBAND(P) Program Example (1) The following program performs the dead band control by applying the lower and upper limits of 0 and 1000 for the data set in BCD at X20 to X2F and stores the result of control at D1 when X0 is turned ON.
Page 700: Zone Control For Bin 16-Bit And Bin 32-Bit Data (Zone(P),Dzone(P))
ZONE(P),DZONE(P) 7.13.3 Zone control for BIN 16-bit and BIN 32-bit data (ZONE(P),DZONE(P)) ZONE(P),DZONE(P) High Basic Process Redundant Universal LCPU performance indicates an instruction symbol of ZONE/DZONE. Command ZONE,DZONE Command ZONEP,DZONEP : Negative bias value to be added to an input value (BIN 16/32 bits) : Positive bias value to be added to an input value (BIN 16/32 bits) : Input value used for a zone control (BIN 16/32 bits) : Head number of the devices where the output value controlled by the zone control will be stored...
Page 701 ZONE(P),DZONE(P) (2) The values that can be designated by , and are in the range of from 32768 to 32767. (3) The output value stored at is a signed 16-bit BIN value. Therefore, if the operation results exceed the range of 32768 to 32767, the following will take place: Negative bias value ......
Page 702 ZONE(P),DZONE(P) Program Example (1) The following program performs zone control by applying negative and positive bias values 100 to 100 for the data set at D0 and stores the result of control at D1 when X0 is turned [Ladder Mode] [List Mode] Step Instruction...
Page 703: Scaling (Point-By-Point Coordinate Data) (Scl(P),Dscl(P))
(SCL(P),DSCL(P)) 7.13.4 Scaling (Point-by-point coordinate data) (SCL(P),DSCL(P)) (SCL(P),DSCL(P)) Ver. High Basic Process Redundant Universal LCPU performance QnU(D)(H)CPU: The serial number (first five digits) is "10102" or later. QnUDE(H)CPU: The serial number (first five digits) is "10102" or later. SCL/DSCL indicates an instruction symbol of Command SCL/DSCL Command...
Page 704 (SCL(P),DSCL(P)) (5) If some specified points have same X coordinates, the Y coordinate data of the highest point number will be output. (6) Specify the number of coordinate points of scaling conversion data from 1 to 32767. DSCL(P) (1) This instruction executes scaling for the scaling conversion data (32-bit data units) specified with the input value specified , and then stores the operation result into the devices specified by...
Page 705 (SCL(P),DSCL(P)) (1) There are two searching methods that depend on whether SM750 is on or off. SM750 Searching method Range of number of searches Sequential search Number of times 32767 Binary search Number of times (2) When the scaling conversion data are set in ascending order, the searching methods change from one to the other depending on the SM750 status.
Page 706 (SCL(P),DSCL(P)) Operation Error (1) In any of the following cases, an operation error occurs, the error flag (SM0) turns on, and an error code is stored into SD0. • The X coordinates of the scaling conversion data positioned before the point specified by are not set in ascending order.
Page 707: Scaling (Point-By-Point Coordinate Data) (Scl2(P),Dscl2(P))
SCL2,DSCL2 7.13.5 Scaling (Point-by-point coordinate data) (SCL2(P),DSCL2(P)) SCL2,DSCL2 Ver. High Basic Process Redundant Universal LCPU performance QnU(D)(H)CPU: The serial number (first five digits) is "10102" or later. QnUDE(H)CPU: The serial number (first five digits) is "10102" or later. SCL2/DSCL2 indicates an instruction symbol of Command SCL2/DSCL2 Command...
Page 708 SCL2,DSCL2 (4) Set the input value within the range of the scaling conversion data (within the range of devices). (5) If some specified points have same X coordinates, the Y coordinate data of the highest point number will be output. DSCL2(P) (1) This instruction executes scaling for the scaling conversion data (32-bit data units) specified with the input value specified...
Page 709 SCL2,DSCL2 Operation Error (1) In any of the following cases, an operation error occurs, the error flag (SM0) turns on, and an error code is stored into SD0. • The X coordinates are not set in ascending order. (Error code: 4100) •...
Page 710: File Register Switching Instructions
RSET(P) 7.14 File register switching instructions 7.14.1 Switching file register numbers (RSET(P)) RSET(P) Ver. High Basic Process Redundant Universal LCPU performance Universal model QCPU: Other than Q00UJCPU Command RSET RSET Command RSETP RSETP : Block number data used to change the block number or the number of the device where the block number data is stored (BIN 16 bits) Internal Devices Setting...
Page 711 RSET(P) Operation Error (1) In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and an error code is stored into SD0. • The block number designated by does not exist. (Error code: 4100) •...
Page 712: Setting Files For File Register Use (Qdrset(P))
QDRSET(P) 7.14.2 Setting files for file register use (QDRSET(P)) QDRSET(P) Ver. High Basic Process Redundant Universal LCPU performance Universal model QCPU: Other than Q00UJCPU Command QDRSET QDRSET Command QDRSETP QDRSETP : Character string data of the drive No./file name in which the file register is set, or head number of the devices where the character string data is stored (character string) Internal Devices Setting...
Page 713 QDRSET(P) (2) Drive number can be designated from 1 to 4. (The drive number cannot be designated as drive 0 (program memory/internal memory).) Note that available drives vary depending on the CPU module used. Refer to the manual of the CPU module and check the drives that can be specified. (3) It is not necessary to designate the extension (.QDR) with the file name.
Page 714 QDRSET(P) Program Example (1) The following program compares R0 of ABC in block No. 1 and R0 of DEF in block No. 1. [Ladder Mode] [List Mode] Step Instruction Device [Operation] Block No. 0 Block No. 1 -3216 5001 9330 -1762 -7981 -3216...
Page 715: File Setting For Comments (Qcdset(P))
QCDSET(P) 7.14.3 File setting for comments (QCDSET(P)) QCDSET(P) High Basic Process Redundant Universal LCPU performance Command QCDSET QCDSET Command QCDSETP QCDSETP : Character string data of the drive No./file name in which the comment file is set, or head number of the devices where the character string data is stored (character string) Internal Devices Setting...
Page 716 QCDSET(P) (4) A file name setting can be deleted by designating the NULL character (00 ) for the file name. (5) File names designated with this instruction will be given priority even if a drive number and file name have been designated in the parameters. If the file name is changed with the QCDSET instruction, the file name returns to the name specified by the parameter when the CPU module is switched from STOP to RUN.
Page 717: Clock Instructions
DATERD(P) 7.15 Clock instructions 7.15.1 Reading clock data (DATERD(P)) DATERD(P) High Basic Process Redundant Universal LCPU performance Command DATERD DATERD Command DATERDP DATERDP : Head number of the devices where the read clock data will be stored (BIN 16 bits) Internal Devices Setting R, ZR...
Page 718 DATERD(P) Program Example (1) The following program outputs the following clock data as BCD values: Year ..Y70 to Y7F Month..Y68 to Y6F Day ...Y60 to Y67 Hour..Y58 to Y5F Minute..Y50 to Y57 Second ..Y48 to Y4F Week ..Y44 to Y47 [Ladder Mode] Outputs "Year"...
Page 719: Writing Clock Data (Datewr(P))
DATEWR(P) 7.15.2 Writing clock data (DATEWR(P)) DATEWR(P) High Basic Process Redundant Universal LCPU performance Command DATEWR DATEWR Command DATEWRP DATEWRP : Head number of the devices where clock data to be written into the clock device is stored (BIN 16 bits) Internal Devices Setting R, ZR...
Page 720 DATEWR(P) Operation Error (1) In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and an error code is stored into SD0. • Individual items of data have been set outside the setting range. (Error code: 4100) •...
Page 721: Clock Data Addition Operation (Date+(P))
DATE+(P) 7.15.3 Clock data addition operation (DATE+(P)) DATE+(P) High Basic Process Redundant Universal LCPU performance Command DATE+ DATE+ Command DATE+P DATE+P : Head number of the devices where the clock data to be adjusted by addition is stored (BIN 16 bits) : Head number of the devices where the time data to be added for adjustment is stored (BIN 16 bits) : Head number of the devices where the result of addition of clock (time) data will be stored (BIN 16 bits) Internal Devices...
Page 722 DATE+(P) Operation Error (1) In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and an error code is stored into SD0. • The data set by is outside the setting range. (Error code: 4100) •...
Page 723: Clock Data Subtraction Operation (Date-(P))
DATE-(P) 7.15.4 Clock data subtraction operation (DATE-(P)) DATE-(P) High Basic Process Redundant Universal LCPU performance Command DATE- DATE- Command DATE-P DATE-P : Head number of the devices where the clock time data to be adjusted by substraction is stored (BIN 16 bits) : Head number of the devices where time data to be subtracted for adjustment is stored (BIN 16 bits) : Head number of the devices where the result of subtraction of clock (time) data will be stored (BIN 16 bits) Internal Devices...
Page 724 DATE-(P) Operation Error (1) In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and an error code is stored into SD0. • The data set by is outside the setting range. (Error code: 4100) •...
Page 725: Time Data Conversion (From Hour/Minute/Second To Second) (Second(P))
SECOND(P) 7.15.5 Time data conversion (from Hour/Minute/Second to Second) (SECOND(P)) SECOND(P) High Basic Process Redundant Universal LCPU performance Command SECOND SECOND Command SECONDP SECONDP : Head number of the devices where the clock data before conversion is stored (BIN 16 bits) : Head number of the devices where the clock data after conversion will be stored (BIN 32 bits) Internal Devices Setting...
Page 726 SECOND(P) Program Example (1) The following program converts the clock time data read from the clock element into second when X20 is turned ON, and stores the result at D100 and D101. [Ladder Mode] [List Mode] Step Instruction Device [Operation] •...
Page 727: Time Data Conversion (From Second To Hour/Minute/Second) (Hour(P))
HOUR(P) 7.15.6 Time data conversion (from Second to Hour/Minute/Second) (HOUR(P)) HOUR(P) High Basic Process Redundant Universal LCPU performance Command HOUR HOUR Command HOURP HOURP : Head number of the devices where clock data before conversion is stored (BIN 32 bits) : Head number of the devices where the clock data after conversion will be stored (BIN 16 bits) Internal Devices Setting...
Page 728 HOUR(P) Program Example (1) The following program converts the seconds stored at D0 and D1 into an hour, minute, second format, and stores the result at devices starting from D100 when X20 is turned ON. [Ladder Mode] [List Mode] Step Instruction Device [Operation]...
Page 729: Date Comparison (Dt=,Dt<>,Dt>,Dt<=,Dt<,Dt>=)
(DT=,DT<>,DT>,DT<=,DT<,DT>=) 7.15.7 Date comparison (DT=,DT<>,DT>,DT<=,DT<,DT>=) (DT=,DT<>,DT>,DT<=,DT<,DT>=) Ver. High Basic Process Redundant Universal LCPU performance QnU(D)(H)CPU: The serial number (first five digits) is "10102" or later. QnUDE(H)CPU: The serial number (first five digits) is "10102" or later. DT=/DT<>/DT</DT<=/DT>/DT>= indicates an instruction symbol of Command Command : Head number of the devices where the data to be compared are stored (BIN 16 bits)
Page 730 (DT=,DT<>,DT>,DT<=,DT<,DT>=) When either corresponds to any of the following in comparing given or current date data with given date data, the operation error (error code: 4101) or a malfunction may occurs. • The range of the devices to be used for the index modification is specified over the range of the device specified by •...
Page 731 (DT=,DT<>,DT>,DT<=,DT<,DT>=) (c) The following table shows processing details of bits to be compared. n value for n value for comparison of comparison of Date to be Processing details specified date data specified date data compared with given date data with current date data 0001 8001 Comparison of days (...
Page 732 (DT=,DT<>,DT>,DT<=,DT<,DT>=) (a) The following figure shows the comparison example of dates. 2006/1/1 2007/1/1 2008/1/1 2009/1/1 (2006/9/22) (2007/6/23) (2008/8/8) The following table shows the conductive states resulting from performing the comparison operation of the dates A, B, and C shown above. Even if the objects to be compared are under the same condition, the comparison operation results vary depending on the objects selected.
Page 733 (DT=,DT<>,DT>,DT<=,DT<,DT>=) Operation Error (1) Any operation errors do not occur in DT=,DT<>,DT>,DT<=,DT<,DT>= instruction. Program Example (1) The following program compares the data stored in D0 with the data (year, month, and day) stored in D10, and makes Y33 be conductive status when the data stored in D0 meet the data stored in D10.
Page 734: Clock Comparison (Tm=,Tm<>,Tm>,Tm<=,Tm<,Tm>=)
(TM=,TM<>,TM>,TM<=,TM<,TM>=) 7.15.8 Clock comparison (TM=,TM<>,TM>,TM<=,TM<,TM>=) (TM=,TM<>,TM>,TM<=,TM<,TM>=) Ver. High Basic Process Redundant Universal LCPU performance QnU(D)(H)CPU: The serial number (first five digits) is "10102" or later. QnUDE(H)CPU: The serial number (first five digits) is "10102" or later. (TM=,TM<>,TM>,TM<=,TM<,TM>=) DT＝/DT＜＞/DT＜/DT＜＝/DT＞/DT＞＝ indicates an instruction symbol of Command Command : Head number of the devices where the data to be compared are stored (BIN 16 bits)
Page 735 (TM=,TM<>,TM>,TM<=,TM<,TM>=) (b) Comparison of current time data • This instruction treats the clock data specified by and the current time data as a normally open contact, and compares the data in accordance with the value of n. • This instruction treats the clock data specified by as dummy data and ignores the data.
Page 736 (TM=,TM<>,TM>,TM<=,TM<,TM>=) (c) The following table shows processing details of bits to be compared. n value for n value for comparison of comparison of Time to be Processing details pecified clock data with specified clock data with compared given clock data current time data 0001 8001...
Page 737 (TM=,TM<>,TM>,TM<=,TM<,TM>=) (a) The following figure shows the comparison example of time. 0 Midnight 6:00 N00n 18:00 0 Midnight 4:50:55 14:08:58 22:47:05 The following table shows the conductive states resulting from performing the comparison operation of the dates A, B, and C shown above. Even if the objects to be compared are under the same condition, the comparison operation results vary depending on the objects selected.
Page 738 (TM=,TM<>,TM>,TM<=,TM<,TM>=) Program Example (1) The following program compares the data stored in D0 with the data (hour, minute, and second) stored in D10, and makes Y33 be conductive status when the data stored in D0 meet the data stored in D10. [Ladder Mode] [List Mode] Step...
Page 739: Expansion Clock Instructions
S(P).DATERD 7.16 Expansion Clock Instructions 7.16.1 Reading expansion clock data (S(P).DATERD) S(P).DATERD Ver. Ver. Ver. High Basic Process Redundant Universal LCPU performance High performance model QCPU, Process CPU, Redundant CPU: The serial number (first five digits) is "07032" or later. Command S.DATERD S.DATERD...
Page 740 S(P).DATERD Program Example (1) The following program outputs the following clock data as BCD values: Year ....Y70 to Y7F Month....Y68 to Y6F Day ..... Y60 to Y67 Hour....Y58 to Y5F Minute....Y50 to Y57 Second ....Y48 to Y4F Week ....
Page 741 S(P).DATERD Caution (1) This instruction reads clock data and stores those to a specified device even if a wrong clock data is set to the CPU module. (example: Feb. 30th) When setting clock data with the DATEWR instruction or GX Developer, make sure to set a correct data.
Page 742: Expansion Clock Data Addition Operation (S(P).Date+)
S(P).DATE+ 7.16.2 Expansion clock data addition operation (S(P).DATE+) S(P).DATE+ Ver. Ver. Ver. High Basic Process Redundant Universal LCPU performance High performance model QCPU, Process CPU, Redundant CPU: The serial number (first five digits) is "07032" or later. Command S.DATE+ S.DATE+ Command SP.DATE+ SP.DATE+...
Page 743 S(P).DATE+ (2) If the results of the addition of time exceed 24 hours, 24 hours will be subtracted from the sum to make the final operation result. For example, when the time 20:20:20:500 is added to 14:20:30:875, the result is not 34:40:51:375, but 10:40:51:375.
Page 744 S(P).DATE+ Program Example (1) The following program adds 1 hour to the clock data read from the clock element, and stores the results into the area starting from D100 when X20 is turned ON. [Ladder Mode] Reads out the clock element data to D0 or later.
Page 745: Expansion Clock Data Subtraction Operation (S(P).Date-)
S(P).DATE- 7.16.3 Expansion clock data subtraction operation (S(P).DATE-) S(P).DATE- Ver. Ver. Ver. High Basic Process Redundant Universal LCPU performance High performance model QCPU, Process CPU, Redundant CPU: The serial number (first five digits) is "07032" or later. Command S.DATE- S.DATE- Command SP.DATE- SP.DATE-...
Page 746 S(P).DATE- (2) If the subtraction results in a negative number, 24 will be added to the result to make a final operation result. For example, when the clock time 10:42:12:500 is subtracted from 4:50:32:875, the result is not 6:8:20:375, but 18:8:20:375. Hour: 4 Hour: 10 Hour: 18...
Page 747 S(P).DATE- Program Example (1) The following program subtracts the time data stored in the area starting from D10 from the clock data read from the clock element when X1C is turned ON, and stores the result into the area starting from D100. [Ladder Mode] Reads out the clock element data to D0 or later.
Page 748: Program Control Instructions
7.17 Program control instructions (1) Processing when the execution type is converted with the program control instruction is as follows. Executed Instruction Execution type before change PSCAN PSTOP POFF PLOW No change-remains Output turned OFF in Scan execution type scan type execution. next scan.
Page 749 (2) As program execution type conversions by PSCAN and PSTOP instructions occur at the END processing, such conversions are impossible during program execution. When different execution types have been set for the same program in the same scan, the execution type will be that specified by the execution switching command that was executed last.
Page 750: Program Standby Instruction (Pstop(P))
PSTOP(P) 7.17.1 Program standby instruction (PSTOP(P)) PSTOP(P) High Basic Process Redundant Universal LCPU performance Command PSTOP PSTOP Command PSTOPP PSTOPP : Character string for the name of the program file to be set in the stand-by status or head number of the devices where the character string data is stored (character string) Internal Devices Setting...
Page 751: Program Output Off Standby Instruction (Poff(P))
POFF(P) 7.17.2 Program output OFF standby instruction (POFF(P)) POFF(P) High Basic Process Redundant Universal LCPU performance Command POFF POFF Command POFFP POFFP : File name of the program to be set in the standby status by turning OFF the output, or the device where the file name is stored (character string) Internal Devices Setting...
Page 752 POFF(P) Remark 1. Non-execution processing is identical to the processing that is conducted when the condition contacts for the individual coil instructions are in the OFF state. The operation results for the individual coil instructions following non-execution processing will be as follows, regardless of the ON/OFF status of the individual contacts: OUT instruction ..
Page 753: Program Scan Execution Registration Instruction (Pscan(P))
PSCAN(P) 7.17.3 Program scan execution registration instruction (PSCAN(P)) PSCAN(P) High Basic Process Redundant Universal LCPU performance Command PSCAN PSCAN Command PSCANP PSCANP : File name of the program to be set as a scan execution type, or head number of the devices where the file name is stored (character string) Internal Devices Setting...
Page 754 PSCAN(P) Operation Error (1) In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and an error code is stored into SD0. • The program with the file name specified by does not exist. (Error code: 2410) •...
Page 755: Program Low Speed Execution Registration Instruction (Plow(P))
PLOW(P) 7.17.4 Program low speed execution registration instruction (PLOW(P)) PLOW(P) High Basic Process Redundant Universal LCPU performance Command PLOW PLOW Command PLOWP PLOWP : File name of the program to be set as a low speed execution type, or head number of the devices where the file name is stored (character string) Internal Devices Setting...
Page 756 PLOW(P) Program Example (1) The following program sets the program with file name ABC as low-speed execution type when X0 is turned ON. [Ladder Mode] [List Mode] Step Instruction Device 7-382...
Page 757: Program Execution Status Check Instruction (Pchk)
PCHK 7.17.5 Program execution status check instruction (PCHK) PCHK High Basic Process Redundant Universal LCPU performance LDPCHK File name PCHK Command ANDPCHK PCHK File name Command ORPCHK PCHK File name : File name of the program whose execution status will be checked (character string) Internal Devices Setting Constants...
Page 758 PCHK Remark Non-execution indicates that the program execution type is a stand-by type. Execution indicates that the program execution type is a scan execution type (including during output OFF (during non-execution processing)), low speed execution type or fixed scan execution type. The PCHK instruction is in conduction when the program of the specified file name (target program) is in execution, and the instruction is in non-conduction when the program is in non-execution.
Page 759: Other Instructions
WDT(P) 7.18 Other instructions 7.18.1 Resetting watchdog timer (WDT(P)) WDT(P) High Basic Process Redundant Universal LCPU performance Command Command WDTP WDTP Internal Devices Setting R, ZR Constants Other Data Word Word –– –– Function (1) Resets watchdog timer during the execution of a sequence program. (2) Used in cases where the scan time exceeds the value set for the watchdog timer due to prevailing conditions.
Page 760 WDT(P) Operation Error (1) There are no operation errors associated with the WDT(P) instruction. Program Example (1) The following program has a watchdog timer setting of 200 ms, when due to the execution conditions program execution requires 300 ms from step 0 to the END (FEND) instruction. [When WDT instruction is used] Program where Program where...
Page 761: Timing Pulse Generation (Duty)
DUTY 7.18.2 Timing pulse generation (DUTY) DUTY High Basic Process Redundant Universal LCPU performance Command DUTY DUTY n1 : Number of scans for ON (BIN 16 bits) n2 : Number of scans for OFF (BIN 16 bits) : User timing clock (SM420 to SM424, SM430 to M434) (bits) Internal Devices Setting Constants...
Page 762 DUTY Program Example (1) The following program turns SM420 ON for 1 scan, and OFF for 3 scans if X0 is ON. [Ladder Mode] [List Mode] Step Instruction Device [Operation] SM420 1 scan 3 scans 7-388...
Page 763: Time Check Instruction (Timchk)
TIMCHK 7.18.3 Time check instruction (TIMCHK) TIMCHK Ver. High Basic Process Redundant Universal LCPU performance Basic model QCPU: The upper five digits of the serial No. are "04122" or larger. command TIMCHK TIMCHK : Device where the measured current value will be stored (BIN 16 bits) : Device where the set value of measurement is stored (BIN 16 bits) : Device to be turned ON at time-out (bits) Internal Devices...
Page 764: Direct 1-Byte Read From File Register (Zrrdb(P))
ZRRDB(P) 7.18.4 Direct 1-byte read from file register (ZRRDB(P)) ZRRDB(P) High Basic Process Redundant Universal LCPU performance Command ZRRDB ZRRDB Command ZRRDBP ZRRDBP n : Serial byte number for the file register to be read (BIN 32 bits) : Number of the device where the read data will be stored (BIN 16 bits) Internal Devices Setting Constants...
Page 765 ZRRDB(P) (a) If the value of n has been designated as 23560, the data at the lower 8 bits of ZR11780 will be read. Read destination b8 b7 b8 b7 designation ZR11780 23560 Data is stored (b) If the value of n has been designated as 43257, the data at the upper 8 bits of ZR21628 will be read.
Page 766: File Register Direct 1-Byte Write (Zrwrb(P))
ZRWRB(P) 7.18.5 File register direct 1-byte write (ZRWRB(P)) ZRWRB(P) High Basic Process Redundant Universal LCPU performance Command ZRWRB ZRWRB Command ZRWRBP ZRWRBP n : Serial byte number for the file register to be written (BIN 32 bits) : Number of the device where the data to be written is stored (BIN 16 bits) Internal Devices Setting Constants...
Page 767 ZRWRB(P) If n 12340 is specified, the data will be written to the lower 8 bits of ZR11170. Write destination b8 b7 b8 b7 designation 12340 Ignored ZR11170 b8 b7 If n 43257 is specified, the data will be written to the upper 8 bits of ZR21628. Write destination designation b8 b7...
Page 768: Indirect Address Read Operations (Adrset(P))
ADRSET(P) 7.18.6 Indirect address read operations (ADRSET(P)) ADRSET(P) High Basic Process Redundant Universal LCPU performance Command ADRSET ADRSET Command ADRSETP ADRSETP : Number of the device whose indirect address is read out (Device name) : Number of the device where the indirect address of the device designated by will be stored (BIN 32 bits) Internal Devices Setting...
Page 769: Numerical Key Input From Keyboard (Key)
7.18.7 Numerical key input from keyboard (KEY) High Basic Process Redundant Universal LCPU performance Command : Head number of the devices (X) to which a numeral will be input (bits) n : Number of digits of the numeral to be input (BIN 16 bits) : Head number of the devices where the input numeral will be stored (BIN 16 bits) : Number of the bit device to turn ON at the completion of input (bits) Internal Devices...
Page 770 (2) Numerical input to input (X) designated by undergoes bit development at through +7 and is input as the ASCII code corresponding to the numbers. ASCII code which can be input is from 30 (0) to 39 (9), and from 41 (A) to 46 (F).
Page 771 (7) Fetching of the input data is completed when any of the inputs shown below has been made. At the completion, the bit device designated by is turned ON. • When the number of digits specified by n has been input •...
Page 772 Program Example (1) The following program fetches data of the 5 or fewer digits from the numerical key pad connected to X20 to X28, and stores it to the area starting from D0 when X0 is turned ON. [Ladder Mode] Clears the previous input data Sets the number of digits to be input Resets the data input completion fag...
Page 773: Batch Save Or Recovery Of Index Register (Zpush(P),Zpop(P))
ZPUSH(P),ZPOP(P) 7.18.8 Batch save or recovery of index register (ZPUSH(P),ZPOP(P)) ZPUSH(P),ZPOP(P) High Basic Process Redundant Universal LCPU performance indicates an instruction symbol of ZPUSH/ZPOP. Command ZPUSH, ZPOP Command ZPUSHP, ZPOPP : Head number of the devices to/from which contents of an index register are saved/recovered (BIN 16 bits) Internal Devices Setting R, ZR...
Page 774 ZPUSH(P),ZPOP(P) • When using a High Performance model QCPU/Process CPU/Redundant CPU Number of saves 1st nesting (18 words for the 1st nesting) Reserved by the system (2 words) 2nd nesting • When using Universal model QCPU/LCPU Number of saves 1st nesting (22 words for the 1st nesting) Reserved by the system (2 words)
Page 775: Reading Module Information (Unird(P))
UNIRD(P) 7.18.9 Reading Module Information (UNIRD(P)) UNIRD(P) High Basic Process Redundant Universal LCPU performance Command UNIRD UNIRD Command UNIRDP UNIRDP n1 : Value obtained by dividing the head I/O number of the reading module information source by 16 (0 to FFn) (BIN 16 bits) : Head number of the devices where the module information will be stored (device name) n2 : The number of points of read data (0 to 256) (BIN 16 bits)
Page 776 UNIRD(P) Remark The value of n1 is designated by the higher 3 digits of the head I/O number of the slot from which the module information is read, when it is expressed in 4 digits in hexadecimal notation. QCPU Power QY41 supply QX10 QX10...
Page 777 UNIRD(P) The details of the module information are described as follows: b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 Individual module information Meaning Item QCPU LCPU 000: 16 points 001: 32 points 010: 48 points 011: 64 points Number of I/O points...
Page 778 UNIRD(P) Operation Error (1) In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and an error code is stored into SD0. [High Performance model QCPU, Process CPU, Redundant CPU and Universal model QCPU, L26CPU-BT] •...
Page 779 UNIRD(P) Program Example (1) The following program stores the module information at I/O numbers 10 to 20 into the devices starting from D0 when X10 is turned ON. Card information Device X/Y0 module information X/Y10 module information X/Y20 module information X/YFE0 module information X/YFF0 module information [Ladder Mode]...
Page 780 UNIRD(P) (b) 32-point module for A series b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 For an A series module, all of these bits turn 0 because information is not stored. A series module Module is installed b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 All of these bits turn 0 because information is stored to "D0."...
Page 781 UNIRD(P) (6) L series 32-point intelligent function module b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 32-point module Intelligent function module (Empty) (Empty) (Empty) No module errors Module preparation complete (Empty) Module connected b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 All 0, because information is stored in "D0".
Page 782: Reading Module Model Name (Typerd(P))
7.18.10 Reading module model name (TYPERD(P)) Ver. High Basic Process Redundant Universal LCPU performance Universal model QCPU: The serial number (first five digits) is "11043" or later. Command TYPERD TYPERD Command TYPERDP TYPERDP Internal device Setting Constant R, ZR Others data K, H Word...
Page 783 (2) Specify the start I/O number of a module whose model name is to be read by "n" as follows: • Specify the value obtained by dividing the start I/O number of the target module by 16. Universal model QCPU Power QY41 QX10 QX10 QX10 QX10...
Page 784 • When the target module is a CPU module in multiple CPU systems Specify the value obtained by dividing the start I/O number of the target CPU module by Power Q20UDH Q20UDH Q20UDH QY41 QY41 supply QY10 QY10 module module 3E00 3E10 3E20...
Page 785 (b) When the model name has not been written to the target module (example: QX40) b8 b7 ○+0 Stores 1. Indicates that the character ○+1 string consists of module type and ○+2 the number of points is stored. Nine words are used. Stores the character string consists ○+3 of module type and the number of points.
Page 786 (c) Others • The specified slot is empty or the target module is during online module change. • The specified value (n) is not the start I/O number. • The specified value (n) is within the allowable setting range, but cannot be set in the I/O assignment setting screen of the PLC parameter dialog box.
Page 787: Trace Set/Reset (Trace,Tracer)
TRACE,TRACER 7.18.11 Trace Set/Reset (TRACE,TRACER) TRACE,TRACER Ver. High Basic Process Redundant Universal LCPU performance Universal model QCPU: Other than Q00UJCPU Command TRACE TRACE Command TRACER TRACER Internal Devices Setting R, ZR Constants Other Data Word Word –– –– Function The sampling trace function collects the specified device data of a CPU module consecutively at the specified timing.
Page 788 TRACE,TRACER TRACE (1) The TRACE instruction turns ON SM803, executes sampling by the number of times set for "After trigger number of times" in the Trace condition settings, latches the data and stops sampling trace. (2) The sampling is stopped if SM801 is turned OFF during the trace execution. (3) After the TRACE instruction is executed and the trace is completed, SM805 is turned ON.
Page 789: Writing Data To Designated File (Sp.fwrite)
SP.FWRITE 7.18.12 Writing Data to Designated File (SP.FWRITE) SP.FWRITE Ver. High Basic Process Redundant Universal LCPU performance Universal model QCPU: Other than Q00UJCPU/Q00UCPU/Q01UCPU Command SP.FWRITE SP.FWRITE Internal Devices Constants Setting R, ZR Other Data Word Word K, H –– –– ––...
Page 790 SP.FWRITE Setting Meaning Setting Range Set by Data Type Data When binary write is specified at , always set 0. When CSV format write is specified at No. of set the number of columns where data will be columns FFFF User written.
Page 791 SP.FWRITE Caution (1) For only QCPU, only the ATA card drive (2) can be set as (drive designation). Note that when the Flash card is loaded, the SP.FWRITE instruction cannot be used to perform writing. The SRAM card, standard RAM or standard ROM drive cannot be set. For only LCPU, only the SD memory card drive (2) can be set as (drive designation).
Page 792 SP.FWRITE Function (1) The designated number of data is written to the designated file. Set the execution/completion type in the control data to designate whether to write binary data without any conversion or to convert binary data into CSV format data before writing it. (For QCPU, writing is only supported for ATA cards.
Page 793 SP.FWRITE (4) When writing binary data (a) If the extension of the target file is omitted, ".BIN" is used as an extension. (b) When the designated file does not exist, a new file is created and the data is added/ saved from the beginning of the file.
Page 794 SP.FWRITE (e) When the designated number of columns is "0", the data is stored as single-row data in CSV format file. Example When data is written after CSV format conversion and the designated No. of columns is "0": D20 D99 M0 SP.FWRITE * Designation in word units H0100...
Page 795 SP.FWRITE (f) When data is written after CSV format conversion and the designated number of columns is other than "0", the data is stored as table data with designated number of columns in a CSV format file. Example When data is written after CSV format conversion and the designated No. of columns is other than "0": SP.FWRITE D20 D99 M0...
Page 796 SP.FWRITE (g) When data is added by the High Performance model QCPU/Process CPU/Redundant CPU/Universal model QCPU/LCPU of which the first 5 digits of the serial number are 01112 or higher: [Specify the file to which data will be written.] (If a file exists, delete it and create a new file again.) Execution type = CSV format...
Page 797 SP.FWRITE Below is the method for calculating the file size (total number of bytes) when a CSV format file is written to the ATA card. Total number of bytes = Total bytes excluding final line + bytes of final line (Number of bytes on a line = number of columns + 1 + total bytes of all data values on line...
Page 798 SP.FWRITE Operation Error (1) In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and an error code is stored into SD0. • Drive specified by drive designation device contains the medium other than the ATA card.
Page 799 SP.FWRITE Program Example (1) When X10 is turned ON, the following program adds four bytes of binary data (00 , 01 , and 03 ) to file "ABCD.BIN" in the memory card inserted to drive 2. • Assume that 8 points from are reserved for the control data devices.
Page 800 SP.FWRITE (2) When X10 is turned ON, the following program creates a file named "ABCD.CSV" in the memory card inserted to drive 1, and writes four bytes of data (00 , 01 , 02 , and 03 ) as two-column table data in CSV format. •...
Page 801: Reading Data From Designated File (Sp.fread)
SP.FREAD 7.18.13 Reading Data from Designated File (SP.FREAD) SP.FREAD Ver. High Basic Process Redundant Universal LCPU performance Universal model QCPU: Other than Q00UJCPU/Q00UCPU/Q01UCPU Command SP.FREAD SP.FREAD Internal Devices Constants Setting R, RZ Other Data Word Word K, H –– –– ––...
Page 802 SP.FREAD Setting Meaning Setting Range Set by Data Type Data Designate the file position to start reading when binary data reading is designated by 00000000 : Starting at the beginning of the file 00000001 to FFFFFFFE :From the designated position The unit for the value is determined by word/byte unit designation.
Page 803 SP.FREAD Setting Meaning Setting Range Set by Data Type Data Bit device that turned ON at the completion of the processing. +1 is also turned ON at error completion.) Device Item Contents/Setting Data Setting Range Set by Indicates the completion of the processing. Completion ON: Completed ––...
Page 804 SP.FREAD (3) Be sure to use word units to designate the number of request read data ( +2), file position +4 and +5), and read data device size ( The following shows how the individual device data is read in binary data reading operation. Control data D0+0 H0000...
Page 805 SP.FREAD (e) When the designated number of columns is 0, the data is read by ignoring the rows in CSV format file. Example When data is read after CSV format conversion and the designated No. of columns is 0: Data created by EXCEL Measured value Main / sub item Length...
Page 806 SP.FREAD If the number of columns varies in each row, the data is also read by ignoring the rows. Such file cannot be created using EXCEL. This happens when CSV file is modified by a user. Example If the number of columns varies in each row when the data is read: Main / sub item , , Measured value Excess CR LF...
Page 807 SP.FREAD (f) When data is read after CSV format conversion and the designated number of columns is other than 0, the data is read as the table with designated number of columns in CSV format file. The elements outside of the designated columns are ignored. Example When data is read after CSV format conversion and the designated No.
Page 808 SP.FREAD If the number of columns varies in each row, the elements outside of the designated columns are ignored and "0" is added to the places where elements do not exist. Example If the number of columns varies in each row when the data is read: Main / sub item , , Measured value Excess CR LF...
Page 809 SP.FREAD (g) With the High Performance model QCPU/Process CPU/Redundant CPU/Universal model QCPU/LCPU whose first 5 digits of the serial number are "01112" or later, it is possible to divide read operation into multiple times. [Specify the row desired to start read.] Execution type = CSV format Starting row number...
Page 810 SP.FREAD (h) When data is read after CSV format conversion, the numerical values that are out of range or the elements other than numerical values in the object CSV format file are converted into 0 When data is read after CSV format conversion, numerical values are read and converted as follows: Numerical Values in -32768 to -1...
Page 811 SP.FREAD Program Example (1) The following program reads 4 bytes of binary data from the beginning of file "ABCD.BIN" in the memory card inserted to drive 2 when X10 is turned ON. • Assume that 8 points from (D0) are reserved for the control data devices. •...
Page 812 SP.FREAD (2) The following program reads file "ABCD.CSV" in the PC card inserted to slot 0 as two-column table data in CSV format when X10 is turned ON. • Assume that 8 points from (D0) are reserved for the control data devices. •...
Page 813: Writing Data To Standard Rom (Sp.devst)
SP.DEVST 7.18.14 Writing Data to Standard ROM (SP.DEVST) SP.DEVST High Basic Process Redundant Universal LCPU performance Command SP.DEVST SP.DEVST n1: Write offset of the device data storage file (specified in units of 16-bit words) (BIN 32-bit) : Head device number written to the standard ROM (device name) n2: The number of write points (BIN 16-bit) +0 : FCompletion device (bit) +1 : FError completion device (bit)
Page 814 SP.DEVST (4) SM721 turns ON during execution of this instruction. When SM721 has already turned ON, this instruction can not be executed. (If executed, no processing is performed.) (5) When an error is detected at execution of this instruction, the completion device ( +0), error completion device ( +1) and SM721 do not turn ON.
Page 815: Read Data From Standard Rom (S(P).Devld)
(S(P).DEVLD) 7.18.15 Read Data from Standard ROM (S(P).DEVLD) (S(P).DEVLD) High Basic Process Redundant Universal LCPU performance Command S.DEVLD S.DEVLD Command SP.DEVLD SP.DEVLD n1 : Read offset of the device data storage file (specified in units of 16-bit words) (BIN 32-bit) : Head device number read from the standard ROM (device name) n2 : The number of reading points (BIN 16-bit) Internal Devices...
Page 816 (S(P).DEVLD) Operation Error (1) In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and an error code is stored into SD0. • The address specified at n1 is out of the standard ROM range. (Error code: 4100) •...
Page 817: Load Program From Memory Card (Ploadp)
PLOADP 7.18.16 Load Program from Memory Card (PLOADP) PLOADP High Basic Process Redundant Universal LCPU performance Command PLOADP PLOADP : Drive No. storing the program to be loaded, character string data of the file name, or head number of the devices storing the character string data (BIN 16 bits) : Device that turns ON for 1 scan by the instruction completion (bits) Internal Devices...
Page 818 PLOADP (b) When there are multiple open program Nos., the program designated by the PLOADP instruction is added to the lowest number among them to be added. (The open program Nos. are made when programs are deleted by the PUNLOADP instruction.) When programs No.
Page 819 PLOADP (10) The "PLOADP instruction" and "Write during RUN" processing cannot be executed simultaneously. (a) When a write during RUN request is given during processing of the PLOADP instruction, write during RUN is delayed. Write during RUN is started after the processing of the PLOADP instruction is completed.
Page 820: Unload Program From Program Memory (Punloadp)
PUNLOADP 7.18.17 Unload Program from Program Memory (PUNLOADP) PUNLOADP High Basic Process Redundant Universal LCPU performance Command PUNLOADP PUNLOADP : Character string data of the program file name to be unloaded, or head number of the devices storing the character string data (BIN 16 bits) : Device turned ON for 1 scan on completion of the instruction (bits) Internal Devices Setting...
Page 821 PUNLOADP (6) When the Programmable Controller is powered OFF, then ON or the CPU module is reset after execution of the PUNLOADP instruction, the following operation is performed. (a) When boot setting has been made in the PLC parameter dialog box, the program where the boot setting has been made is transferred to the program memory.
Page 822: Load + Unload (Pswapp)
PSWAPP 7.18.18 Load + Unload (PSWAPP) PSWAPP High Basic Process Redundant Universal LCPU performance Command PSWAPP PSWAPP : Character string data of the file name of the program to be unloaded, or head number of the devices storing the character string data (BIN 16 bits) : Drive No.
Page 823 PSWAPP (3) Drive Nos. 1, 2, and 4 can be specified. (Drive 3 cannot be specified.) • Drive 1: Memory card (RAM) • Drive 2: Memory card (ROM) • Drive 4: Standard ROM (4) An extension (.QPG) need not be specified for the file name. (5) The bit device specified by is turned ON during the END processing of the scan where this instruction is completed.
Page 824 PSWAPP Operation Error (1) In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and an error code is stored into SD0. • The drive No. or the file name designated by does not exist. (Error code: 2410) •...
Page 825: High-Speed Block Transfer Of File Register (Rbmov(P))
RBMOV(P) 7.18.19 High-speed Block Transfer of File Register (RBMOV(P)) RBMOV(P) Ver. High Basic Process Redundant Universal LCPU performance Universal model QCPU: Other than Q00UJCPU Command RBMOV RBMOV Command RBMOVP RBMOVP : Head number of the devices where the data to be transferred is stored (BIN 16 bits) : Head number of the devices of transfer destination (BIN 16 bits) : Number of data to be transferred (BIN 16 bits) Internal Devices...
Page 826 RBMOV(P) Example Transfer ranges of ZR and R overlap when transferring 10000 points of data from ZR30000 (source) to R10 (block No.1 of the destination). • ZR transfer range (30000) to (30000+10000-1) (30000) to (39999) • R transfer range (10+(1 32768)) to (10+(1 32768)+10000-1) (32778) to (42777) Therefore, the range 32778 to 39999 overlaps.
Page 827 RBMOV(P) Program Example (1) The following program outputs the lower four bits of data in R66 to R69 to Y30 through Y3F in units of 4 points. [Ladder Mode] [List Mode] Step Instruction Device Before execution After execution (source of transfer) (destination of transfer) 1 1 0 1 Y33 to Y30...
Page 828 RBMOV(P) The RBMOV (P) instruction is useful to batch transfer a large quantity of file register data with the QnHCPU/QnPHCPU/QnPRHCPU. For the QnUCPU, the processing speed of the RBMOV instruction is equivalent to that of the BMOV instruction. The comparison of processing speed between the RBMOV and BMOV instructions is as follows: (1)Transfer from file registers to internal devices/internal devices to file registers 1 word...
Page 829 RBMOV(P) (2)Transfer from file registers to file registers 1 word 1000 words 10000 words Target memory where Instruction file register is stored Min. Max. Min. Max. Min. Max. Standard RAM 20.0 µs 91.0 µs 775.0 µs RBMOV QnHCPU SRAM card 22.5 µs 545.0 µs 5300.0 µs...
Page 830: User Message (Umsg)
7.18.20 User Message (UMSG) High Basic Process Redundant Universal LCPU performance Command UMSG UMSG : String to display on display unit, or lead number (string) of device storing string to display Internal Device Constants Indirect Setting R, ZR Specifica- Others Real Data Word...
Page 831 (3) The user message is displayed when the UMSG instruction command is rising. If the string is changed while the command is on, then the modified user message will appear in the display unit. (4) The string specified by the UMSG instruction is displayed upon END processing. If two or more UMSG instructions are executed, then the last UMSG instruction executed before the END is valid.
Page 832 Program Example (1) This program displays the string stored after D10 on the display unit, when X10 is set to "on". [Circuit Mode] [List Mode] Step Instruction Device [Action] b15 to b8 b7 to b0 User message Line-A Working Run UMSG instruction (2) This program displays "Line-A Working"...
Page 833 (3) This program displays "Line-B stop" on the display unit when X10 is set to "on", and clears the message when X10 is set to "off". [Ladder Mode] [List Mode] Step Instruction Device "Line-B stop" "Line-B stop" [Action] X10 set to "on" X10 set to "off"...
Page 834 MEMO 7-460...
Page 835 INDEX Index-1...
Page 836 INDEX ....6-15 0 to 9 BIN block data comparisons ....5-40 Bit device output reverse .
Page 837 . . . 6-89 ..... . 7-355 Conversion from BIN 16-bit to BIN 32-bit data Date comparison . . . 6-90 .
Page 838 List of instructions for reading from the CPU ... . . 2-60 shared memory of another CPU ....1-5 High Performance model QCPU List of instructions for reading/writing routing .
Page 839 ....5-15 Operation results inversion ... . . 5-12 Operation results push,read,pop ......6-161 .
Page 840 Square root operation for floating-point data ..... .7-288 (Double precision) Square root operation for floating-point data ..... . .7-286 (Single precision) .
Page 841 INSTRUCTION INDEX ......6-101 Symbols BKBIN(P) BKCMP ....... . 6-15 .
Page 842 ......7-323 ......7-19 DBAND(P) DXOR(P) .
Page 843 ......6-135 ....... 6-170 GOEND .
Page 844 .......7-38 ......7-413 ROL(P) TRACE .
Page 845 6. Failure caused by reasons unpredictable by scientific technology standards at time of shipment from Mitsubishi. 7. Any other failure found not to be the responsibility of Mitsubishi or that admitted not to be so by the user. 2. Onerous repair term after discontinuation of production (1) Mitsubishi shall accept onerous product repairs for seven (7) years after production of the product is discontinued.
Page 846 Microsoft, Windows, Windows NT are registered trademarks of Microsoft Corporation in the United States and other countries. Pentium and Celeron are trademarks of Intel Corporation in the United States and other countries. Ethernet is a trademark of Xerox Co., Ltd. in the United States. CompactFlash is a trademark of SanDisk Corporation.
Page 851: Safety Precautions
SAFETY PRECAUTIONS (Always read these cautions before using the product) Before using this product, please read this manual and the related manuals introduced in this manual, and pay full attention to safety to handle the product correctly. Please store this manual in a safe place and make it accessible when required. Always forward a copy of the manual to the end user.
Page 852: Conditions Of Use For The Product
CONDITIONS OF USE FOR THE PRODUCT (1) Mitsubishi programmable controller ("the PRODUCT") shall be used in conditions; i) where any problem, fault or failure occurring in the PRODUCT, if any, shall not lead to any major or serious accident; and...
Page 853: Revisions
This manual confers no industrial property rights or any rights of any other kind, nor does it confer any patent licenses. Mitsubishi Electric Corporation cannot be held responsible for any problems involving industrial property rights which may occur as a result of using the contents noted in this manual.
Page 854: Introduction
INTRODUCTION This document is the MELSEC-Q/L Programming Manual (Common Instructions). It describes the common instructions required for programming of the QCPU and LCPU. • "Common instructions" are all instructions except for dedicated instructions for such intelligent function modules as QJ71C24N and QJ71E71-100; PID control instructions; SFC instructions; ST instructions; instructions for socket communication features;...
Page 855 MEMO...
Page 856: Contents
CONTENTS SAFETY PRECAUTIONS ........................A - 1 CONDITIONS OF USE FOR THE PRODUCT ..................A - 2 REVISIONS ............................A - 3 INTRODUCTION ..........................A - 4 CONTENTS ............................A - 6 MANUALS............................A - 17 Common Instructions 1/2 1. GENERAL DESCRIPTION 1 - 1 to 1 - 8 Related Programming Manuals 1 - 2 Abbreviations and Generic Names...
Page 857: Sequence Instructions
2.5.11 Character string processing instructions ..............2 - 43 2.5.12 Special function instructions ..................2 - 46 2.5.13 Data control instructions ..................... 2 - 49 2.5.14 Switching instructions ....................2 - 51 2.5.15 Clock instructions ....................... 2 - 52 2.5.16 Expansion clock instruction ..................2 - 55 2.5.17 Program control instructions..................
Page 858: Association Instructions
5.1.2 Pulse operation start, pulse series connection, pulse parallel connection (LDP,LDF,ANDP,ANDF,ORP,ORF) ................5 - 5 5.1.3 Pulse NOT operation start, pulse NOT series connection, pulse NOT parallel connection (LDPI,LDFI,ANDPI,ANDFI,ORPI,ORFI) ............... 5 - 7 Association Instructions 5 - 10 5.2.1 Ladder block series connection and parallel connection (ANB,ORB) ......5 - 10 5.2.2 Operation results push,read,pop (MPS,MRD,MPP) ...........
Page 859: Data Transfer Instructions 6 - 107 6.4.1 16-Bit And 32-Bit Data Transfers (Mov(P),Dmov(P))
6.2.3 BIN 16-bit multiplication and division operations (*(P),/(P))........6 - 30 6.2.4 BIN 32-bit multiplication and division operations (D*(P),D/(P)) ........6 - 32 6.2.5 BCD 4-digit addition and subtraction operations (B+(P),B-(P)) ........6 - 34 6.2.6 BCD 8-digit addition and subtraction operations (DB+(P),DB-(P)) ......6 - 38 6.2.7 BCD 4-digit multiplication and division operations (B*(P),B/(P)) ........
Page 860: Program Branch Instructions
6.4.8 Identical 32-bit data block transfers (DFMOV(P))............. 6 - 125 6.4.9 16-bit and 32-bit data exchanges (XCH(P),DXCH(P)) ..........6 - 127 6.4.10 Block 16-bit data exchanges (BXCH(P)) ..............6 - 129 6.4.11 Upper and lower byte exchanges (SWAP(P)) ............6 - 131 Program Branch Instructions 6 - 132 6.5.1...
Page 861: Data Processing Instructions
7.4.1 Bit set and reset for word devices (BSET(P),BRST(P)) ..........7 - 59 7.4.2 Bit tests (TEST(P),DTEST(P))..................7 - 61 7.4.3 Batch reset of bit devices (BKRST(P)) ............... 7 - 64 Data processing instructions 7 - 66 7.5.1 16-bit and 32-bit data searches (SER(P),DSER(P))........... 7 - 66 7.5.2 16-bit and 32-bit data checks (SUM(P),DSUM(P)).............
Page 862: Debugging And Failure Diagnosis Instructions
7.10 Debugging and failure diagnosis instructions 7 - 174 7.10.1 Special format failure checks (CHKST,CHK) ............7 - 174 7.10.2 Changing check format of CHK instruction (CHKCIR,CHKEND) ......7 - 178 7.11 Character string processing instructions 7 - 182 7.11.1 Conversion from BIN 16-bit or 32-bit to decimal ASCII (BINDA(P),DBINDA(P))..7 - 182 7.11.2 Conversion from BIN 16-bit or 32-bit data to hexadecimal ASCII (BINHA(P),DBINHA(P)) ....................
Page 863 7.12.17 Exponentiation operation on floating-point data (Single precision) (POW(P))..7 - 282 7.12.18 Exponentiation operation on floating-point data (Single precision) (POWD(P)) ..7 - 284 7.12.19 Square root operation for floating-point data (Single precision) (SQR(P)) ....7 - 286 7.12.20 Square root operation for floating-point data (Double precision) (SQRD(P)) ... 7 - 288 7.12.21 Exponent operation on floating-point data (Single precision) (EXP(P))....
Page 864 7.17.2 Program output OFF standby instruction (POFF(P))..........7 - 377 7.17.3 Program scan execution registration instruction (PSCAN(P)) ........7 - 379 7.17.4 Program low speed execution registration instruction (PLOW(P)) ......7 - 381 7.17.5 Program execution status check instruction (PCHK)..........7 - 383 7.18 Other instructions 7 - 385 7.18.1 Resetting watchdog timer (WDT(P)).................
Page 865 11. QCPU INSTRUCTIONS 11 - 1 to 11 - 4 11.1 System Switching Instruction (SP.CONTSW) 11 - 2 12. ERROR CODES 12 - 1 to 12 - 88 12.1 Error Code List 12 - 2 12.1.1 Error codes ......................... 12 - 3 12.1.2 Reading an error code....................
Page 866: Index - 1 To Index
INDEX Index - 1 to Index - 10 INDEX Index- 2 INSTRUCTION INDEX Index- 7 A-16...
Page 867: Manuals
MANUALS To understand the main specifications, functions, and usage of the CPU module, refer to the basic manuals. Read other manuals as well when using a different type of CPU module and its functions. Order each manual as needed, referring to the following list. The numbers in the "CPU module"...
Page 868 Basic manual, :Other CPU module manuals CPU module Manual name Description < Manual number (model code) > ■Programming Manual MELSEC-Q /L Programming Manual (Common How to use sequence instructions, basic instructions, Instructions) and application instructions < SH-080809ENG (13JW10) > System configuration, performance specifications, MELSEC-Q /L/QnA Programming Manual (SFC) functions, programming, debugging, and error codes <...
Page 869 INSTRUCTIONS FOR DATA LINK Reference Category Processing Details section Network refresh instructions Section 8.1 Refreshes the specified network module. Section 8.2.1 Reading the data specified by routing parameters. Routing information read/write instructions Writing routing data to the area specified by routing parameters. Section 8.2.2 Remark In this chapter, instruction names are abbreviated as follows if not specified...
Page 870: Network Refresh Instructions
ZCOM Network refresh instructions 8.1.1 Refresh instruction for the designated module (S(P).ZCOM) ZCOM High Basic Process Redundant Universal LCPU performance Command S.ZCOM S.ZCOM Command SP.ZCOM SP.ZCOM Command S.ZCOM S.ZCOM Command SP.ZCOM SP.ZCOM Jn : Network No. of host station (BIN 16 bits) (QCPU only) Un : Head I/O number of host station network module (BIN 16 bits) Internal Devices Setting...
Page 871 ZCOM (2) The ZCOM instruction does not perform the following processing. (a) Communication processing between CPU module and programming tool (b) Monitor processing of other station (c) Read processing of buffer memory of other intelligent function module by serial communication module. (d) Low-speed cyclic data transmission of MELSECNET/H (3) PLC to PLC network (QCPU only)
Page 872 ZCOM (4) Remote I/O network (QCPU only) The link refresh of the remote master station is performed by the "END processing" of the CPU module. Since link scan is performed at completion of link refresh, link scan 'synchronizes' with the program of the CPU module.
Page 873 ZCOM (6) Designating "Un" in the argument enables the target designation of the intelligent function as well as the network modules. In this case, the auto refresh is performed for the buffer memory of the intelligent function modules. (It replaces the FROM/TO instructions.) (7) Only with the Universal model QCPU and LCPU, interruption of processing is enabled during the execution of the ZCOM instruction.
Page 874: Reading/Writing Routing Information
RTREAD Reading/Writing Routing Information 8.2.1 Reading routing information (S(P).RTREAD) RTREAD High Basic Process Redundant Universal LCPU performance Command S.RTREAD S.RTREAD Command SP.RTREAD SP.RTREAD : Transfer destination network No. (1 to 239) (BIN 16 bits) : Head number of the devices that stores the read data (Device name) Internal Devices Setting Constants...
Page 875 RTREAD Program Example (1) The following program reads the routing information for the network number specified by D0 when X0 is turned ON. [Ladder Mode] [List Mode] Step Instruction Device [Operation] [Content of routing parameter setting] Transfer Relay network Relay station destination number number...
Page 876: Registering Routing Information (S(P).Rtwrite)
RTWRITE 8.2.2 Registering routing information (S(P).RTWRITE) RTWRITE High Basic Process Redundant Universal LCPU performance Command S.RTWRITE S.RTWRITE Command SP.RTWRITE SP.RTWRITE : Transfer destination network No. (1 to 239) (BIN 16 bits) : Head number of the devices where the data to be written is stored (Device name) Internal Devices Setting Constants...
Page 877 RTWRITE Program Example (1) The following program writes the routing information specified by D1 to D3 to the network module of the network number specified by D0 when X0 is turned ON. [Ladder Mode] [List Mode] Step Instruction Device [Operation] [Content of routing parameter setting] Transfer Relay station...
Page 878 MEMO 8-10...
Page 879 MULTIPLE CPU DEDICATED INSTRUCTION Reference Category Processing Details section Writing to the CPU shared Writes device data of the host CPU to the CPU shared Section 9.1 memory of host CPU memory of the host CPU module. Reading from the CPU shared Reads device data from the CPU shared memory of another Section 9.2 memory of another CPU...
Page 880: Writing To The Cpu Shared Memory Of Host Cpu
Writing to the CPU Shared Memory of Host CPU The S.TO or TO instruction is used to write to the CPU shared memory of the host station in the multiple CPU system. The following table indicates the usability of the S.TO and TO instructions. CPU Module Type Name S.TO Instruction TO Instruction...
Page 881 (2) Operation of the TO instruction The TO instruction can write device memory data to the following memories. • CPU shared memory of host CPU module • Buffer memory of intelligent function module The following figure shows the processing performed when the TO instruction is executed in CPU No.
Page 882: Write To Host Cpu Shared Memory (S(P).To)
S(P).TO 9.1.1 Write to Host CPU Shared Memory (S(P).TO) S(P).TO Ver. Ver. High Basic Process Redundant Universal LCPU performance Basic model QCPU:The first 5 digits of serial No is "04122" or higher. Hight performance modele QCPU:Function version B or later. Command S.TO S.TO...
Page 883 S(P).TO (a) CPU shared memory address of the Basic model QCPU CPU shared memory address Host CPU operation information area Write designation 96(60 prohibited area System area 192(C0 Host CPU refresh area Write designation permitted area User free area 511(1FF (b) CPU shared memory address of the High Performance model QCPU, Process CPU and Universal model QCPU* CPU shared memory address...
Page 884 S(P).TO Operation Error In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and an error code is stored into SD0. (1) When the specified data is outside the following range (Error code: 4101) •...
Page 885: Writing To Host Station Cpu Shared Memory (To(P), Dto(P))
TO(P), DTO(P) 9.1.2 Writing to host station CPU shared memory (TO(P), DTO(P)) Ver. High Basic Process Redundant Universal LCPU performance Q00CPU/Q01CPU whose first 5 digits of the serial No. is "04122" or higher TO(P), DTO(P) indicates an instruction symbol of TO/DTO. Command TO,DTO Command...
Page 886 TO(P), DTO(P) When a constant is specified to , writes the same data (value specified to ) to the area of n3 words from the specified CPU shared memory. CPU shared memory of host CPU (n1) Constant (When "5" is designated Writes the n3 words same data to...
Page 887 TO(P), DTO(P) (1) Writes device data of words to (n3×2) to the CPU shared memory address specified by n2 of the host CPU module or later address. Host CPU CPU shared memory Device memory of host CPU (n1) n3 2 Writes the data of (n3 2) words...
Page 888 TO(P), DTO(P) Operation Error In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and an error code is stored into SD0. (1) When the specified data is outside the following range (Error code: 4101) •...
Page 889: Reading From The Cpu Shared Memory Of Another Cpu
Reading from the CPU Shared Memory of another CPU The FROM(P)/DFRO(P) instruction of Multiple CPU system can be read from the following memories. • Buffer memory of intelligent function module • CPU shared memory of other CPU module • CPU shared memory of host CPU module (applicable for the Basic model QCPU and Universal model QCPU) The following figure shows the processing performed when the FROM(P) instruction is executed in CPU No.
Page 890: Reading From Other Cpu Shared Memory (From(P), Dfro(P))
FROM(P),DFRO(P) 9.2.1 Reading from Other CPU Shared Memory (FROM(P), DFRO(P)) FROM(P),DFRO(P) Ver. Ver. High Basic Process Redundant Universal LCPU performance Basic model QCPU:The first 5 digits of serial No is "04122" or higher. High performance model QCPU:Function version B or later. (1) When Basic model QCPU, Universal model QCPU is used indicates an instruction symbol of FROM/DFRO.
Page 891 FROM(P),DFRO(P) (a) CPU shared memory address of the Basic model QCPU CPU shared memory address Host CPU operation information area 96(60 System area 192(C0 Host CPU refresh area Read designation permitted area User free area 511(1FF (b) CPU shared memory address of the Universal model QCPU CPU shared memory address Host CPU operation information area 512(200...
Page 892 FROM(P),DFRO(P) (2) When 0 is specified in n3 as the number of data to be read, no processing is performed. (3) The number of data to be read changes depending on the target CPU module. CPU Module Number of Read Points Basic model QCPU 1 to 256 1 to 7168...
Page 893 FROM(P),DFRO(P) Program Example (1) The following program stores 10 points of data from address C0 of the CPU shared memory of CPU No. 2 into the area starting from D0 when X0 is turned ON. [Ladder Mode] [List Mode] Step Instruction Device (2) The following program stores 20 points of data from address 10000 of the CPU shared...
Page 894 FROM(P),DFRO(P) (2) When High Performance model QCPU, Process CPU is used Command FROM FROM Command FROMP FROMP n1 : Head I/O number of the reading target CPU module (BIN 16 bits) n2 : Head address of data to be read (BIN 16 bits) : Head number of the devices where the read data is stored (BIN 16 bits) n3 : Number of read data (BIN 16 bits) Internal Devices...
Page 895 FROM(P),DFRO(P) Read of data from the CPU shared memory can also be performed using the intelligent function module devices. For intelligent function module device, refer to the QnUCPU User's Manual (Function Explanation, Program Fundamentals) or Qn(H)/QnPH/QnPRHCPU User's Manual (Function Explanation, Program Fundamentals). Operation Error In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and an error code is stored into SD0.
Page 896 MEMO 9-18...
Page 897 QCPU INSTRUCTIONS Reference Category Processing Details section Write instruction to another CPU Writes devices to another CPU. Section 10.2 Read instruction from another Section 10.3 Reads devices from another CPU. 10-1...
Page 898: Overview
10.1 Overview The multiple CPU high-speed transmission dedicated instruction directs the Universal model QCPU to write/read device data to/from the Universal model QCPU in another CPU. The following shows an operation when CPU No.1 writes device data to CPU No.2 with the multiple CPU high-speed transmission dedicated instruction.
Page 899 (2) Writable/readable devices (a) Writable/readable device names The following table shows the devices that can be written to/read from the Univesal model QCPU in another CPU with the multiple CPU high-speed transmission dedicated instruction. Setting of target Category Type Device name Remarks device Requirements for the setting...
Page 900 Writable/readable device range in device specification Host CPU Another CPU Data register Data register Writable/readable (12k points) (16k points) D12287 D12287 D12288 Not writable/not readable D16383 (b) String specification The string specification is a method to specify a device in another CPU to be written/ read by character string.
Page 901 (4) Managing the multiple CPU high speed transmission area (a) The multiple CPU high speed transmission area is managed by blocks in units of 16 words. The following table shows the number of blocks that can be used in each CPU and the number of blocks used in the instruction.
Page 902 (6) The multiple CPU high-speed transmission dedicated instructions that can be executed concurrently For the Universal model QCPU, the multiple CPU high-speed transmission dedicated instructions can be concurrently executed within the range satisfying the following formula. The number of blocks that Total number of blocks used for the can be used in each CPU instructions concurrently executed...
Page 903 (7) Interlock when using the multiple CPU high-speed transmission dedicated instruction (a) Special relays SM796 to SM799 (maximum number of used blocks for multiple CPU high-speed transmission dedicated instruction setting) can be used as an interlock for the multiple CPU high-speed transmission dedicated instruction. When executing the multiple CPU high-speed transmission dedicated instructions concurrently, use SM796 to SM799 as an interlock for the instructions.
Page 904 (b) Program example when SM796 to SM799 are used as an interlock The following shows a program that executes the D.DDWR instruction to CPU No.2 at the rise of X0, and executes the D.DDWR instruction to CPU No.3 at the rise of X1. The maximum number of used blocks for multiple CPU hight speed transmission dedicated SM402 SD797...
Page 905 (8) Program example when the multiple CPU high-speed transmission dedicated instructions are executed to CPU modules by turns When the multiple CPU high-speed transmission dedicated instructions are executed to Universal model QCPUs by turns, release an interlock to prevent the concurrent execution. Use the cyclic transmission area device (from U3En\G10000) as an interlock.
Page 906 Program example when the multiple CPU high-speed transmission dedicated instruction is executed at CPU No.2 SM402 SD796 Turn-on for one Maximum number of used blocks scan after RUN (CPU No.1) During execution the Read instruction DDRD instruction U3E1\G10000.0 is turned on while CPU No.2 is executing the DP.DDRD instruction. U3E0\G10000.0 SM796 U3E1\...
Page 907 (a) Program example when one D(P).DDWR instruction is executThe following shows a program example that writes ZR0 to ZR999 (1000 points) in CPU No.1 to ZR0 to ZR999 in CPU No.2 with the D.DDWR instruction. In the following program example, the next D.DDWR instruction is executed after the completion device of the D.DDWR instruction (M2) turns on so that only one D.DDWR instruction may be executed.
Page 908 (b) Program example when the D(P).DDWR instructions are executed concurrently The following shows a program example that writes ZR0 to ZR999 (1000 points) in CPU No.1 to ZR0 to ZR999 in CPU No.2 with the D.DDWR instruction. As shown on the program example, multiple CPU device write/read instructions can be executed concurrently.
Page 909: Writing Devices To Another Cpu (D(P).Ddwr)
D(P).DDWR 10.2 Writing Devices to Another CPU (D(P).DDWR) D(P).DDWR Ver. High Basic Process Redundant Universal LCPU performance Q03UDCPU, Q04UDHCPU, Q06UDHCPU: that the first 5 digits of serial number is 10012 or higer QnUDE(H)CPU. Command D.DDWR D.DDWR Command DP.DDWR DP.DDWR Internal device Setting Constant R, ZR...
Page 910 D(P).DDWR Control Data Device Item Setting data Setting range Set by An execution result upon completion of the instruction is stored. Completion status –– System 0000(H): No errors (normal completion) Other than 0000(H): Error code (error completion) Number of write Set the number of write points in units of words.
Page 911 D(P).DDWR (3) The number of blocks used for the instruction depends on the number of write points (refer to Section 12.1). Number of blocks used for the instruction Number of write points D(P).DDWR specified by the instruction instruction 1 to 4 5 to 20 21 to 36 37 to 52...
Page 912 D(P).DDWR In any of the following cases, the instruction is completed abnormally, and an error code is stored into a device specified at completion status storage device ( +0). (1) The request of the instruction to the target CPU is more than the acceptable value (no empty blocks exist in the multiple CPU high speed transmission area).
Page 913: Reading Devices From Another Cpu (D(P).Ddrd)
D(P).DDRD 10.3 Reading Devices from Another CPU (D(P).DDRD) D(P).DDRD Ver. High Basic Process Redundant Universal LCPU performance Q03UDCPU, Q04UDHCPU, Q06UDHCPU: that the first 5 digits of serial number is 10012 or higer QnUDE(H)CPU. Command D.DDRD D.DDRD Command DP.DDRD DP.DDRD Internal device Setting Constant R, ZR...
Page 914 D(P).DDRD Control Data Device Item Setting data Setting range Set by An execution result upon completion of the instruction is stored. Completion status –– System 0000( ): No errors (normal completion) Other than 0000( ): Error code (error completion) Number of read Set the number of read points in units of words.
Page 915 D(P).DDRD Operation Error In any of the following cases, an operation error occurs, the error flag (SM0) turns on, and an error code is stored into SD0. (1) Specified another CPU is wrong or the multiple CPU high-speed transmission dedicated instruction cannot be used in the setting (Error code: 4350).
Page 916 D(P).DDRD Program Example (1) This program stores data by 10 words starting from D0 in CPU No.2 into W10 or later in host CPU when X0 turns on. [Ladder mode] [List mode] Caution (1) Digit specification of bit device is possible for n, , and .
Page 917 QCPU INSTRUCTIONS Reference Category Processing Details section Switches between the control system and standby system at System switching instruction the END processing of the scan executed with the Section 11.1 SP.CONTSW instruction. 11-1...
Page 918 SP.CONTSW 11.1 System Switching Instruction (SP.CONTSW) SP.CONTSW High Basic Process Redundant Universal LCPU performance Command SP.CONTSW SP.CONTSW : Value other than 0 and used to identify the processing that issued the system switching request (BIN 16 bits) : Error completion device number (bits) Internal Devices Setting Constants...
Page 919 SP.CONTSW (5) The error completion device is turned ON by the control system CPU module when system switching by the SP.CONTSW instruction was unsuccessful. (a) When OPERATION ERROR is detected due to any of the following reasons at the execution of the SP.CONTSW instruction, the error completion device is turned ON during the instruction execution.
Page 920 SP.CONTSW (2) If system switching was unsuccessful, the error flag (SM0) is turned ON and an error code is stored into SD0. • The tracking cable is disconnected or faulty. (Error code: 6220) • Hardware fault, power-off, reset or watchdog timer error occurred in the standby system. (Error code: 6220) •...
Page 921: Error Codes
ERROR CODES 12-1...
Page 922: Error Code List
12.1 Error Code List The CPU module uses the self diagnostics function to display error information (on the LED) and stores the information into the special relay SM and special register SD, when an error occurs in the following situations: •...
Page 923: Reading An Error Code
Determine the error level, i.e. whether the operation can be continued or stopped, by referring to "Operating Statuses of CPU" described in Section 12.1.3 to 12.1.9 "Error Code List" 2: When detected an error code without being noted in the reference table, please contact your local Mitsubishi representive. 12.1.2 Reading an error code When an error occurs, reading an error code, error message or the like can be executed with GX Developer.
Page 924: Error Code List (1000 To 1999)
• Always 1000 a hardware failure of the CPU module. (Please [CPU UNIT DOWN] consult your local Mitsubishi representative, Runaway or failure of the CPU module explaining a detailed description of the • Malfunctioning due to noise or other reason problem.)
Page 925 1003 a hardware failure of the CPU module. (Please Flicker [CPU UNIT DOWN] consult your local Mitsubishi representative, Runaway or failure of the CPU module explaining a detailed description of the CPU Status: • Malfunctioning due to noise or other reason problem.)
Page 926 • Hardware failure ■Collateral information a hardware failure of the CPU module. (Please QCPU • Common Information:- consult your local Mitsubishi representative, • Individual Information:- explaining a detailed description of the ■Diagnostic Timing problem.) • Always...
Page 927 QnPRH extension cable. (Please consult your local module. ■Collateral information Mitsubishi representative, explaining a detailed • Common Information:- description of the problem.) • Individual Information:- 1009 ■Diagnostic Timing •...
Page 928 1035 a failure of the CPU module. (Please consult [CPU UNIT DOWN] Runaway or failure of the CPU module your local Mitsubishi representative, explaining • Malfunction due to noise etc. a detailed description of the problem.) • Hardware failure ■Collateral information LCPU •...
Page 929 • Individual Information:- ■Diagnostic Timing The cause is a hardware failure of the CPU • Always module. (Please consult your local Mitsubishi representative, explaining a detailed description of [TRK. CIR. ERROR] A fault was detected by the initial check of the the problem.)
Page 930 A fault was detected by the initial check of the The cause is a hardware failure of the CPU tracking hardware. QnPRH module. (Please consult your local Mitsubishi ■Collateral information 1115 • Common Information:- representative, explaining a detailed description of •...
Page 931 • Common Information:- • Individual Information:- ■Diagnostic Timing The cause is a hardware failure of the CPU • At power-on/At reset module. (Please consult your local Mitsubishi QCPU representative, explaining a detailed description of LCPU [OPE. CIRCUIT ERR.] the problem.) The hardware (logic) in the CPU module does not operate normally.
Page 932 • Individual Information:- ■Diagnostic Timing The cause is a hardware failure of the CPU ERR.: • When an END instruction executed module. (Please consult your local Mitsubishi Flicker QnPRH representative, explaining a detailed description of [OPE. CIRCUIT ERR.] the problem.)
Page 933 CPU module, I/O module, intelligent function module, or END LCPU ■Collateral information • Common Information:- cover. (Please consult your local Mitsubishi • Individual Information:- representative, explaining a detailed description ■Diagnostic Timing of the problem.) • During interrupt [I/O INT.
Page 934 • Common information: Module No. (Slot No.) module, intelligent function module, or END LCPU • Individual information: Program error location cover. (Please consult your local Mitsubishi ■Diagnostic Timing representative, explaining a detailed description • When an intelligent function module access of the problem.)
Page 935 CPU • Individual Information:- module, or base unit. (Please consult your local ■Diagnostic Timing Mitsubishi representative, explaining a detailed • When an END instruction executed description of the problem.) [SP. UNIT DOWN] • There was no response from the intelligent function module/special function module when the END instruction is executed.
Page 936 ERR.: • Common Information: Module No. (Slot No.) the intelligent function module, CPU module, or Flicker • Individual Information:- base unit. (Please consult your local Mitsubishi ■Diagnostic Timing 1414 representative, explaining a detailed description • Always CPU Status: of the problem.)
Page 937 Q01CPU • Common Information: Module No. (Slot No.) CPU module, or base unit. (Please consult your • Individual Information:- local Mitsubishi representative, explaining a ■Diagnostic Timing detailed description of the problem.) • At power-on/At reset [CONTROL-BUS. ERR.] A reset signal error was detected on the system bus.
Page 938 • Individual Information:- a failure of the CPU module. (Please consult ■Diagnostic Timing your local Mitsubishi representative, explaining 1435 • Always a detailed description of the problem.) Reset the CPU module and run it again. If the...
Page 939 • Always intelligent function module, or END cover. (Please [UNIT BUS ERROR] consult your local Mitsubishi representative, • An error was detected on the system bus. explaining a detailed description of the problem.) • An error was detected in the connected module.
Page 940 CPU operations when an error occurred can determined with a parameter. (LED indication varies according to the status of the CPU module) The BAT. LED turns on or flashes if the BATTERY ERROR occurs. Intelligent function module operations when an error occurred can be selected with a parameter from either to stop or continue.
Page 941: Error Code List (2000 To 2999)
12.1.4 Error code list (2000 to 2999) The following shows the error messages from the error code 2000 to 2999, the contents and causes of the errors, and the corrective actions for the errors. Error LED Status Corresponding Error Contents and Cause Corrective Action Code CPU Status...
Page 942 • At power-on/At reset is a hardware failure of the CPU module, I/O LCPU module, intelligent function module, or END [NO END COVER] cover. (Please consult your local Mitsubishi No END cover. representative, explaining a detailed ■Collateral information • Common information:- 2031 description of the problem.)
Page 943 CPU module, I/O ■Diagnostic Timing module, intelligent function module, or END • Always cover. (Please consult your local Mitsubishi representative, explaining a detailed description of the problem.) [SP. UNIT LAY ERR.] The slot where the QI60 is mounted was assigned...
Page 944 CPU module, I/O dialog box, the number of points assigned to the intelligent function module is less than that of the module, intelligent function module, or END cover. (Please consult your local Mitsubishi mounted module. ■Collateral information representative, explaining a detailed •...
Page 945 Error LED Status Corresponding Error Contents and Cause Corrective Action Code CPU Status [SP. UNIT LAY ERR.] Two or more QI60 modules where interrupt pointer setting has not been made are mounted. • Reduce the QI60 modules to one. ■Collateral information Q00J/Q00/Q01 2103 •...
Page 946 • Common information: Module No. (Slot No.) is a hardware failure of the CPU module, I/O • Individual information:- module, intelligent function module, or END ■Diagnostic Timing cover. (Please consult your local Mitsubishi • At power-on/At reset representative, explaining a detailed description of the problem.) 12-26...
Page 947 CPU module, I/O • Common information: Module No. (Slot No.) module, intelligent function module, or END • Individual information: Program error location cover. (Please consult your local Mitsubishi ■Diagnostic Timing representative, explaining a detailed • When instruction executed description of the problem.)
Page 948 CPU module, I/O • Individual information: Program error location module, intelligent function module, or END ■Diagnostic Timing cover. (Please consult your local Mitsubishi • When instruction executed/STOP→RUN representative, explaining a detailed description of the problem.) RUN: [SP.
Page 949 Error LED Status Corresponding Error Contents and Cause Corrective Action Code CPU Status [SP. UNIT ERROR] A CPU module that cannot be specified in the Read individual information of the error using the instruction dedicated to the multiple CPU system Q00J/Q00/Q01 programming tool to identify the numeric value was specified.
Page 950 Error LED Status Corresponding Error Contents and Cause Corrective Action Code CPU Status [SP. UNIT LAY ERR.] • A module is mounted on the 65th slot or later • Remove the module mounted on the 65th slot slot. or later slot. •...
Page 951 CPU module, I/O • Individual information:- module, intelligent function module, or END ■Diagnostic Timing cover. (Please consult your local Mitsubishi • At power-on/At reset representative, explaining a detailed description of the problem.) • Reduce the number of connectable modules to [SP.
Page 952 CPU module, I/O LCPU • Common information:- module, intelligent function module, or END • Individual information:- cover. (Please consult your local Mitsubishi ■Diagnostic Timing representative, explaining a detailed At power-on/At reset description of the problem)
Page 953 Qn(H) ■Collateral information • The cause is a hardware failure of the CPU QnPRH • Common information: Drive name 2211 module. (Please consult your local Mitsubishi • Individual information:- representative, explaining a detailed LCPU ■Diagnostic Timing description of the problem.) •...
Page 954 Error LED Status Corresponding Error Contents and Cause Corrective Action Code CPU Status [RESTORE ERROR] • The device information (number of points) backed up by the device data backup function is different from that configured in the PLC Parameter dialog box. •...
Page 955 • When memory card is inserted or removed Flicker/On If the same error code is displayed again, the cause is a failure of the memory card. (Please CPU Status: consult your local Mitsubishi representative, Stop/ explaining a detailed description of the problem.) Continue [ICM. OPE. ERROR] 2301 •...
Page 956 Error LED Status Corresponding Error Contents and Cause Corrective Action Code CPU Status [FILE SET ERROR] Automatic write to standard ROM was performed on the CPU module that is incompatible with • Execute automatic write to standard ROM on automatic write to standard ROM. the CPU module which is compatible with (Memory card where automatic write to standard automatic write to standard ROM.
Page 957 Error LED Status Corresponding Error Contents and Cause Corrective Action Code CPU Status [FILE SET ERROR] Program memory capacity was exceeded by performing boot operation or automatic write to standard ROM. Qn(H) ■Collateral information QnPH • Common information: File name/Drive name QnPRH •...
Page 958 Error LED Status Corresponding Error Contents and Cause Corrective Action Code CPU Status [FILE SET ERROR] When the extended data register and extended link register are configured in the File Register RUN: Extended Setting in the Device tab of the PLC •...
Page 959 Error LED Status Corresponding Error Contents and Cause Corrective Action Code CPU Status [CAN'T EXE. PRG.] • Any of the program files are using a device that • Read the common information of the error is out of the range configured in the Device tab using the programming tool to identify the of the PLC Parameter dialog box.
Page 960 Error LED Status Corresponding Error Contents and Cause Corrective Action Code CPU Status [CAN'T EXE. PRG.] The program file is incorrect. Or the contents of the file are not programs. Ensure that the program version is ***.QPG and QCPU ■Collateral information •...
Page 961 • Common information:- same error is displayed again, the CPU module • Individual information:- or display unit is faulty. (Please consult your ■Diagnostic Timing local Mitsubishi representative, explaining a • Always detailed description of the problem.) [DISPLAY ERROR] RUN: A failure was detected in the display unit.
Page 962: Error Code List (3000 To 3999)
• If the same error occurs, the cause is a The parameter setting in the individual information hardware failure. (Please consult your local of the error (SD16) is invalid. Mitsubishi representative, explaining a detailed ■Collateral information • Common information: File name/Drive name description of the problem.) QCPU •...
Page 963 CPU module, standard • Individual information: Parameter number RAM, or SD memory card. (Please consult your ■Diagnostic Timing local Mitsubishi representative, explaining a • At power-on/At reset/STOP→RUN/At writing to detailed description of the problem.) programmable controller [PARAMETER ERROR] The parameter settings are corrupted.
Page 964 • Individual information: Parameter number program memory of the CPU module or ■Diagnostic Timing memory card. (Please consult your local • At power-on/At reset/STOP→RUN/At writing to Mitsubishi representative, explaining a detailed programmable controller QCPU description of the problem.) LCPU [PARAMETER ERROR] The parameter file is incorrect.
Page 965 Error LED Status Corresponding Error Contents and Cause Corrective Action Code CPU Status [PARAMETER ERROR] The parameter-set number of CPU modules differs The number of CPU modules in the multiple CPU from the actual number in a multiple CPU system. ■Collateral information system must be the same as the value derived as Qn(H)
Page 966 CPU module. ■Collateral information 3041 If the same error occurs, the cause is a hardware • Common information:- failure. (Please consult your local Mitsubishi • Individual information:- representative, explaining a detailed description ■Diagnostic Timing of the problem.) •...
Page 967 CPU module. If the same error occurs, the cause is a hardware failure. (Please consult your local [PARAMETER ERROR] Mitsubishi representative, explaining a detailed RUN: The system file that have stored the remote description of the problem.) password setting information is damaged.
Page 968 • Individual information: Parameter number If an error occurs even after taking the above ■Diagnostic Timing measures, the cause is a hardware failure. • At power-on/At reset/STOP→RUN (Please consult your local Mitsubishi representative, explaining a detailed description Qn(H) of the problem.) QnPH •...
Page 969 If an error occurs even after taking the above • The mode switch of MELSECNET/H module measures, the cause is a hardware failure. is outside the range. (Please consult your local Mitsubishi ■Collateral information representative, explaining a detailed description • Common information: File name/Drive name of the problem.)
Page 970 If the error occurs after the above checks, the • Common information: File name/Drive name cause is a hardware fault. (Please consult your • Individual information: Parameter number local Mitsubishi representative, explaining a ■Diagnostic Timing detailed description of the problem.) • At power-on/At reset/STOP→RUN [LINK PARA.
Page 971 • If the error occurs after correction, it suggests a [LINK PARA. ERROR] hardware fault. (Please consult your local • The network module detected a network Mitsubishi representative, explaining a detailed parameter error. description of the problem.) • A MELSECNET/H network parameter error was detected.
Page 972 ERR.: QnPRH the Ethernet module is mounted on the main hardware fault. (Please consult your local Flicker base unit. Mitsubishi representative, explaining a detailed ■Collateral information description of the problem.) CPU Status: • Common information: File name/Drive name Stop • Individual information: Parameter number ■Diagnostic Timing...
Page 973 Network Parameter 3105 hardware fault. (Please consult your local dialog box does not correspond to the system. Mitsubishi representative, explaining the L26CPU-BT • The station type specified in the Network detailed description of the problem.) Parameter dialog box for CC-Link does not correspond to the system.
Page 974 Error LED Status Corresponding Error Contents and Cause Corrective Action Code CPU Status [LINK PARA. ERROR] • The CC-Link parameter setting is incorrect. • The set mode is not allowed for the version of the mounted CC-Link module. QCPU 3107 ■Collateral information Check the parameter setting.
Page 975 Error LED Status Corresponding Error Contents and Cause Corrective Action Code CPU Status [SP. PARA ERROR] • The refresh setting of the intelligent function module exceeded the file register capacity. Q00J/Q00/Q01 • The intelligent function module set in GX Configurator differs from the actually mounted •...
Page 976 Error LED Status Corresponding Error Contents and Cause Corrective Action Code CPU Status [REMOTE PASS. ERR.] The head I/O number of the target module of the Qn(H) remote password is set to other than 0 to 0FF0 QnPH Change the head I/O number of the target module ■Collateral information QnPRH to be within the 0...
Page 977 Error LED Status Corresponding Error Contents and Cause Corrective Action Code CPU Status [REMOTE PASS. ERR.] Any of the following modules is not mounted on the slot specified for the head I/O number of the Mount the following modules according to the remote password.
Page 978: Error Code List (4000 To 4999)
12.1.6 Error code list (4000 to 4999) The following shows the error messages from the error code 4000 to 4999, the contents and causes of the errors, and the corrective actions for the errors. Error LED Status Corresponding Code Error Contents and Cause Corrective Action CPU Status (SD0)
Page 979 Error LED Status Corresponding Code Error Contents and Cause Corrective Action CPU Status (SD0) [MISSING END INS.] There is no END (FEND) instruction in the program. ■Collateral information QCPU 4010 • Common information: Program error location LCPU • Individual information:- ■Diagnostic Timing •...
Page 980 QnPRH ■Collateral information hardware failure of the ATA card or SD memory 4100 • Common information: Program error location card. (Please consult your local Mitsubishi • Individual information:- representative, explaining a detailed LCPU ■Diagnostic Timing description of the problem.) •...
Page 981 Error LED Status Corresponding Code Error Contents and Cause Corrective Action CPU Status (SD0) [OPERATION ERROR] • The block data that crosses over the boundary between the internal user device and the extended data register (D) or extended link Read common information of the error using the register is specified (including 32-bit binary, real programming tool to identify the numeric value number (single precision, double precision),...
Page 982 Error LED Status Corresponding Code Error Contents and Cause Corrective Action CPU Status (SD0) RUN: [OPERATION ERROR] Off/On Q00/Q01 33 or more multiple CPU dedicated instructions ERR.: Using the multiple CPU dedicated instruction were executed from one CPU module. Qn(H) Flicker/On ■Collateral information completion bit, provide interlocks to prevent one...
Page 983 Error LED Status Corresponding Code Error Contents and Cause Corrective Action CPU Status (SD0) [OPERATION ERROR] Since the manual system switching enable flag (SM1592) is off, a manual system switching cannot be executed by the control system switching To execute control system switching by the SP. instruction (SP.
Page 984 Error LED Status Corresponding Code Error Contents and Cause Corrective Action CPU Status (SD0) [FOR-NEXT ERROR] The NEXT instruction was not executed although a FOR instruction has been executed. Alternatively, there are fewer NEXT instructions than FOR instructions. 4200 ■Collateral information •...
Page 985 Error LED Status Corresponding Code Error Contents and Cause Corrective Action CPU Status (SD0) [CAN'T EXECUTE(P)] More than 16 nesting levels are programmed. ■Collateral information • Common information: Program error location 4213 Keep nesting levels at 16 or under. • Individual information:- ■Diagnostic Timing •...
Page 986 Error LED Status Corresponding Code Error Contents and Cause Corrective Action CPU Status (SD0) [INST. FORMAT ERR.] The number of IX and IXEND instructions is not equal. ■Collateral information 4231 QCPU • Common information: Program error location • Individual information:- RUN: ■Diagnostic Timing Read common information of the error using the...
Page 987 Error LED Status Corresponding Code Error Contents and Cause Corrective Action CPU Status (SD0) [MULTI-COM. ERROR] The device which cannot be used for the multiple CPU high-speed transmission dedicated instruction specified by the program is specified. 4353 ■Collateral information • Common information: Program error location •...
Page 988 Error LED Status Corresponding Code Error Contents and Cause Corrective Action CPU Status (SD0) [CAN'T SET(S)] Total number of steps in all the SFC programs exceeded the maximum value. ■Collateral information 4421 • Common information: Program error location RUN: • Individual information:- Q00J/Q00/Q01 ■Diagnostic Timing Qn(H)
Page 989 Error LED Status Corresponding Code Error Contents and Cause Corrective Action CPU Status (SD0) [SFCP. FORMAT ERR.] The numbers of BLOCK and BEND instructions in an SFC program are not equal. ■Collateral information 4500 • Common information: Program error location •...
Page 990 Error LED Status Corresponding Code Error Contents and Cause Corrective Action CPU Status (SD0) [SFCP. FORMAT ERR.] RUN: The structure of the SFC program is illegal. • In a reset step, the host step number was specified as the destination step. ERR.: Q00J/Q00/Q01 4506...
Page 991 Error LED Status Corresponding Code Error Contents and Cause Corrective Action CPU Status (SD0) [BLOCK EXE. ERROR] Startup was executed at a block in the SFC Read common information of the error using the program that was already started up. programming tool to identify the numeric value Qn(H) ■Collateral information...
Page 992: Error Code List (5000 To 5999)
• Common information: Time (value set) tracking cable or CPU module. (Please consult • Individual information: Time (value actually RUN: your local Mitsubishi representative, explaining a measured) detailed description of the problem.) ■Diagnostic Timing ERR.: •...
Page 993 Error LED Status Corresponding Error Contents and Cause Corrective Action Code CPU Status [PRG. TIME OVER] • The program scan time exceeded the constant scan time specified in the PLC RAS tab of the Qn(H) PLC Parameter dialog box. QnPH ■Collateral information QnPRH •...
Page 994: Error Code List (6000 To 6999)
12.1.8 Error code list (6000 to 6999) The following shows the error messages from the error code 6000 to 6999, the contents and causes of the errors, and the corrective actions for the errors. Error LED Status Corresponding Error Contents and Cause Corrective Action Code CPU Status...
Page 995 Error LED Status Corresponding Error Contents and Cause Corrective Action Code CPU Status [OPE. MODE DIFF.] At power-on/reset, the RUN/STOP switch settings of the control system and standby system are not the same in a redundant system. (This can be detected from the control system or Set the RUN/STOP switches of the control system 6020 standby system of the redundant system.)
Page 996 (Please consult your ERR.: • The error occurred at a startup since the 6100 local Mitsubishi representative, explaining a redundant system startup procedure was not detailed description of the problem.) followed. • Confirm the redundant system startup CPU Status: ■Collateral information...
Page 997 • A data error (other than sum value error) or tracking cable is faulty. (Please consult your ERR.: occurred in tracking (data reception). local Mitsubishi representative, explaining a QnPRH • (This error may be caused by tracking cable detailed description of the problem.) removal or other system power-off (including •...
Page 998 CPU module • Common information: Tracking transmission or tracking cable is faulty. (Please consult your data classification local Mitsubishi representative, explaining a • Individual information:- detailed description of the problem.) ■Diagnostic Timing • Confirm the redundant system startup •...
Page 999 6120 transmission hardware is faulty. Flicker cable. (Please consult your local Mitsubishi (This can be detected from the control system or representative, explaining a detailed description of CPU Status: standby system of the redundant system.) the problem.)
Page 1000 Error LED Status Corresponding Error Contents and Cause Corrective Action Code CPU Status [STANDBY] The control system has been switched to the standby system in a redundant system. (Detected by the CPU that was switched from the control system to the standby system.) Since this error code does not indicate the error RUN: information of the CPU module but indicates its...
Page 1001 • Replace the tracking cable. If the same error still RUN: system. occurs, this indicates the CPU module is faulty. • The error occurred at a startup since the (Please consult your local Mitsubishi ERR.: redundant system startup procedure was not representative, explaining a detailed description Flicker QnPRH followed.
Page 1002: Error Code List (7000 To 10000)
Flicker module in a multiple CPU system during initial hardware fault of any of the CPU modules. communication. (Please consult your local Mitsubishi CPU Status: • In a multiple CPU system, a CPU module representative, explaining a detailed description Stop...
Page 1003 CPU module • Individual information:- hardware is faulty. (Please consult your local ■Diagnostic Timing Mitsubishi representative, explaining a detailed • Always description of the problem.) [MULTI EXE. ERROR] • In a multiple CPU system, a faulty CPU module was mounted.
Page 1004 Error LED Status Corresponding Error Contents and Cause Corrective Action Code CPU Status [MULTI EXE. ERROR] Either of the following settings was made in a multiple CPU system. • Multiple CPU automatic refresh setting was made for the inapplicable CPU module. •...
Page 1005 If the same error code is displayed again, the • Individual information: File diagnostic LCPU cause is a hardware failure of the CPU module. information (Please consult your local Mitsubishi ■Diagnostic Timing representative, explaining a detailed description of • At power-on/At reset/STOP→RUN/At writing to the problem.)
Page 1006 Error LED Status Corresponding Error Contents and Cause Corrective Action Code CPU Status [<CHK>ERR ***-***] RUN: Error detected by the CHK instruction. (The "***" portion of the error message indicates ERR.: Read the individual information of the error using the numbers of contact and coil that have been Qn(H) detected.) the programming tool to identify the numeric value...

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Mitsubishi MELSEC Q Series Programming Manual

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