Page 3: Safety Precautions
SAFETY PRECAUTIONS (Always read these instructions before using this equipment.) Before using this product, please read this manual and the relevant manuals introduced in this manual carefully and pay full attention to safety to handle the product correctly. In this manual, the safety instructions are ranked as "DANGER" and "CAUTION". Indicates that incorrect handling may cause hazardous conditions, DANGER resulting in death or severe injury.
Page 4 [Design Precautions] DANGER Install a safety circuit external to the programmable controller that keeps the entire system safe even when there are problems with the external power supply or the programmable controller module. Otherwise, trouble could result from erroneous output or erroneous operation. (1) Outside the programmable controller, construct mechanical damage preventing interlock circuits such as emergency stop, protective circuits, positioning upper and lower limits switches and interlocking forward/reverse operations.
Page 5 [Design Precautions] DANGER When overcurrent which exceeds the rating or caused by short-circuited load flows in the output module for a long time, it may cause smoke or fire. To prevent this, configure an external safety circuit, such as fuse. Build a circuit that turns on the external power supply when the programmable controller main module power is powered on.
Page 6 [Installation Precautions] CAUTION Use the programmable controller in an environment that meets the general specifications contained in QCPU User’s Manual (Hardware Design, Maintenance and Inspection). Using this programmable controller in an environment outside the range of the general specifications could result in electric shock, fire, erroneous operation, and damage to or deterioration of the product.
Page 7 [Wiring Precautions] DANGER Completely turn off the externally supplied power used in the system when installing or placing wiring. Not completely turning off all power could result in electric shock or damage to the product. When turning on the power supply or operating the module after installation or wiring work, be sure that the module's terminal covers are correctly attached.
Page 8 DANGER Be sure to ground the FG terminals and LG terminals to the protective ground conductor. Not doing so could result in electric shock or erroneous operation. When wiring in the programmable controller, be sure that it is done correctly by checking the product's rated voltage and the terminal layout.
Page 9 [Startup and Maintenance Precautions] DANGER Do not touch the terminals while power is on. Doing so could cause shock or erroneous operation. Correctly connect the battery. Also, do not charge, disassemble, heat, place in fire, short circuit, or solder the battery. Mishandling of battery can cause overheating or cracks which could result in injury and fires.
Page 10 [Startup and Maintenance Precautions] CAUTION The online operations conducted for the CPU module being operated, connecting the peripheral device (especially, when changing data or operation status), shall be conducted after the manual has been carefully read and a sufficient check of safety has been conducted. Operation mistakes could cause damage or problems with of the module.
Page 11 [Disposal Precautions] CAUTION When disposing of this product, treat it as industrial waste. [Transportation Precautions] CAUTION When transporting lithium batteries, make sure to treat them based on the transport regulations. (Refer to Appendix 1 for details of the controlled models.)
Page 12: Revisions
This manual confers no industrial property rights or any rights of any other kind, nor does it confer any patent licenses. Mitsubishi Electric Corporation cannot be held responsible for any problems involving industrial property rights which may occur as a result of using the contents noted in this manual.
Page 13: Table Of Contents
INTRODUCTION Thank you for choosing the Mitsubishi MELSEC-Q Series of General Purpose Programmable Controllers. Before using the equipment, please read this manual carefully to develop full familiarity with the functions and performance of the Q series programmable controller you have purchased, so as to ensure correct use.
Page 14 Access Range of CPU Module and Other Modules •••••••••••••••••••••••••••••••••••••••••••••••••••••••• 3 - 22 3.4.1 Access range with controlled module ••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••• 3 - 22 3.4.2 Access range with non-controlled module•••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••• 3 - 22 Access target under GOT connection••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••• 3 - 29 Access with instruction using link direct device ••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••• 3 - 29 Access range of GX Developer ••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••...
Page 15 CHAPTER7 PRECAUTIONS FOR USING AnS/A SERIES-COMPATIBLE MODULES 7 - 1 to 7 - 4 Precautions for use of AnS/A series compatible module•••••••••••••••••••••••••••••••••••••••••••••••••••• 7 - 1 CHAPTER8 STARTING UP THE MULTIPLE CPU SYSTEM 8 - 1 to 8 - 39 Flow-chart for Starting Up the Multiple CPU System •••••••••••••••••••••••••••••••••••••••••••••••••••••••• 8 - 1 Setting Up the Multiple CPU System Parameters ••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••...
Page 16: About Manuals
ABOUT MANUALS The following manuals are also related to this product. In necessary, order them by quoting the details in the tables below. Related Manuals (1) Common to CPU modules The following table indicates the related manuals common to the Basic model QCPU, High Performance model QCPU, Process CPU and Universal model QCPU.
Page 17 (3) High Performance model QCPU The following table indicates the related manuals of the High Performance model QCPU other than the manuals indicated in "(1) Common to CPU modules". Manual Number Manual Name (Model Code) QCPU (Q Mode)/QnACPU Programming Manual (PID Control Instructions) SH-080040 This manual describes the dedicated instructions used to exercise PID control.
Page 18: How To See This Manual
HOW TO SEE THIS MANUAL CPU modules requiring precautions Chapter heading Reference destination The CPU modules requiring precautions are A reference destination or The index on the right side of the page shown as icons. reference manual is marked shows the chapter of the open page at a "Note "...
Page 19 In addition, this manual provides the following explanations. POINT Explains the matters to be especially noted, the functions and others related to the description on that page. Remark Provides the reference destination related to the description on that page and the convenient information.
Page 20: How To Use This Manual
This manual is designed for users to understand the multiple CPU system including information of the system configuration, functions, and communication with external devices that are required when the MELSEC-Q series programmable controller is used in the multiple CPU system.
Page 21: Generic Terms And Abbreviations
Other name for compact types of Mitsubishi MELSEC-A series Programmable AnS series Controller. A series Other name for Large types of Mitsubishi MELSEC-A series Programmable Controller. Product name for Q series compatible SW D5C-GPPW-E type GPP function software package. GX Developer indicates the version.
Page 22 Generic Term/Abbreviation Description Other name for Q68RB redundant power supply base unit on which Q series I/O modules, intelligent function module, and redundant power supply module can be Q6 RB mounted. Generic term for QA1S65B and QA1S68B extension base units with AnS Series power QA1S6 B supply module, I/O module, and special function module can be mounted.
Page 23 Generic term for Q172LX, Q172EX, Q173PX, Q172DLX, Q172DEX, and Q172DPX Motion module modules dedicated to Mitsubishi motion controllers. Generic term for Mitsubishi graphic operation terminal, GOT-A*** series and GOT-F*** series. Single CPU system System in which a QCPU (including Q00JCPU) is installed in CPU slot for control.
Page 24: Chapter1 Outline
OUTLINE CHAPTER1 OUTLINE This manual describes the system configuration and the functions for use of the Q series CPU module ( (1) below) in the multiple CPU system. Refer to the manual below for the power supply module, base unit, extension cable, memory card and battery.
Page 25 OUTLINE (2) List of Q Series CPU Module manuals The Q series CPU module manuals are as shown below. For details such as manual numbers, refer to "About Manuals" in this manual. (a) Basic model QCPU Table1.2 List of user's manuals of Basic model QCPU Multi CPU Redundant Maintenance...
Page 26 OUTLINE Table1.3 List of programming manuals of Basic model QCPU PID Control Common Structured Process Control MELSAP-L Instruction Instructions Instructions Text QCPU (Q mode)/ QCPU (Q mode)/ QnPHCPU/ QnACPU QnACPU QnPRHCPU QCPU (Q mode)/ QCPU (Q mode) QCPU (Q mode) Programming Programming Programming...
Page 27 OUTLINE (b) High Performance Model QCPU Table1.4 List of user's manuals of High Performance model QCPU Multi CPU Redundant Maintenance Program and Inspection Fundamentals System System QCPU User's Manual QCPU User's Manual QnPRHCPU User's (Hardware Design, QCPU User's Manual Purpose (Function Explanation, Manual (Redundant Maintenance and...
Page 28 OUTLINE Table1.5 List of programming manuals of High Performance model QCPU PID Control Common Structured Process Control MELSAP-L Instruction Instructions Instructions Text QCPU (Q mode)/ QCPU (Q mode)/ QnPHCPU/ QnACPU QnACPU QnPRHCPU QCPU (Q mode)/ QCPU (Q mode) QCPU (Q mode) Programming Programming Programming...
Page 29 OUTLINE (c) Process CPU Table1.6 List of user's manuals of Process CPU Multi CPU Redundant Maintenance Program and Inspection Fundamentals System System QCPU User's Manual QCPU User's Manual QnPRHCPU User's (Hardware Design, QCPU User's Manual Purpose (Function Explanation, Manual (Redundant Maintenance and (Multiple CPU System) Program Fundamentals)
Page 30 OUTLINE Table1.7 List of programming manuals of Process CPU PID Control Common Structured Process Control MELSAP-L Instruction Instructions Instructions Text QCPU (Q mode)/ QCPU (Q mode)/ QnPHCPU/ QnACPU QnACPU QnPRHCPU QCPU (Q mode)/ QCPU (Q mode) QCPU (Q mode) Programming Programming Programming QnACPU...
Page 31 OUTLINE (d) Universal Model QCPU Table1.8 List of user's manuals of Universal model QCPU Multi CPU Redundant Maintenance Program and Inspection Fundamentals System System QCPU User's Manual QCPU User's Manual QnPRHCPU User's (Hardware Design, QCPU User's Manual Purpose (Function Explanation, Manual (Redundant Maintenance and (Multiple CPU System)
Page 32 OUTLINE Table1.9 List of programming manuals of Universal model QCPU PID Control Common Structured Process Control MELSAP-L Instruction Instructions Instructions Text QCPU (Q mode)/ QCPU (Q mode)/ QnPHCPU/ QnACPU QnACPU QnPRHCPU QCPU (Q mode)/ QCPU (Q mode) QCPU (Q mode) Programming Programming Programming...
Page 33: What Is Multiple Cpu System
OUTLINE 1.1 What is multiple CPU system? (1) Configuration of multiple CPU system A multiple CPU system is a system in which more than one CPU module are mounted on several a main base unit in order to control the I/O modules and intelligent function modules.
Page 34 OUTLINE (2) Available CPU modules in multiple CPU system Note1.1 Table1.10 shows the available CPU modules in multiple CPU system. Note1 Refer to Section 2.3 for the compatible version of each module.Note2Note3 Redundant Table1.10 Applicable CPU modules Note1.1 CPU module Model Basic Note1.2...
Page 35 OUTLINE (3) Method for controlling I/O module and intelligent function module It is necessary to set (control CPU setup) which CPU modules are to control which I/O modules and intelligent function modules with a multiple CPU system. Slot number Control CPU setting Control with CPU module 1.
Page 36 OUTLINE (4) Multiple CPU system setting For control in the multiple CPU system, it is necessary to set up the "Number of mounted CPU modules" and the "Control CPU" with PLC parameter for all CPU modules mounted on the main base unit. QCPU User's Manual (Function Explanation, Program Fundamentals) (5) Access range of multiple CPU system In the multiple CPU system, the access ranges are different between the controlled...
Page 37 OUTLINE (c) Range of access to other station's CPU module To access to a CPU module on other station from GX Developer, access can be made through a network module controlled by any CPU module in the multiple CPU system. When other station has multiple CPUs, specifying the CPU No.
Page 38: Features Of Multiple Cpu System
OUTLINE 1.2 Features of multiple CPU system (1) Multi-control system (a) Configuration optimum for system Since each system uses not only one QCPU but any combinations of the QCPU, Motion CPU, and PC CPU module according to the system, the development efficiency and ease of maintenance of the system can be enhanced.
Page 39 OUTLINE Interaction with a motion controller for motion control is enhanced in the Universal model QCPU. (a) Speeding up data transfer between multiple CPUs Maximum 14 k word-data and a sequence program can be transferred between multiple CPUs with parallel processing. It enables high-speed data transfer independent of scan time, which leads to takt time shortening of equipment.
Page 40 OUTLINE (b) Enabling synchronous processing with a motion control An interrupt program which is synchronized with the operation cycle of a motion controller (multiple CPU synchronous interrupt program) can be executed. Command I/O from a motion controller can be synchronized with the operation cycle of the motion controller, which enables high-speed data transfer independent of scan time.
Page 41 OUTLINE (c) Timing of data send/receive between the CPU modules can be checked The sampling trace function of the Universal model QCPU enables to check the data send/receive timing with the Motion controller. (Timing of data send/receive can be checked between the Universal model QCPUs.) Using the sampling trace function facilitates to check the data send/receive timing between CPU modules, and reduces the debug time of the multiple CPU system.
Page 42 OUTLINE (3) System configuration based on load distribution. (a) Distribution of processing By distributing the high-load processing performed on a single QCPU over several CPU modules, it is possible to reduce the overall system scan time. (Control in 1ms or less) (Control in several to several dozen ms) Data processing (low speed) CPU module for machine control...
Page 43 OUTLINE (5) Communication between CPU modules in the multiple CPU system The following data transfer can be made between CPU modules in the multiple CPU system. (a) Data transfer between CPU modules The following data transfer can be made between CPU modules in the multiple CPU system.
Page 44: Difference From Single Cpu System
OUTLINE 1.3 Difference from Single CPU System Differences between the single CPU system and the multiple CPU system are described in this section. Refer to the manuals below for the single CPU system. QCPU User's Manual (Hardware Design, Maintenance and Inspection) QCPU User's Manual (Function Explanation, Program Fundamentals) (1) When using the Basic model QCPU Table1.11 Difference from single CPU system...
Page 45 OUTLINE Table1.11 Difference from single CPU system (continued) Item Single CPU system Multiple CPU system Reference The number of mountable modules The number of mountable modules per QCPU Restrictions on number of Concept per CPU module is restricted and per system is restricted depending on the Section 2.4 mountable modules depending on the module type.
Page 46 OUTLINE (2) When using the High Performance model QCPU Table1.12 Difference from single CPU system Item Single CPU system Multiple CPU system Reference Maximum number of extension 7 stages stages Maximum number of mountable *1,*2 65 - (No. of CPUs) I/O modules Q3 B, Q3 SB, Q3 RB, Q3 DB Main base unit model...
Page 47 OUTLINE Table1.12 Difference from single CPU system (continued) Item Single CPU system Multiple CPU system Reference Setting the relations between the CPU Access from CPU module to All modules can be controlled. module and other modules with the PLC Section 3.4 other modules parameter (control CPU) is required.
Page 48 OUTLINE Table1.12 Difference from single CPU system (continued) Single CPU system Multiple CPU system Reference 1) No. of CPU modules (Multiple CPU setting) 2) Control CPU (detailed I/O assignment setting) 3) Out-of-group I/O setting (Multiple CPU setting) Parameters added for multiple 4) Operation mode for CPU error stop Parameter ----...
Page 49 OUTLINE (3) When using the Process CPU Table1.13 Difference from single CPU system Item Single CPU system Multiple CPU system Reference Maximum number of extension 7 stages stages Maximum number of mountable 65 - (No. of CPUs) I/O modules Main base unit model Q3 B, Q3 RB, Q3 DB System Section 2.1.2...
Page 50 OUTLINE Table1.13 Difference from single CPU system (continued) Item Single CPU system Multiple CPU system Reference Setting the relations between the CPU Access from CPU module to All modules can be controlled. module and other modules with the PLC Section 3.4 other modules parameter (control CPU) is required.
Page 51 OUTLINE (4) When using the Universal model QCPU Table1.14 Difference from single CPU system Item Single CPU system Multiple CPU system Reference Maximum number of extension 7 stages (when the Q02UCPU is used:4 stages) stages 65 - (No. of CPUs) (when the Q02UCPU is Maximum number of mountable *1,*2 I/O modules...
Page 52 OUTLINE Table1.14 Difference from single CPU system (continued) Item Single CPU system Multiple CPU system Reference Setting the relations between the CPU Access from CPU module to All modules can be controlled. module and other modules with the PLC Section 3.4 other modules parameter (control CPU) is required.
Page 53 OUTLINE Table1.14 Difference from single CPU system (continued) Item Single CPU system Multiple CPU system Reference Transmission from each CPU module is up to Communication using QCPU ---- 2k words in total of four ranges. The total for Section 4.1.2 standard area by auto refresh all CPU modules is 8k words.
Page 54: Chapter2 System Configuration
SYSTEM CONFIGURATION CHAPTER2 SYSTEM CONFIGURATION This chapter explains the system configuration of Multiple CPU Systems, and the precautions for Multiple CPU System configuration. 2.1 System configuration 2.1.1 System configuration using Basic model QCPU (Q00CPU, Q01CPU) This following explains the system configuration using the Basic model QCPU. (1) System using the main base unit (Q3 B) (a) System configuration Battery for...
Page 55 SYSTEM CONFIGURATION POINT (1) The Q00JCPU is not available for the multiple CPU system. (2) When the multiple CPU system is configured using the Basic model QCPU as the CPU No.1, only the following CPU modules can be used as the CPUs No.2 and 3.
Page 56 SYSTEM CONFIGURATION (b) Outline of system configuration Main base unit..32-point modules are mounted on each slot. Q38B (8 slots occupied) ..Slot number ..I/O number Empty space of 16 points Q series power CPU module 3 supply module CPU module 2 CPU module 1 Extension base unit ..32-point modules are mounted on each slot.
Page 57 SYSTEM CONFIGURATION Table2.1 Restrictions on system configuration, available base units, extension cables, and power supply modules CPU1: CPU No. 1 (Basic model QCPU), CPU2: CPU No. 2 (Motion CPU), CPU number CPU3: CPU No.3 (PC CPU module/C Controller module) Maximum number of 4 extension units extension stages Maximum number of...
Page 58 SYSTEM CONFIGURATION (2) When using the slim type main base unit (Q3 SB) (a) System configuration Battery for QCPU (Q6BAT) Basic model C Controller QCPU module Slim type main base unit * Slim type power supply/input/output/intelligent function module * 1: The slim type main base unit does not have an extension cable connector. The extension base unit and GOT cannot be bus-connected.
Page 59 SYSTEM CONFIGURATION (b) Outline of system configuration Slim type main base unit 32-point modules are mounted on each slot. Q35SB (5 slots occupied) Slot number PULL I/O number Slim type power supply CPU module 2 module CPU module 1 Diagram 2.4 System configuration example for using Q3 Table2.2 Restrictions on system configuration, available base units, extension cables, and power supply modules CPU number CPU1: CPU No.
Page 60 SYSTEM CONFIGURATION (3) When using the Multiple CPU High speed main base unit (Q3 DB) (a) System configuration Battery for QCPU (Q6BAT) PC CPU Basic model C Controller module * QCPU module * DB type multiple CPU high speed main base unit * Extension cable Q series power supply/input/output/intelligent...
Page 61 SYSTEM CONFIGURATION POINT (1) The Q00JCPU is not available for the multiple CPU system. (2) When the multiple CPU system is configured using the Basic model QCPU as the CPU No.1, only the following CPU modules can be used as the CPUs No.2.
Page 62 SYSTEM CONFIGURATION (b) Outline of system configuration Main base unit..32-point modules are mounted on each slot. Q38DB (8 slots occupied) ..Slot number ..I/O number Q series power Empty space of 16 points supply module CPU module 2 * CPU module 1 Extension base unit ..32-point modules are mounted on each slot.
Page 63 SYSTEM CONFIGURATION Table2.3 Restrictions on system configuration, available base units, extension cables, and power supply modules CPU number CPU1: CPU No. 1 (Basic model QCPU), CPU2: CPU No. 2 (PC CPU module C Controller module) Maximum number of 4 extension units extension stages Maximum number of mountable I/O...
Page 64: System Configuration Using High Performance Model Qcpu Or Process Cpu As Cpu
SYSTEM CONFIGURATION 2.1.2 System configuration using High Performance model QCPU or Process CPU as CPU No.1 This following explains the system configuration using the High Performance model QCPU and the Process CPU as the CPU No.1. (1) When using the main base unit (Q3 B) (a) System configuration Memory card * High Performance...
Page 65 SYSTEM CONFIGURATION * 1: Only one memory card can be mounted. Select an appropriate memory card from the SRAM, Flash and ATA in accordance with application and capacity. When a commercial memory card is used, the operation is not guaranteed. * 2: Use the Q series power supply module for the power supply module.
Page 66 SYSTEM CONFIGURATION (b) Outline of system configuration Main base unit..32-point modules are mounted on each slot. Q312B (12 slots occupied) ..Slot number ..I/O number Q series power CPU module 4 CPU module 3 supply module CPU module 2 CPU module 1 Extension base unit ..32-point modules are mounted on each slot.
Page 67 SYSTEM CONFIGURATION Table2.4 Restrictions on system configuration, available base units, extension cables, and power supply modules CPU number CPU module1: CPU No.1, CPU module 2: CPU No.2, CPU module 3: CPU No.3, CPU module 4: CPU No.4 Maximum number of 7 extension stages extension stages Maximum number of...
Page 68 SYSTEM CONFIGURATION • "No. of CPUs" is the number of CPUs set by [No. of PLC] of GX Developer. • When mounting the Universal model QCPU (except the Q02UCPU) and the Motion CPU at the same time, use the Q172DCPU or Q173DCPU as the Motion CPU.
Page 69 SYSTEM CONFIGURATION (2) When using the redundant power main base unit (Q3 RB) (a) System configuration Memory card * High Performance model QCPU Process CPU Battery for QCPU (Q6BAT) Universal model Q7BAT-SET QCPU RB type redundant power main base unit * Battery holder Battery for QCPU (Q7BAT) Q8BAT-SET...
Page 70 SYSTEM CONFIGURATION POINT (1) When the multiple CPU system is configured using the High Performance model QCPU or the Process CPU as the CPU No.1, only the following modules can be used as the CPUs No.2 to CPU No.4. • High Performance model QCPU •...
Page 71 SYSTEM CONFIGURATION (b) Outline of system configuration Redundant main base unit ..32-point module is mounted on each slot. Q38RB (8 slots occupied) ..Slot number ..I/O number CPU module 4 Redundant Power CPU module 3 supply module CPU module 2 CPU module 1 Extension base unit ..32-point modules are mounted on each slot.
Page 72 SYSTEM CONFIGURATION Table2.5 Restrictions on system configuration, available base units, extension cables, and power supply modules CPU number CPU module1: CPU No.1, CPU module 2: CPU No.2, CPU module 3: CPU No.3, CPU module 4: CPU No.4 Maximum number of 7 extension stages extension stages Maximum number of...
Page 73 SYSTEM CONFIGURATION (3) When using the slim type main base unit (Q3 SB) (a) System configuration Memory card * High Performance C Controller model QCPU module * Battery for QCPU (Q6BAT) Universal model Q7BAT-SET QCPU * Slim type main base unit * Battery holder Battery for QCPU (Q7BAT) Q8BAT-SET...
Page 74 SYSTEM CONFIGURATION POINT When the multiple CPU system is configured using the High Performance model QCPU as the CPU No.1, only the following CPU modules can be used as the CPUs No.2 and 3. • High Performance model QCPU • Universal model QCPU (except Q02UCPU) •...
Page 75 SYSTEM CONFIGURATION (4) When using the Multiple CPU high speed main base unit (Q3 DB) (a) System configuration Memory card * High Performance PC CPU module C Controller Battery for QCPU (Q6BAT) model QCPU module * Q7BAT-SET Process CPU Universal model QCPU* DB type multiple CPU high speed main Battery holder...
Page 76 SYSTEM CONFIGURATION POINT When the multiple CPU system is configured using the High Performance model QCPU or the Process CPU as the CPU No.1, only the following CPU modules can be used as the CPUs No.2 to No.4. • High Performance model QCPU •...
Page 77 SYSTEM CONFIGURATION (b) Outline of system configuration Main base unit..32-point modules are mounted on each slot. Q312DB (12 slots occupied) ..Slot number ..I/O number Q series power CPU module 4 CPU module 3 supply module CPU module 2 CPU module 1 Extension base unit ..32-point modules are mounted on each slot.
Page 78 SYSTEM CONFIGURATION Table2.7 Restrictions on system configuration, available base units, extension cables, and power supply modules CPU number CPU module1: CPU No.1, CPU module 2: CPU No.2, CPU module 3: CPU No.3, CPU module 4: CPU No.4 Maximum number of 7 extension stages extension stages Maximum number of...
Page 79 SYSTEM CONFIGURATION 2.1.3 System configuration using Universal model QCPU as CPU No.1 The following explains the system configuration using the Universal model QCPU as the CPU No.1. (1) When using the Multiple CPU High speed main base unit (Q3 DB) (a) System configuration Memory card * Motion...
Page 80 SYSTEM CONFIGURATION * 8: When the Q8BAT is used for the Universal model QCPU, use the connection cable whose connector part displays "A". For details of connector part of a connection cable, refer to the following manual. QCPU User's Manual (Hardware Design, Maintenance and Inspection) * 9: For further information on PC CPU module, consult CONTEC Co., Ltd Tel: +81-6-6472-7130) POINT (1) When the multiple CPU system is configured using Q02UCPU as the CPU...
Page 81 SYSTEM CONFIGURATION (b) Outline of system configuration Main base unit..32-point modules are mounted on each slot. Q312DB (12 slots occupied) ..Slot number ..I/O number Q series power CPU module 4 CPU module 3 supply module CPU module 2 CPU module 1 Extension base unit ..32-point modules are mounted on each slot.
Page 82 SYSTEM CONFIGURATION Table2.8 Restrictions on system configuration, available base units, extension cables, and power supply modules CPU number CPU module1: CPU No.1, CPU module 2: CPU No.2, CPU module 3: CPU No.3, CPU module 4: CPU No.4 Maximum number of 7 extension stages(when the Q02UCPU is used: 4 extension stages) extension stages Maximum number of...
Page 83 SYSTEM CONFIGURATION (2) When using the main base unit (Q3 B) (a) System configuration Memory card * High Performance Motion PC CPU C Controller Battery for QCPU (Q6BAT) model QCPU CPU* module * module * Q7BAT-SET Process CPU Universal model QCPU Battery holder Battery for QCPU (Q7BAT)
Page 84 SYSTEM CONFIGURATION POINT (1) When the multiple CPU system is configured using Q02UCPU as the CPU No.1, only the following CPU modules can be used as the CPUs No.2. • Motion CPU (Q172CPUN, Q173CPUN, Q172HCPU, and Q173HCPU) • PC CPU module (PPC-CPU852(MS)-512) •...
Page 85 SYSTEM CONFIGURATION (b) Outline of system configuration Main base unit..32-point modules are mounted on each slot. Q312B (12 slots occupied) ..Slot number ..I/O number Q series power CPU module 4 CPU module 3 supply module CPU module 2 CPU module 1 Extension base unit ..32-point modules are mounted on each slot.
Page 86 SYSTEM CONFIGURATION Table2.9 Restrictions on system configuration, available base units, extension cables, and power supply modules CPU number CPU module1: CPU No.1, CPU module 2: CPU No.2, CPU module 3: CPU No.3, CPU module 4: CPU No.4 Maximum number of 7 extension stages (when the Q02UCPU is used: 4 extension stages) extension stages Maximum number of...
Page 87 SYSTEM CONFIGURATION (3) When using the redundant power main base unit (Q3 RB) (a) System configuration Memory card * High Performance model QCPU Process CPU Battery for QCPU (Q6BAT) Universal model Q7BAT-SET QCPU RB type redundant power main base unit * Battery holder Battery for QCPU (Q7BAT) Q8BAT-SET...
Page 88 SYSTEM CONFIGURATION POINT (1) The Q02UCPU is not available for the multiple CPU system. (2) When the multiple CPU system is configured using the Universal model QCPU (except Q02UCPU) or the Process CPU as the CPU No.1, only the following modules can be used as the CPUs No.2 to CPU No.4. •...
Page 89 SYSTEM CONFIGURATION (b) Outline of system configuration Redundancy main base unit ..32-point module is mounted on each slot. Q38RB (8 slots occupied) ..Slot number ..I/O number CPU module 4 Redundant Power CPU module 3 supply module CPU module 2 CPU module 1 Extension base unit ..32-point modules are mounted on each slot.
Page 90 SYSTEM CONFIGURATION Table2.10 Restrictions on system configuration, available base units, extension cables, and power supply modules CPU number CPU module1: CPU No.1, CPU module 2: CPU No.2, CPU module 3: CPU No.3, CPU module 4: CPU No.4 Maximum number of 7 extension stages extension stages Maximum number of...
Page 91 SYSTEM CONFIGURATION (4) When using the slim type main base unit (Q3 SB) (a) System configuration Memory card * High Performance C Controller model QCPU module * Battery for QCPU (Q6BAT) Universal model Q7BAT-SET QCPU Slim type main base unit * Battery holder Battery for QCPU (Q7BAT) Q8BAT-SET...
Page 92 SYSTEM CONFIGURATION (b) Outline of system configuration Slim type main base unit ..32-point module is mounted on each slot. Q35SB(5 slots occupied) ..Slot number ..I/O number Slim type power CPU module 3 supply module CPU module 2 CPU module 1 Diagram 2.22 System configuration example on using Q3 SB Table2.11 Restrictions on system configuration, available base units, extension cables, and power supply modules CPU number...
Page 93: Configuration Of Peripheral Devices
SYSTEM CONFIGURATION 2.2 Configuration of peripheral devices This section describes the system configurations of peripheral devices that can be used with the Basic model QCPU, High Performance model QCPU, Process CPU and Universal model QCPU. (1) When using the Basic model QCPU Basic model QCPU PC (GX Developer, GX Configurator) RS-232 cable...
Page 94 SYSTEM CONFIGURATION (2) When using the High Performance model QCPU High Performance model QCPU Memory card * PC (GX Developer, GX Configurator) * RS-232 cable Memory card * PC card adapter USB cable * * 1: Do not format the ATA card by other than GX Developer. QCPU User's Manual (Hardware Design, Maintenance and Inspection) * 2: It is not used for the Q02CPU.
Page 95 SYSTEM CONFIGURATION (3) When using the Process CPU Process CPU Memory card * RS-232 cable PC(GX Developer, GX Configurator, PX Developer) * USB cable * Memory card * PC card adapter * 1: Do not format the ATA card by other than GX Developer. QCPU User's Manual (Hardware Design, Maintenance and Inspection) * 2: For writing into memory card by GX Developer and information on USB cables, refer to the operating manual of the GX Developer.
Page 96 SYSTEM CONFIGURATION (4) When using the Universal model QCPU (a) For the QnU(D)(H)CPU Universal model QCPU Memory card * RS-232 cable PC(GX Developer, GX Configurator) * USB cable * Memory card * PC card adapter * 1: Do not format the ATA card by other than GX Developer. QCPU User's Manual (Hardware Design, Maintenance and Inspection) * 2: For writing into memory card by GX Developer and information on USB cables, refer to the operating manual of the GX Developer.
Page 97 SYSTEM CONFIGURATION (b) For the QnUDE(H)CPU Universal model QCPU Memory card * Ethernet cable* PC(GX Developer, GX Configurator) * USB cable * Memory card * PC card adapter * 1: Do not format the ATA card by other than GX Developer. QCPU User's Manual (Hardware Design, Maintenance and Inspection) * 2: For writing into memory card by GX Developer and information on USB cables, refer to the operating manual of the GX Developer.
Page 98: Configurable Device And Available Software
SYSTEM CONFIGURATION 2.3 Configurable device and available software Information on devices and software packages used for the system configuration is described in this section. (1) CPU modules available for multiple CPU system There are some restrictions on the CPU module model and function version as shown in the table below.
Page 99 SYSTEM CONFIGURATION (b) When High Performance model QCPU is used as CPU No.1 Table2.13 Available CPU modules CPU module Model Restrictions High Performance model Q02CPU, Q02HCPU, Q06HCPU, Function version B Q12HCPU, Q25HCPU QCPU Q02PHCPU, Q06PHCPU, Process CPU No version restriction Q12PHCPU, Q25PHCPU Q03UDCPU, Q04UDHCPU, Q06UDHCPU, Q13UDHCPU,...
Page 100 SYSTEM CONFIGURATION (c) When Process CPU is used as CPU No.1 Table2.14 Available CPU modules CPU module Model Restrictions High Performance model Q02CPU, Q02HCPU, Q06HCPU, Function version B QCPU Q12HCPU, Q25HCPU Q02PHCPU, Q06PHCPU, Process CPU No version restriction Q12PHCPU, Q25PHCPU Q03UDCPU, Q04UDHCPU, Q06UDHCPU, Q13UDHCPU, Universal model QCPU...
Page 101 SYSTEM CONFIGURATION (d) When Universal model QCPU is used as CPU No.1 1) When the Q02UCPU is used Table2.15 Available CPU modules CPU module Model Restrictions Universal model QCPU Q02UCPU No version restriction Q172CPUN, Q173CPUN, Refer to the CPU module Motion CPU Q172HCPU, Q173HCPU manual.
Page 102 SYSTEM CONFIGURATION (2) Precautions when using Q Series I/O modules and intelligent function modules (a) Compatible I/O modules All I/O modules (QX , QY ) are compatible with the multiple CPU system. They can be used by setting any of CPU No.1 to No.4 as a control CPU. (b) Compatible intelligent function modules 1) The intelligent function modules compatible with the multiple CPU system are those of function version B or later.
Page 103 SYSTEM CONFIGURATION (3) Module replaceable online (a) I/O modules and intelligent function modules When a multiple CPU system includes a Process CPU, online module change is allowed. The modules controlled by the Process CPU can be changed online. The modules controlled by the High Performance model QCPU, Motion CPU, PC CPU module and Universal model QCPU cannot be changed online.
Page 104 SYSTEM CONFIGURATION (4) Applicable software (a) GX Developer and PX Developer Versions of the GX Developer and the PX Developer applicable in the multiple CPU system are shown in Table2.19. Table2.19 Applicable GX Developer and PX Developer Applicable software version QCPU GX Developer PX Developer...
Page 105 SYSTEM CONFIGURATION (b) Applicable GX Configurator Versions of GX Configurator applicable in the multiple CPU system are shown in Table2.20 Available GX Configurator versions vary depending on the intelligent function module used. For available GX Configurator versions, refer to the manual for the intelligent function module.
Page 106 SYSTEM CONFIGURATION Table2.20 Applicable GX Configurator (continued) Applicable software version QCPU Product name Version GX Configurator-AD Version 2.05F or later GX Configurator-DA Version 2.06G or later GX Configurator-SC Version 2.12N or later GX Configurator-CT Version 1.25AB or later GX Configurator-TI Version 1.24AA or later GX Configurator-TC Version 1.23Z or later...
Page 107: Precautions For System Configuration
SYSTEM CONFIGURATION 2.4 Precautions for system configuration Restrictions on the system configuration using the Q series CPU module are provided in this section. (1) Modules of restricted quantity The number of mountable modules and supported functions are restricted depending on the module type. For the number of modules that can be mounted for each Motion CPU or PC CPU module, refer to each CPU module manual.
Page 108 SYSTEM CONFIGURATION (b) When using the High Performance model QCPU, Process CPU Table2.22 Modules of restricted quantity Number of modules that can Product Model Quantity restriction per QCPU be mounted per system CC-Link IE controller network • QJ71GP21-SX Up to 2 Up to 2 •...
Page 109 SYSTEM CONFIGURATION (c) When using the Universal model QCPU Table2.23 Modules of restricted quantity Number of modules that can Product Model Quantity restriction per QCPU be mounted per system CC-Link IE controller network • QJ71GP21-SX • QJ71GP21S-SX module • QJ71LP21 •...
Page 110 SYSTEM CONFIGURATION (2) Modules that have restrictions on use of a Built-in Ethernet port QCPU Table2.24 lists the module that have restrictions on use of a Built-in Ethernet port QCPU. Table2.24 Modules that have restrictions on use of a Built-in Ethernet port QCPU Five digits of available Product name Model...
Page 111 SYSTEM CONFIGURATION (4) Precautions for using QCPU of function version A When the multiple CPU system has been configured using a QCPU of function version A, an error occurs and the multiple CPU system is not started. Errors shown in Table2.25 will occur and the multiple CPU system will not start up if function version A High Performance model QCPUs and High Performance model QCPU/Process CPU are used on a multiple CPU system.
Page 112: Chapter3 Concept For Multiple Cpu System
CONCEPT FOR MULTIPLE CPU SYSTEM CHAPTER3 CONCEPT FOR MULTIPLE CPU SYSTEM 3.1 Mounting Position of CPU Module For the configuration of the multiple CPU system, the combination of CPU modules shown in Table3.1 is available. Table3.1 Combination of CPU modules Number of CPU that can be mounted on CPU module No.2 or later Maximum Motion CPU...
Page 113: When Cpu No.1 Is Basic Model Qcpu
CONCEPT FOR MULTIPLE CPU SYSTEM 3.1.1 When CPU No.1 is Basic model QCPU The mounting position of each CPU module is shown in Table3.2. (1) Mounting position of Basic model QCPU Only one Basic model QCPU can be mounted on the CPU slot (slot on the right-hand side of the power supply module) of the main base unit.
Page 114 CONCEPT FOR MULTIPLE CPU SYSTEM (a) When mounting the Motion CPU • The PC CPU module can be mounted on slot 1 or 2. • The C Controller module can be mounted on slot 1 (b) When not mounting the Motion CPU •...
Page 115 CONCEPT FOR MULTIPLE CPU SYSTEM (c) When adding the C Controller module in the future. 1) When mounting the Motion CPU Set slot 1 as "PLC (Empty)." Slot number Slot number Added C Controller module Diagram 3.5 "PLC (Empty)" setting for addition of C Controller module 2) When not mounting Motion CPU Set slot 0 as "PLC (Empty)."...
Page 116 CONCEPT FOR MULTIPLE CPU SYSTEM Table3.2 Mounting position of CPU module : Slot number Mounting position of CPU module No. of CPUs ---- ---- * 1: No. of CPUs indicates the value set in the multiple CPU setting of the PLC parameter. * 2: The PC CPU module occupies 2 slots.
Page 117: When Cpu No.1 Is High Performance Model Qcpu Or Process Cpu
CONCEPT FOR MULTIPLE CPU SYSTEM 3.1.2 When CPU No.1 is High Performance model QCPU or Process CPU The mounting position of each CPU module is shown in Table3.3. (1) Mounting position of High Performance model QCPU or Process CPU Up to four modules of High Performance model QCPUs or Process CPUs can be mounted from the CPU slot (the slot on the right side of power supply module) to slot There must be no empty slot between CPU modules.
Page 118 CONCEPT FOR MULTIPLE CPU SYSTEM (5) Mounting position of the C Controller module Up to three C Controller modules can be mounted on slots 0 to 2 of the main base unit. Note that the any CPU module cannot be mounted on the right side of the C Controller module.
Page 119 CONCEPT FOR MULTIPLE CPU SYSTEM Table3.3 Mounting position of CPU module : Slot number Mounting position of CPU module No. of CPUs ---- ---- ---- * 1: The number of CPUs shows the value set by the multiple CPU setting. * 2: The PC CPU module occupies two slots.
Page 120 CONCEPT FOR MULTIPLE CPU SYSTEM Mounting position of CPU module No. of CPUs * 1: The number of CPUs shows the value set by the multiple CPU setting. * 2: The PC CPU module occupies two slots. * 3: The High Performance model QCPU and Process CPU can be mounted. * 4: The High Performance model QCPU, Process CPU, and Universal model QCPU (except Q02UCPU) can be mounted.
Page 121: When Cpu No.1 Is Universal Model Qcpu
CONCEPT FOR MULTIPLE CPU SYSTEM 3.1.3 When CPU No.1 is Universal model QCPU The mounting position of each CPU module is shown is Table3.4. (1) Mounting position of Universal model QCPU Only one Q02UCPU can be mounted on the CPU slot (the right side slot of the power supply module).
Page 122 CONCEPT FOR MULTIPLE CPU SYSTEM (6) "PLC (Empty)" setting An empty slot can be reserved for future addition of a CPU module. Select the number of CPU modules including empty slots at No. of PLC and set the type of the slots to be emptied to "PLC (Empty)" in the I/O assignment screen of PLC parameter.
Page 123 CONCEPT FOR MULTIPLE CPU SYSTEM Table3.4 Mounting position of CPU module(When the Q02UCPU is mounted on the CPU No.1) : Slot number Mounting position of CPU module No. of CPUs ---- ---- * 1: No. of CPUs indicates the value set in the multiple CPU setting of the PLC parameter. * 2: The Q02UCPU can be mounted.
Page 124 CONCEPT FOR MULTIPLE CPU SYSTEM Table3.5 Mounting position of CPU module(When except the Q02UCPU is mounted on the CPU No.1) : Slot number Mounting position of CPU module No. of CPUs ---- * 1: No. of CPUs indicates the value set in the multiple CPU setting of the PLC parameter. * 2: Universal model QCPU (except the Q02UCPU) can be mounted.
Page 125 CONCEPT FOR MULTIPLE CPU SYSTEM Mounting position of CPU module No. of CPUs ---- * 1: No. of CPUs indicates the value set in the multiple CPU setting of the PLC parameter. * 2: Universal model QCPU (except the Q02UCPU) can be mounted. * 3: Universal model QCPU (except the Q02UCPU) and Motion CPU (Q172UDCPU,Q173UDCPU) can be mounted.
Page 126 CONCEPT FOR MULTIPLE CPU SYSTEM Mounting position of CPU module No. of CPUs * 1: No. of CPUs indicates the value set in the multiple CPU setting of the PLC parameter. * 2: Universal model QCPU (except the Q02UCPU) can be mounted. * 3: Universal model QCPU (except the Q02UCPU) and Motion CPU (Q172UDCPU,Q173UDCPU) can be mounted.
Page 127 CONCEPT FOR MULTIPLE CPU SYSTEM Mounting position of CPU module No. of CPUs ---- * 1: No. of CPUs indicates the value set in the multiple CPU setting of the PLC parameter. * 2: Universal model QCPU (except the Q02UCPU) can be mounted. * 3: Universal model QCPU (except the Q02UCPU) and Motion CPU (Q172UDCPU,Q173UDCPU) can be mounted.
Page 128: Cpu No. Of Cpu Module
CONCEPT FOR MULTIPLE CPU SYSTEM 3.2 CPU No. of CPU module (a) CPU No. allocation CPU numbers are allocated for identifying the CPU modules mounted on the main base unit in the multiple CPU system. CPU No.1 is allocated to the CPU slot, and Basic CPU No.2, No.3 and No.4 are allocated to the right of the CPU No.1 in this order.
Page 129 CONCEPT FOR MULTIPLE CPU SYSTEM • Setting a control CPU in the I/O assignment. Control CPU (Control PLC) setting Diagram 3.17 Control CPU setting (b) Checking host CPU number The QCPU stores the host number in the special register (SD395). It is recommended to create a program for checking the host number on the QCPU.
Page 130: Concept Of I/O Number Assignment
CONCEPT FOR MULTIPLE CPU SYSTEM 3.3 Concept of I/O number assignment In the multiple CPU system, I/O numbers are used for interactive transmission between a CPU module and the I/O modules and intelligent function modules, or between CPU modules. 3.3.1 I/O number assignment of each module The multiple CPU system is different from the Single CPU system in the position (slot) of I/ O number 00 However, the concept of the order of allocating I/O numbers, I/O numbers for each slot...
Page 131 CONCEPT FOR MULTIPLE CPU SYSTEM (d) When using the PC CPU module The PC CPU module occupies two slots. The one on the right side among the two slots is handled as an empty slot. (16 empty points are occupied by default.) Therefore the I/O number of the next slot on the right side of the PC CPU module is "10 ."...
Page 132: I/O Number Of Each Cpu Module
CONCEPT FOR MULTIPLE CPU SYSTEM 3.3.2 I/O number of each CPU module In the multiple CPU system, I/O numbers are assigned to each CPU module to specify mounted CPU modules. The I/O number for each CPU module is fixed to the corresponding slot and cannot be changed in the I/O assignment of the PLC parameter.
Page 133: Access Range Of Cpu Module And Other Modules
CONCEPT FOR MULTIPLE CPU SYSTEM 3.4 Access Range of CPU Module and Other Modules 3.4.1 Access range with controlled module In the multiple CPU system a CPU can refresh I/O data of its controlled modules and write or read data of the buffer memory of intelligent function modules in the same way as a single CPU system.
Page 134 CONCEPT FOR MULTIPLE CPU SYSTEM (1) Loading input (X) The "I/O sharing when using Multiple CPUs" setting in the PLC parameter's Multiple CPU settings determines whether input can be loaded from input modules and intelligent function modules being controlled by other CPUs. I/O sharing when using Multiple CPUs All CPUs can read all inputs: "All CPUs can read all inputs"...
Page 135 CONCEPT FOR MULTIPLE CPU SYSTEM 2) Input(X) loading is performed for the modules shown in Table3.8, which are mounted to the main base unit or extension base unit(s). Table3.8 Modules that can load inputs I/O allocation type Mounted module Input module High speed input module None I/O composite module...
Page 136 CONCEPT FOR MULTIPLE CPU SYSTEM (2) Loading output (Y) The "I/O sharing when using Multiple CPUs" setting in the PLC parameter's Multiple CPU settings determines whether output can be loaded from output modules and intelligent function modules being controlled by other CPUs. I/O sharing when using Multiple CPUs All CPUs can read all outputs: "All CPUs can read all outputs"...
Page 137 CONCEPT FOR MULTIPLE CPU SYSTEM 2) Output(Y) loading is performed for the modules shown in Table3.9, which are mounted to the main base unit or extension base unit(s). Table3.9 Modules that can load outputs I/O allocation type Mounted module Output module None I/O composite module Intelligent function module...
Page 138 CONCEPT FOR MULTIPLE CPU SYSTEM (3) Output to output modules and intelligent function modules It is not possible to output ON/OFF data to non-controlled modules. Devices will be turned ON or OFF inside the QCPU when the output from output modules or intelligent function modules controlled by other CPUs is turned ON/OFF by a sequence program, but this will not be actually output to the output modules or intelligent function modules.
Page 139 CONCEPT FOR MULTIPLE CPU SYSTEM (b) Writing to buffer memory The following instructions cannot be used to write data to the buffer memory of intelligent function modules being controlled by other CPUs. • TO instruction • Instructions that use inteligent function module device (U \G ) •...
Page 140: Access Target Under Got Connection
CONCEPT FOR MULTIPLE CPU SYSTEM 3.5 Access target under GOT connection When a GOT is connected, the access range to QCPU varies depending on the connection method. For details, refer to the GOT manual. 3.6 Access with instruction using link direct device Only control CPUs can execute instructions using link direct devices to access other modules.
Page 141: Access Range Of Gx Developer
CONCEPT FOR MULTIPLE CPU SYSTEM 3.7 Access range of GX Developer (1) Access to QCPU It is possible to write parameters and programs and perform monitoring and tests on QCPUs connected to GX Developer. To access QCPUs of other CPU No. via a QCPU connected to GX Developer, specify the target CPU No.
Page 142 CONCEPT FOR MULTIPLE CPU SYSTEM (2) Access to controlled module and non-controlled module GX Developer can access the modules regardless of whether they are controlled or non-controlled by the QCPU connected to the GX Developr. By connecting GX Developer to a single QCPU, it is possible to perform monitoring and tests on all modules being controlled by the multiple CPU system's QCPU.
Page 143 CONCEPT FOR MULTIPLE CPU SYSTEM (3) Access from GX Developer in other station From GX Developer connected to other station on the same network, all QCPUs in the multiple CPU system can be accessed. Station No. 2 (normal station) Station No. 3 (normal station) Control CPU setting MELSECNET/H PLC to PLC network Station No.
Page 144: Clock Data Used By Cpu Module And Intelligent Function Module
CONCEPT FOR MULTIPLE CPU SYSTEM 3.8 Clock data used by CPU module and intelligent function module This section shows the clock data used by the CPU module and the intelligent function module. 3.8.1 Clock data used by CPU module Note3.5 The following shows the clock data used by the CPU module.
Page 145: Resetting The Multiple Cpu System
CONCEPT FOR MULTIPLE CPU SYSTEM 3.9 Resetting the multiple CPU system The entire multiple CPU system can be reset by resetting CPU No.1. The CPU modules of No.2 to No.4, I/O modules and intelligent function modules will be reset when CPU No.1 is reset. If a stop error occurs in any of the CPUs on the multiple CPU system, either reset CPU No.1 or restart the multiple CPU system (power supply ON ON) for recovery.
Page 146: Operation For Cpu Module Stop Error
CONCEPT FOR MULTIPLE CPU SYSTEM 3.10 Operation for CPU module stop error The entire system will behaves differently depending whether a stop error occurs in CPU No.1 or any of CPU No.2 to No.4 in the multiple CPU system. (1) When a stop error occurs at CPU No.1 A "MULTI CPU DOWN (error code: 7000)"...
Page 147 CONCEPT FOR MULTIPLE CPU SYSTEM POINT When a stop error occurs, a "MULTI CPU DOWN (error code : 7000)" stop error will occur at the CPU on which the error was detected. Depending on the timing of error detection, a "MULTI CPU DOWN" error may be detected in a CPU of "MULTI CPU DOWN"...
Page 148 CONCEPT FOR MULTIPLE CPU SYSTEM (3) System recovery procedure Observe the following procedures to restore the system. 1) Confirm the error-derected CPU No. and error cause with the PLC diagnostics on GX Developer. 2) Remove the error cause. 3) Either reset the CPU No.1 or restart the power to the programmable controller (power ON ON).
Page 149: Host Cpu Number Of Multiple Cpu System
CONCEPT FOR MULTIPLE CPU SYSTEM 3.11 Host CPU number of multiple CPU system Checking the host CPU number of the multiple CPU system is a function to check whether [Host CPU number] in [Multiple CPU settings] of the PLC parameter is identical to the number of the host CPU which is actually mounted.
Page 150 CONCEPT FOR MULTIPLE CPU SYSTEM POINT When making multiple CPU settings of all CPU modules in multiple CPU system same, set "No specification" to "Host CPU number". If [No specification] is set at [Host CPU number], all CPU modules used in the multiple CPU system can share the same multiple CPU setting.
Page 151: Chapter4 Communications Between Cpu Modules
COMMUNICATIONS BETWEEN CPU MODULES CHAPTER4 COMMUNICATIONS BETWEEN CPU MODULES In the multiple CPU system, the following methods are available to read/write data between CPU modules: • Communications with auto refresh Section 4.1.2, Section 4.1.3) Data reading/writing between CPU modules • Communications with programs Section 4.1.4) Writing/reading of data among the C Controller module, PC CPU module, and QCPU in another CPU...
Page 152 COMMUNICATIONS BETWEEN CPU MODULES (1) Communications between CPU modules In the multiple CPU system, various communications between CPU modules are available depending on the communication source and destination CPU module types as shown Table4.1. For communication from the Motion CPU, PC CPU module, and C Controller module, refer to the manuals of each module.
Page 153: Communications Between Cpu Modules Using Cpu Shared Memory
COMMUNICATIONS BETWEEN CPU MODULES 4.1 Communications between CPU modules using CPU shared memory This chapter describes communication methods between CPU modules of the multiple CPU system using the CPU shared memory. First, the CPU shared memory is described. 4.1.1 CPU shared memory The CPU shared memory is a memory provided for each CPU module and by which data are written or read between CPU modules of the multiple CPU system.
Page 154 COMMUNICATIONS BETWEEN CPU MODULES The CPU shared memory configuration and the availability of the communication from the host CPU using the CPU shared memory by program are shown in Diagram 4.1 to Diagram 4.3. • For Basic model QCPU Host CPU Other CPUs Write Read...
Page 155 COMMUNICATIONS BETWEEN CPU MODULES • For Universal model QCPU Host CPU Other CPU CPU shared memory Write Read Write Read Host CPU operation information area ( 1FF G511 ( 200 G512 Restricted system area QCPU standard ( 7FF G2047 area ( 800 G2048 Auto refresh area...
Page 156 COMMUNICATIONS BETWEEN CPU MODULES (1) Host CPU operation information area (a) Information stored in the host CPU operation information area The following information is stored in the host CPU operation infomation area in the multiple CPU system. These will all remain as 0 and will not change in the case of single CPU system. Table4.2 List of host CPU operation information areas Correspon shared...
Page 157 COMMUNICATIONS BETWEEN CPU MODULES (2) Restricted system area The area used by the system of the CPU module (OS.) (3) Auto refresh area The area used when the multiple CPU system is automatically refreshed. Section 4.1.2) The points from the address next to the last address in the restricted system area are used for auto refresh.
Page 158: Communication By Auto Refresh Using Cpu Shared Memory
COMMUNICATIONS BETWEEN CPU MODULES 4.1.2 Communication by auto refresh using CPU shared memory Universal The following describes communications with auto refresh using auto refresh area in CPU Note4.2 Note4.2 shared memory. For the communication by the auto refresh using the multiple CPU high speed Note4.3 transmission area in the Universal model QCPU , refer to Section 4.1.3.
Page 159 COMMUNICATIONS BETWEEN CPU MODULES (1) Communication using auto refresh (a) Operation of auto refresh Auto refresh allows communications using the auto refresh area of the CPU shared memory. By making multiple CPU settings in "PLC parameter", data are automatically written/read between all CPU modules of the multiple CPU system. As device memory data of other CPUs are automatically read by the auto refresh function, the host CPU can use those device data.
Page 160 COMMUNICATIONS BETWEEN CPU MODULES Diagram 4.5 shows an outline of operations when CPU No.1 performs auto refresh of 32 points for B0 to B1F, and when CPU No.2 performs auto refresh of 32 points for B20 to B3F. CPU No. 1 CPU No.
Page 161 COMMUNICATIONS BETWEEN CPU MODULES (2) Refresh settings To perform auto refresh in CPU shared memory, set the number of points to be sent from each CPU module (Send range for each PLC) and a device for storing data (PLC side device) on Multiple CPU settings in PLC parameter. Select either setting the device of Setting No.
Page 162 COMMUNICATIONS BETWEEN CPU MODULES 3) The number of send points is as follows: • For Basic model QCPU The numbers of send points are 320 words for the Basic model QCPU and 2048 words for the Motion CPU/PC CPU module, making a total of 4416 points (4416 words) for all CPU modules.
Page 163 COMMUNICATIONS BETWEEN CPU MODULES 4) The area occupied for auto refresh in the CPU shared memory is a total of Setting 1 to 4. When send points are set, the first and last addresses of the auto refresh area are automatically displayed as hexadecimal offset values. For example, the CPU that has send point setting in Setting 1 and 2 has the last address of "the first address of the auto refresh area + offset value of Setting 2".
Page 164 COMMUNICATIONS BETWEEN CPU MODULES 5) The same number of send points must be set for all CPUs in the multiple CPU system. If different number of send points is set for a CPU, "PARAMETER ERROR" occurs in the consistency check between CPUs. Section 6.1 (3)) For details of consistency check between CPUs, refer to Section 6.1.
Page 165 COMMUNICATIONS BETWEEN CPU MODULES 3) The CPU devices are set as follows. • It is possible to change the device for settings 1 to 4. The same devices can also be specified as long as the device range for settings 1 to 4 are not overlapped. Setting 1: For link relay Settings with different devices are available at...
Page 166 COMMUNICATIONS BETWEEN CPU MODULES • Devices of setting 1 to 4 can be set independently for each CPU. For example, devices of CPU No.1 can be set up as link relays, and those of CPU No.2 can be set up as internal relays. Refresh setting of CPU No.
Page 167 COMMUNICATIONS BETWEEN CPU MODULES 4) When the auto refresh operations are divided into four ranges (Setting 1: Link relay (B), Setting 2: Link register (W), Setting 3: Data register (D), Setting 4: Internal relay (M)), the outline is as shown in Diagram 4.16.Note5 CPU No.
Page 168 COMMUNICATIONS BETWEEN CPU MODULES POINT The followings are available when selecting the method of setting devices with each CPU optionally. • The order of the send range for each module can be changed, since devices can be set individually. • The system scan time can be reduced, since it is possible to set for not performing unnecessary refresh.
Page 169 COMMUNICATIONS BETWEEN CPU MODULES (Example 2) When setting not to perform unnecessary refresh The following shows the example performing auto refresh between each CPU from No.2 to No.4 and CPU No.1 only. By leaving the device column of other CPUs of which auto refresh is not required in blank, it is possible to set not to perform unnecessary refresh.
Page 170 COMMUNICATIONS BETWEEN CPU MODULES (3) Precautions Basic Note4.6 Note4.6 (a) Local device setting Note6 Device ranges set for the use of the auto refresh cannot be set to local devices. If set, the refresh data will not be updated. Note4.7 (b) Setting for using the same file name as the program in the file register Basic Do not set devices for the use of the auto refresh in the file register for each...
Page 171 COMMUNICATIONS BETWEEN CPU MODULES 2) Data consistency for data exceeding 32 bits In auto refresh method, data are read in descending order of the setting number in auto refresh setting parameter. Read data separation can be avoided by using the setting number lower than the setting data as an interlock device.
Page 172 COMMUNICATIONS BETWEEN CPU MODULES • Auto refresh between QCPUs Diagram 4.22 shows program examples between the High Performance model QCPU when Auto refresh settings in Multiple CPU settings are made as Table 4.5. <Parameter setting> Table4.5 Parameter setting example for interlock program CPU shared memory Device at CPU Setting...
Page 173: Communication By Auto Refresh Using Multiple Cpu High Speed Transmission Area
COMMUNICATIONS BETWEEN CPU MODULES 4.1.3 Communication by auto refresh using multiple CPU high speed transmission area The following describes the communication by the auto refresh using the multiple CPU high speed transmission area in the Universal model QCPU. The communication by the auto refresh using the multiple CPU high speed transmission area can be performed only when the following conditions are all met.
Page 174 COMMUNICATIONS BETWEEN CPU MODULES (1) Communication using auto refresh (a) Overview of auto refresh The auto refresh is a communication method using the auto refresh area of the multiple CPU high speed transmission area in the CPU shared memory. The data written to the auto refresh area of the multiple CPU high speed transmission area is sent to that of the other CPUs in a certain cycle (multiple CPU high speed transmission cycle).
Page 175 COMMUNICATIONS BETWEEN CPU MODULES Diagram 4.24 shows an outline of operations when CPU No.1 performs auto refresh of 32 points for B0 to B1F, and when CPU No.2 performs auto refresh of 32 points for B20 to B3F. CPU No.1 CPU No.2 CPU shared memory CPU shared memory...
Page 176 COMMUNICATIONS BETWEEN CPU MODULES (c) Memory configuration of multiple CPU high speed transmission area The following explains the memory configuration of the multiple CPU high speed transmission area of the CPU shared memory that is used in the multiple CPU high speed transmission function.
Page 177 COMMUNICATIONS BETWEEN CPU MODULES (d) Settings required for auto refresh To perform auto refresh, setting the number of points to be sent from each CPU module and a device for storing data (device for executing auto refresh) on Multiple CPU settings in PLC parameter is required. 4.1 Communications between CPU modules using CPU shared memory - 27 4.1.3 Communication by auto refresh using multiple CPU high speed transmission area...
Page 178 COMMUNICATIONS BETWEEN CPU MODULES (2) Multiple CPU high speed transmission area setting To perform auto refresh in CPU shared memory, set the number of points to be sent from each CPU module (Send range for each PLC) and a device for storing data (Auto refresh settings) on Multiple CPU settings in PLC parameter.
Page 179 COMMUNICATIONS BETWEEN CPU MODULES POINT Selecting "Advanced settings" enables to change the number of points in Restricted system area used for dedicated instructions to 2 k points. Changing the number of points in system area to 2 k enables to increase the number of dedicated instructions can be executed concurrently in a scan.
Page 180 COMMUNICATIONS BETWEEN CPU MODULES (b) Auto refresh setting Auto refresh setting is a setting to use the auto refresh function. The 32 ranges can be set for each CPU modules. Auto refresh setting screen and the setting range are shown below. Diagram 4.28 Auto refresh setting screen Table4.9 List of setting item for the refresh setting Item...
Page 181 COMMUNICATIONS BETWEEN CPU MODULES (3) Auto refresh setting and data flow The following explains the data flow among CPU modules when a multiple CPU system is configured among three CPU modules and auto refresh is set for two ranges. (a) Setting examples of auto refresh to each CPU module Diagram 4.29 shows the setting examples of auto refresh to explain the data flow by auto refresh.
Page 182 COMMUNICATIONS BETWEEN CPU MODULES (b) Data flow among CPU modules The following explains the data flow among CPU modules by the auto refresh set as (a). 1) Flow of sending data from CPU No.1 to other CPUs <Parameter setting> Diagram 4.30 shows the settings related to sending and receiving CPU No.1 data ((a) to (c) in Diagram 4.30) in the setting example of auto refresh in Diagram 4.30.
Page 183 COMMUNICATIONS BETWEEN CPU MODULES 2) Flow of sending data from CPU No.2 to other CPUs <Parameter setting> Diagram 4.32 shows the settings related to sending and receiving CPU No.2 data ((d) to (f) in Diagram 4.32) in the setting example of auto refresh in Diagram 4.32.
Page 184 COMMUNICATIONS BETWEEN CPU MODULES 3) Flow of sending data from CPU No.3 to other CPUs <Parameter setting> Diagram 4.34 shows the settings related to sending and receiving CPU No.3 data ((g) to (i) in Diagram 4.34) in the setting example of auto refresh in Diagram 4.34.
Page 185 COMMUNICATIONS BETWEEN CPU MODULES POINT If Start and End fields in Auto refresh are left blank, auto refresh is not performed. The example for setting blank to the auto refresh setting .of the CPU No.2 in <Flow of sending data from CPU No.3 to other CPUs> explained in the previous page 3) is shown below.
Page 186 COMMUNICATIONS BETWEEN CPU MODULES (4) Precautions (a) Local device setting Device ranges set for the use of the auto refresh cannot be set to local devices. If set, the refresh data will not be updated. (b) Setting for using the same file name as the program in the file register Do not set devices for the use of the auto refresh in the file register for each program.
Page 187 COMMUNICATIONS BETWEEN CPU MODULES Receive side program (CPU No.2) Transmission side program (CPU No.1) (Transmission side (CPU No. 1)) (Reception side (CPU No. 2)) Write command M100 Operation using Set send data receive data from D0 to D9. (D0 to D9) SET M0 SET M32 RST M0...
Page 188: Communication Using Cpu Shared Memory By Program
COMMUNICATIONS BETWEEN CPU MODULES 4.1.4 Communication using CPU shared memory by program This section explains communications with programs using CPU shared memory in a multiple CPU system. Use the following areas in a CPU shared memory for the communications with programs using CPU shared memory.
Page 189 COMMUNICATIONS BETWEEN CPU MODULES (1) Communication made by program (a) Instructions used for writing to/reading from the CPU shared memory The QCPU in a multiple CPU system enables to communicate each CPU module using user free areas in CPU shared memory and multiple CPU high speed transmission area with the write and read instructions.
Page 190 COMMUNICATIONS BETWEEN CPU MODULES (b) Outline of the communication by the program 1) Using user setting area The data written to the CPU shared memory of the host CPU with a write instruction can be read by another CPU using a read instruction. Unlike the auto refresh of the CPU shared memory, it is possible to read up-to- date data directly when this instruction is executed.
Page 191 COMMUNICATIONS BETWEEN CPU MODULES 2) Using user setting aera in multiple CPU high speed transmission area The data written to the multiple CPU high speed transmission area of the CPU shared memory of the host CPU by the write instruction is sent to the other CPU in a certain cycle.
Page 192 COMMUNICATIONS BETWEEN CPU MODULES (c) Memory configuration of multiple CPU high speed transmission area 1) Addresses of user setting area The addresses of user setting area depend on the CPU module. For user setting area addresses, refer to Section 4.1.1. 2) Addresses of multiple CPU high speed transmission area The following explains the memory configuration of the multiple CPU high speed transmission area that is used in the multiple CPU high speed...
Page 193 COMMUNICATIONS BETWEEN CPU MODULES (3) Assurance of data sent between CPUs The old data and the new data may be mixed (data separation) in each CPU due to the timing of receiving data from the other CPU and reading in the host CPU. The following shows the method to realize the data consistency of the user data for the data transmission in the multiple CPU high speed transmission function.
Page 194 COMMUNICATIONS BETWEEN CPU MODULES (b) Preventing separation for data exceeding 32 bits 1) Using user setting area Programs are read from the start of user setting area. With the write instruction, send data are written from the last address to the start address of the user setting area.
Page 195 COMMUNICATIONS BETWEEN CPU MODULES 2) Using multiple CPU high speed transmission area In the direct access mode, the data is transferred in order starting from the one which was written to the user setting area first. Using the device which is written after the data transfer regardless of kinds of device or addresses can realize the data consistency of the transferred data.
Page 196 COMMUNICATIONS BETWEEN CPU MODULES (4) Precautions (a) First I/O numbers of CPU modules The following values are set for the CPU module's first I/O number in the write/ read instructions.Note10 Table4.12 First I/O numbers of CPU modules Basic CPU No.4 CPU No.
Page 197 COMMUNICATIONS BETWEEN CPU MODULES (e) Data writing to other CPU's shared memory Data cannot be written to the CPU shared memory of other CPU with a write instruction. Writing data to the CPU shared memory of other CPU No. with TO, S.TO instructions or those using the multiple CPU area device (U3En\G ) may result in "SP.
Page 198: Communications Between Cpu Modules When The Error Occurs
COMMUNICATIONS BETWEEN CPU MODULES 4.1.5 Communications between CPU modules when the error occurs (1) Operation when the error occurs to the receive data When the CPU module receives the improper data at the data communication between the CPU modules due to noise or failure, it cancels the receive data. When the receive data is canceled, the data which was received before this one remains without change.
Page 199: Communications With Instructions Dedicated To Motion Cpu
COMMUNICATIONS BETWEEN CPU MODULES 4.2 Communications with instructions dedicated to Motion CPU 4.2.1 Control instruction from QCPU to Motion CPU Control instructions can be issued from the QCPU to Motion CPU with the instructions dedicated to Motion CPU as listed in Table4.14. (Control instructions from a Motion CPU to other Motion CPU is not allowed.) Table4.14 List of instructions dedicated to Motion CPU CPU module...
Page 200 COMMUNICATIONS BETWEEN CPU MODULES (Example) When using the S.SFCS instruction It is possible to start up the Motion CPU's motion SFC from the QCPU. Motion CPU QCPU Motion SFC Start request S.SFCS instruction Diagram 4.45 Operation of S.SFCS instruction POINT One QCPU can concurrently issue up to 32 instructions of "Instructions dedicated to Motion CPU"...
Page 201: Communication With Dedicated Instructions
COMMUNICATIONS BETWEEN CPU MODULES 4.3 Communication with Dedicated Instructions 4.3.1 Writing/reading of device data from QCPU to Motion CPU The QCPU can write/read device data to/from the Motion CPU with the multiple CPU transmission dedicated instruction and multiple CPU high-speed transmission dedicated instruction.
Page 202 COMMUNICATIONS BETWEEN CPU MODULES (2) Multiple CPU high-speed transmission dedicated instruction The Universal model QCPU can write/read device data to/from the Q172DCPU and Q173DCPU with the multiple CPU high-speed transmission dedicated instruction shown on Table4.16. Table4.16 List of multiple CPU high-speed transmission dedicated instructions CPU module Universal model QCPU Q03UD(E)CPU...
Page 203 COMMUNICATIONS BETWEEN CPU MODULES POINT One QCPU can concurrently issue up to 32 instructions of "Instructions dedicated to Motion CPU" and "Multiple CPU transmission dedicated instructions (except for S(P).GINT)". Note that multiple instructions are executed in order starting from the first instruction.
Page 204: Starting Interrupt Program From Qcpu To C Controller Module/Pc Cpu Module
COMMUNICATIONS BETWEEN CPU MODULES 4.3.2 Starting interrupt program from QCPU to C Controller module/PC CPU module Using the multiple CPU transmission dedicated instruction in Table4.17, an interrupt program can be started from the QCPU to the C Controller module/PC CPU module. The interrupt program from the PC CPU module to other CPU module cannot be started.
Page 205: Writing/Reading Of Device Data From Qcpu To Qcpu
COMMUNICATIONS BETWEEN CPU MODULES 4.3.3 Writing/reading of device data from QCPU to QCPU The Universal model QCPU can write/read device data to/from another Universal model QCPU with the multiple CPU high-speed transmission dedicated instruction shown on Table4.18. Table4.18 List of multiple CPU high-speed transmission dedicated instructions CPU module Universal model QCPU Q03UD(E)CPU...
Page 206: Multiple Cpu Synchronous Interrupt
COMMUNICATIONS BETWEEN CPU 4.4 Multiple CPU Synchronous Interrupt The multiple CPU synchronous interrupt function executes interrupt programs (multiple CPU synchronous interrupt programs) at the timing of multiple CPU high speed transmission cycle. The multiple CPU synchronous interrupt enables synchronization with multiple CPU high speed transmission cycle and communications among CPU modules.
Page 207 COMMUNICATIONS BETWEEN CPU When a multiple CPU synchronous interrupt factor occurs during the execution of another interrupt program, the running program is aborted to execute the multiple CPU synchronous interrupt program. Interrupt request from I45 Interrupt request from In Sequence program IRET Interrrupt program IRET...
Page 208: Multiple Cpu Synchronized Boot-Up
COMMUNICATIONS BETWEEN CPU 4.5 Multiple CPU Synchronized Boot-up Multiple CPU synchronized boot-up function synchronizes the start-ups of CPU No.1 to CPU No.4. Since this function monitors the startup of each CPU module, when another station is accessed by manual operation, an interlock program which checks the CPU module startup is unnecessary.
Page 209 COMMUNICATIONS BETWEEN CPU POINT The Multiple CPU synchronous startup setting cannot be made for the CPU modules except the Universal model QCPU (except the Q02UCPU) and the Motion CPU (Q172DCPU, Q173DCPU). When these modules have been used, deselect the relevant CPUs at the Multiple CPU synchronous startup setting.
Page 210: Chapter5 Processing Time Of Qcpu In Multiple Cpu System
PROCESSING TIME OF QCPU IN MULTIPLE CPU SYSTEM CHAPTER5 PROCESSING TIME OF QCPU IN MULTIPLE CPU SYSTEM 5.1 Concept of Scan Time The concept of scan time in the multiple CPU system is the same as that in the single CPU system.
Page 211 PROCESSING TIME OF QCPU IN MULTIPLE CPU SYSTEM (3) Common processing The values in Table5.2 show the common processing time. Table5.2 END processing time QCPU Common processing time Q00CPU (0.05 to 0.13) (No. of other CPUs)ms Q01CPU Q02CPU 0.02ms Q02HCPU, Q06HCPU, Q12HCPU, Q25HCPU 0.03ms Q02PHCPU, Q06PHCPU,...
Page 212: Factors For Prolonged Scan Time
PROCESSING TIME OF QCPU IN MULTIPLE CPU SYSTEM 5.2 Factors for prolonged Scan Time The processing time in Multiple CPU Systems is prolonged in comparison with Single CPU Systems when the following functions are used. When using the following, add the values described later to the values calculated in Sections 5.1.
Page 213 PROCESSING TIME OF QCPU IN MULTIPLE CPU SYSTEM (b) Calculation of auto refresh time The automatic refresh time of the CPU shared memory is calculated in the following equation. 1) For Basic model QCPU (Auto refresh time) = (N1 + (No. of transmission word points) N2)) + (N3 + (No.
Page 214 PROCESSING TIME OF QCPU IN MULTIPLE CPU SYSTEM 3) For Universal model QCPU (Auto refresh time) = (N1 + (No. of transmission word points) N2)) + (N3 + (No. of other CPUs) N4 + (No. of reception word points) N5) (µs) •...
Page 215 PROCESSING TIME OF QCPU IN MULTIPLE CPU SYSTEM (c) When auto refresh of another CPU occurs during auto refresh processing of a CPU If auto refresh of another CPU occurs during auto refresh processing of a CPU, the auto refresh time increases by the time obtained from each the following calculations.
Page 216 PROCESSING TIME OF QCPU IN MULTIPLE CPU SYSTEM High Note5.3, Note5.4 (2) Refresh of CC-Link IE controller network and MELSECNET/ Performance Note5.3 Note5.3 (a) Refresh time of CC-Link IE controller network and MELSECNET/H The amount of time required for performing the refresh between the QCPU and Basic Process the CC-Link IE controller network or MELSECNET/H network module.
Page 217 PROCESSING TIME OF QCPU IN MULTIPLE CPU SYSTEM Note5.5 Note5.6 2) For High Performance model QCPU /Process CPU /Universal High Performance model QCPU Note5.5 (Extension time) = (No. of transmission/reception word points) (No. of other CPUs) ( s) Process The number of transmission/reception words is the total number of transfer data below.
Page 218 PROCESSING TIME OF QCPU IN MULTIPLE CPU SYSTEM (3) CC-Link auto refresh (a) Auto refresh time on CC-Link network The amount of time required for performing the refresh process between QCPU and CC-Link master local modules. Refer to the following manual for details on the auto refresh time for CC-Link. QJ61BT11N CC-Link System Master Local Module User's Manual (b) Calculation of auto refresh time The amount of time required for the auto refresh process will be prolonged only by...
Page 219: Reducing Processing Time
PROCESSING TIME OF QCPU IN MULTIPLE CPU SYSTEM 5.3 Reducing processing time (1) Multiple CPU system processing Access is made between a CPU module and an I/O module or intelligent function module through a bus (base unit pattern, extension cable) and this bus cannot be used by multiple CPU modules at the same time.
Page 220 PROCESSING TIME OF QCPU IN MULTIPLE CPU SYSTEM POINT It is possible to reduce scan time by changing the following PLC parameter Basic Universal settings: Note5.8 Note5.8 • A Series CPU compatibility setting Note4 Note5.9 Universal Basic Process • Floating point arithmetic processing Note5 QCPU User's Manual (Function Explanation, Program Fundamentals).
Page 221: Chapter6 Parameter Added For Multiple Cpu System
PARAMETER ADDED FOR MULTIPLE CPU SYSTEM CHAPTER6 PARAMETER ADDED FOR MULTIPLE CPU SYSTEM 6.1 Parameter list (1) Parameters that enable the use of multiple CPU system Comparing with a single CPU system, a multiple CPU system has additional settings of "Multiple CPU settings" in PLC parameter and "Control PLC" setting in I/O assignment setting.
Page 222 PARAMETER ADDED FOR MULTIPLE CPU SYSTEM Table6.1 Setting list for the multiple CPU and I/O Assignment Note1 Necessity Necessity of same PLC parameter Reference of setup setting I/O Assignment Type ---- Model name ---- ---- Points ---- StartXY ---- Base setting QCPU User's Manual Base model name ----...
Page 223 PARAMETER ADDED FOR MULTIPLE CPU SYSTEM (b) For Universal model QCPU The table 6.2 shows the PLC parameter settings that are required when the Universal model QCPU is used. Table6.2 Setting list for the multiple CPU and I/O Assignment Necessity Necessity of same PLC parameter...
Page 224 PARAMETER ADDED FOR MULTIPLE CPU SYSTEM 1:Necessity of setup column : Items that must be set up for multiple CPU system (operations not possible if not set up.) : Items that may be set up when required for multiple CPU system ---- : Items that are the same as single CPU system.
Page 225 PARAMETER ADDED FOR MULTIPLE CPU SYSTEM (3) Multiple CPU parameters check At the time of the multiple CPU system power-on, reset or mode change from STOP to RUN of CPU No.1, or parameter change, whether the multiple CPU parameters are the same settings for all CPUs or not is checked as shown in Table 6.3 with items marked in the Necessity of same setting column in Tables 6.1 and 6.2...
Page 226: Number Of Cpus Setting
PARAMETER ADDED FOR MULTIPLE CPU SYSTEM POINT After multiple CPU system parameters unavailable with the Motion CPU are changed for the QCPU or PC CPU module in a multiple CPU system including a Motion CPU, be sure to reset the QCPU for CPU No.1 or turn off and on the programmable controller system.
Page 227 PARAMETER ADDED FOR MULTIPLE CPU SYSTEM (2) Reserving empty slot When an empty slot is reserved for the purpose of mounting additional CPU modules in the future, set "PLC (Empty)" on the "I/O assignment" tab screen in the "PLC parameter" dialog box. For example, when setting "4"...
Page 228: Operating Mode Setting
PARAMETER ADDED FOR MULTIPLE CPU SYSTEM 6.1.2 Operating mode setting This is set to continue operation of other CPUs where a stopping error has not occurred when an error occurs at other than CPU No.1. The operating mode for the CPU No.1 cannot be changed (all CPUs will suspend operations when a stop error is triggered for the CPU No.1.) Section 3.10 Basic...
Page 229: Control Cpu Settings
PARAMETER ADDED FOR MULTIPLE CPU SYSTEM 6.1.6 Control CPU settings Sets up the control CPUs (Control PLCs) for the I/O modules and intelligent function modules mounted on the base unit in the multiple CPU system. All default settings are set to CPU No.1. Diagram 6.3 Control CPU setting screen 6.1.7 Multiple CPU synchronized boot-up This is set for synchronizing the boot-up time for each CPU module.
Page 230: Chapter7 Precautions For Using Ans/A Series-Compatible Modules
PRECAUTIONS USING AnS/A SERIES- COMPATIBLE MODULES CHAPTER7 PRECAUTIONS FOR USING ANS/A SERIES- COMPATIBLE MODULES 7.1 Precautions for use of AnS/A series compatible module (1) Available AnS/A series-compatible modules When the multiple CPU system is configured with the High Performance model QCPU, AnS/A series compatible I/O modules and special function modules can be used.
Page 231 PRECAUTIONS USING AnS/A SERIES- COMPATIBLE MODULES (Example) When the control CPU is setup for CPU No.2 Set CPU No.2 to the control CPU for all slots where the AnS/A series- compatible modules are mounted. If setting different CPU as the control CPU among any one of the AnS/ A series-compatible module, "PARAMETER ERROR"...
Page 232 PRECAUTIONS USING AnS/A SERIES- COMPATIBLE MODULES (3) Ranges of access to controlled and non-controlled modules Table7.1 indicates access range to the controlled and non-controlled modules in the multiple CPU system. Table7.1 Access range to controlled module and non-controlled module Non-controlled module (I/O setting outside of Controlled the group) Access target...
Page 233 PRECAUTIONS USING AnS/A SERIES- COMPATIBLE MODULES (b) Unavailable modules The modules shown in Table7.3 cannot be used. Table7.3 List of unavailable modules Module Name Type A1SJ71LP21,A1SJ71BR11,A1SJ71QLP21, A1SJ71QLP21S,A1SJ71QLP21GE,A1SJ71QBR11, MELSECNET/IO network module AJ71LP21,AJ71LP21G,AJ71BR11,AJ71LR21, AJ71QLP21,AJ71QLP21S,AJ71QLP21G, AJ71QBR11,AJ71QLR21 A1SJ71AP21,A1SJ71AR21,A1SJ71AT21B, MELSECNET (II), /B data link module AJ71AP21,AJ71AP21-S3,AJ71AR21,AJ71AT21B A1SJ71QE71-B2-S3(-B5-S3), Ethernet interface module...
Page 234: Chapter8 Starting Up The Multiple Cpu System
STARTING UP THE MULTIPLE CPU SYSTEM CHAPTER8 STARTING UP THE MULTIPLE CPU SYSTEM This Chapter explains the standard start-up procedures for the multiple CPU system. 8.1 Flow-chart for Starting Up the Multiple CPU System Parameters should be preset and sequence programs should be prepared in advance. Section 8.2,Section 8.3) For parameter setting and program creation of the Motion CPU, C Controller module, and PC CPU module, refer to the manuals of each CPU...
Page 235 STARTING UP THE MULTIPLE CPU SYSTEM (From previous page) Writing parameter and Manual of the Motion CPU program to the Motion CPU Writing parameter and program Manual of the C Controller module to the C Controller module Writing parameter and Manual of the PC CPU module program to the PC CPU module RUN/STOP switch setting for all CPUs...
Page 236: Setting Up The Multiple Cpu System Parameters
STARTING UP THE MULTIPLE CPU SYSTEM 8.2 Setting Up the Multiple CPU System Parameters This section explains the procedures for setting multiple CPU parameter with GX Developer. Refer to the GX Developer's operation manual for details on setting up all other parameters.
Page 237 STARTING UP THE MULTIPLE CPU SYSTEM (2) Parameters required for multiple CPU system When the multiple CPU system is used, the following parameter settings are required. Parameters of "Same setting items for each CPU module" should be set with the same settings in all CPU modules used in the multiple CPU system except some parts.( Section...
Page 238 STARTING UP THE MULTIPLE CPU SYSTEM (3) When creating a new multiple CPU system Start The operating manual of GX Developer. Start-up of GX Developer Open the PLC parameter setting window The operating manual of GX Developer. for parameters of GX Developer. Select "PLC system"...
Page 239 STARTING UP THE MULTIPLE CPU SYSTEM Note4 (From previous page) Select "Multiple CPU settings" and display the multiple CPU setting window. No. of PLC (mandatory item) Set the number of CPU modules mounted Basic on the main base unit with the multiple CPU Note 8.3 system.
Page 240 STARTING UP THE MULTIPLE CPU SYSTEM Note5 (From previous page) Operating mode (option) Select if all CPUs are stopped/operated for occurrence of stop error. Default: With any error of CPUs 2, 3 and 4, all CPUs stop (checked). For example, when "All station stop by stop error of PLC 2"...
Page 241 STARTING UP THE MULTIPLE CPU SYSTEM (From previous page) Refresh settings (option) With change of settings, 4 settings from setting 1 to setting can be made. After setting, select "Setting completed" and close the multiple CPU setting window. Select "I/O assignment" and display the I/O assignment setting window.
Page 242 STARTING UP THE MULTIPLE CPU SYSTEM Note6 Note7 (From previous page) Control PLC (mandatory item) Basic Select control PLC (PLC No. 1 to PLC No. 4) Note 8.5 for each slot. Note8.5 For the intelligent function module of function version A, set Control PLC to PLC No. 1. For the AnS/A series-compatible module, set Basic Process...
Page 243 STARTING UP THE MULTIPLE CPU SYSTEM (4) Reusing preset multiple CPU parameters Start Refer to the operating manual of GX Developer. Start-up of GX Developer Open the PLC parameter setting window for the parameter of GX Developer. Select "Multiple CPU settings" and display the multiple CPU setting window.
Page 244 STARTING UP THE MULTIPLE CPU SYSTEM (From previous page) Setting of carry-over project Select the project that carries over multiple CPU setting and I/O assignment. Click "Open". When "OK" is selected, the multiple CPU setting and the I/O assignment setting data are read from the specified project and the data is overwritten.
Page 245 STARTING UP THE MULTIPLE CPU SYSTEM (From previous page) Select "PLC system" and display the PLC system setting window. Check the empty slot points on the PLC system setting window. (To next page) 8.2 Setting Up the Multiple CPU System Parameters - 12 8.2.1 Parameter setting for the Basic model QCPU,High Paformance model QCPU,Process CPU...
Page 246 STARTING UP THE MULTIPLE CPU SYSTEM (From previous page) Select "I/O assignment" and display the I/O assignment setting window. Check the I/O assignment settings and basic settings in the I/O assignment setting window. Select "Detailed setting" and display the detail setting window.
Page 247 STARTING UP THE MULTIPLE CPU SYSTEM (From previous page) Check settings of the control CPU. Set parameters for non-multiple CPU system. Write set parameters in the hard disk/floppy disk. Completed Diagram 8.5 Parameter setting procedure for reusing multiple CPU system parameters 8.2 Setting Up the Multiple CPU System Parameters - 14 8.2.1 Parameter setting for the Basic model QCPU,High Paformance model QCPU,Process CPU...
Page 248: Parameter Setting For The Universal Model Qcpu
STARTING UP THE MULTIPLE CPU SYSTEM 8.2.2 Parameter setting for the Universal model QCPU (1) System configuration Diagram 8.2 shows an example procedures for setting up the multiple CPU parameters. PC (GX Developer) Empty slot for addition of future CPU module CPU 0 Slot number Control CPU...
Page 249 STARTING UP THE MULTIPLE CPU SYSTEM (2) Parameters required for multiple CPU system When the multiple CPU system is used, the following parameter settings are required. Parameters of "Same setting items for each CPU module" should be set with the same settings in all CPU modules used in the multiple CPU system except some parts.( Section 6.1)
Page 250 STARTING UP THE MULTIPLE CPU SYSTEM (3) When creating a new multiple CPU system Start The operating manual of GX Developer. Start-up of GX Developer Open the PLC parameter setting window The operating manual of GX Developer. for parameters of GX Developer. Select "PLC system"...
Page 251 STARTING UP THE MULTIPLE CPU SYSTEM (From previous page) Select "Multiple CPU settings" and display the multiple CPU setting window. No. of PLC (mandatory item) Set the number of CPU modules mounted on the main base unit with the multiple CPU system.
Page 252 STARTING UP THE MULTIPLE CPU SYSTEM (From previous page) Operating mode (option) Select if all CPUs are stopped/operated for occurrence of stop error. Default: With any error of CPUs 2, 3 and 4, all CPUs stop (checked). For example, when "All station stop by stop error of PLC 2"...
Page 253 STARTING UP THE MULTIPLE CPU SYSTEM (From previous page) The number of points setting in Send range for each Set the number of points to be sent/received among CPU modules. Set them within the following number of points. No. of PLC Setting range 0 to 14k points 0 to 13k points...
Page 254 STARTING UP THE MULTIPLE CPU SYSTEM (From previous page) Select "I/O assignment" and display the I/O assignment setting window. I/O assignment (option) Select the slot to "PLC (Empty)" that does not mount the CPU module for each type. Select the type of each module from the pulldown menu.
Page 255 STARTING UP THE MULTIPLE CPU SYSTEM (From previous page) Control PLC (mandatory item) Select Control PLC for each slot. Selectable numbers depend on the CPU module used. Q02UCPU: PLC No.1 to PLC No.3 Except the Q02UCPU: PLC No.1 to PLC No.4 Set parameters for non-multiple CPU system.
Page 256: Reusing Preset Multiple Cpu Parameters
STARTING UP THE MULTIPLE CPU SYSTEM 8.2.3 Reusing preset multiple CPU parameters Start Refer to the operating manual of GX Developer. Start-up of GX Developer Open the PLC parameter setting window for the parameter of GX Developer. Select "Multiple CPU settings" and display the multiple CPU setting window.
Page 257 STARTING UP THE MULTIPLE CPU SYSTEM (From previous page) Setting of carry-over project Select the project that carries over multiple CPU setting and I/O assignment. Click "Open". When "OK" is selected, the multiple CPU setting and the I/O assignment setting data are read from the specified project and the data is overwritten.
Page 258 STARTING UP THE MULTIPLE CPU SYSTEM (From previous page) Select "PLC system" and display the PLC system setting window. Check the empty slot points on the PLC system setting window. (To next page) - 25 8.2 Setting Up the Multiple CPU System Parameters 8.2.3 Reusing preset multiple CPU parameters...
Page 259 STARTING UP THE MULTIPLE CPU SYSTEM (From previous page) Select "I/O assignment" and display the I/O assignment setting window. Check the I/O assignment settings and basic settings in the I/O assignment setting window. Select "Detailed setting" and display the detail setting window.
Page 260 STARTING UP THE MULTIPLE CPU SYSTEM (From previous page) Check settings of the control CPU. Set parameters for non-multiple CPU system. Write set parameters in the hard disk/floppy disk. Completed Diagram 8.9 Parameter setting procedure for reusing multiple CPU system parameters - 27 8.2 Setting Up the Multiple CPU System Parameters 8.2.3 Reusing preset multiple CPU parameters...
Page 261: Communication Program Examples Using Auto Refresh
STARTING UP THE MULTIPLE CPU SYSTEM 8.3 Communication program examples using auto refresh This section explains program examples in the following system configuration given in Diagram 8.10 and assignment of the data communications between CPU modules. PC (GX Developer) CPU 0 Slot number A/D D/A Input...
Page 262 STARTING UP THE MULTIPLE CPU SYSTEM Diagram 8.12 Auto refresh area settings - 29 8.3 Communication program examples using auto refresh 8.3.1 Program examples for the Basic model QCPU, High Performance model QCPU and Process CPU...
Page 263 STARTING UP THE MULTIPLE CPU SYSTEM (2) Example of bit & word data transmission from CPU No. 1 to No. 2 Table8.1 Auto refresh devices used in each CPU module Auto refresh devices used in CPU No. 1 Auto refresh devices used in CPU No. 2 D0,D1 D0,D1 Program example...
Page 264 STARTING UP THE MULTIPLE CPU SYSTEM (3) Example of continuous data transmission from CPU No. 1 to No. 2 Table8.2 Auto refresh devices used in each module Auto refresh devices used in CPU No. 1 Auto refresh devices used in CPU No. 2 D10 to D18 D10 to D18 For handshake in CPU Nos.
Page 265 STARTING UP THE MULTIPLE CPU SYSTEM (4) Writing/reading using the user setting area of the CPU shared memory by a program (a) Memory addresses for auto refresh setting to user setting area The same points must be set for CPU No.1 and CPU No.2 in the auto refresh setting.
Page 266 STARTING UP THE MULTIPLE CPU SYSTEM (b) Program example of continuous data writing/reading using the user setting area from CPU No. 2 to CPU No. 1 Table8.3 Auto refresh devices used in each CPU module Auto refresh device used in CPU No. 2 Auto refresh device used in CPU No.
Page 267: Program Examples For The Universal Model Qcpu
STARTING UP THE MULTIPLE CPU SYSTEM 8.3.2 Program examples for the Universal model QCPU This section explains program examples in the following system configuration given in Diagram 8.18 and assignment of the data communications between CPU modules. PC (GX Developer) CPU 0 Slot number A/D D/A...
Page 268 STARTING UP THE MULTIPLE CPU SYSTEM Diagram 8.20 Auto refresh area setting - 35 8.3 Communication program examples using auto refresh 8.3.2 Program examples for the Universal model QCPU...
Page 269 STARTING UP THE MULTIPLE CPU SYSTEM (2) Example of bit & word data transmission from CPU No. 1 to No. 2 Table8.4 Auto refresh devices used in each CPU module Auto refresh devices used in CPU No. 1 Auto refresh devices used in CPU No. 2 D0,D1 D0,D1 Program example...
Page 270 STARTING UP THE MULTIPLE CPU SYSTEM (3) Example of continuous data transmission from CPU No. 1 to No. 2 Table8.5 Auto refresh devices used in each module Auto refresh devices used in CPU No. 1 Auto refresh devices used in CPU No. 2 D10 to D18 D10 to D18 For handshake in CPU Nos.
Page 271 STARTING UP THE MULTIPLE CPU SYSTEM (4) Writing/reading using the user setting area of the CPU shared memory by a program (a) Memory addresses for auto refresh setting to user setting area In the auto refresh setting, make same settings for CPU No. 1 and CPU No. 2. Diagram 8.23 Auto refresh setting (same settings) User free area will be from 3E0\G10000 for CPU No.1 and from 3E1\G10000 for CPU No.2.
Page 272 STARTING UP THE MULTIPLE CPU SYSTEM (5) Program example of continuous data writing/reading using the user setting area from CPU No. 2 to CPU No. 1 Table8.6 Auto refresh devices used in each CPU module Auto refresh device used in CPU No. 2 Auto refresh device used in CPU No.
Page 273: Appendices
Appendix 1.2 Transport guidelines Comply with IATA Dangerous Goods Regulations, IMDG code and the local transport regulations when transporting products after unpacking or repacking, while Mitsubishi ships products with packages to comply with the transport regulations. Also, contact the transporters.
Page 274 APPENDICES Memo Appendix 1 Transportation Precautions Appendix 1.2 Transport guidelines...
Page 275: Index
INDEX A series ....... . A-19 GOT ........A-21 A series power supply module.
Page 276 Transportation precautions ....App-1 Wiring precautions ..... . A-5 Write instruction .
Page 277 Memo Index...
Page 278 1. Gratis Warranty Term and Gratis Warranty Range If any faults or defects (hereinafter "Failure") found to be the responsibility of Mitsubishi occurs during use of the product within the gratis warranty term, the product shall be repaired at no cost via the sales representative or Mitsubishi Service Company.

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Mitsubishi MELSEC-Q Series User Manual

Chapter1 Outline

Chapter2 System Configuration

Chapter3 Concept For Multiple Cpu System

Chapter4 Communications Between Cpu Modules

Chapter5 Processing Time of Qcpu in Multiple Cpu System

Chapter6 Parameter Added for Multiple Cpu System

CHAPTER7 PRECAUTIONS FOR USING Ans/A SERIES-COMPATIBLE MODULES

Chapter8 Starting Up the Multiple Cpu System

Appendix 1 Transportation Precautions

Appendix 1.1 Controlled Models

Appendix 1.2 Transport Guidelines

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