Page 1 Artisan Technology Group is your source for quality new and certified-used/pre-owned equipment SERVICE CENTER REPAIRS WE BUY USED EQUIPMENT • FAST SHIPPING AND DELIVERY Experienced engineers and technicians on staff Sell your excess, underutilized, and idle used equipment at our full-service, in-house repair center We also offer credit for buy-backs and trade-ins •...
Page 2 QCPU(Q Mode)/QnACPU Programming Manual (Common Instructions) Mitsubishi Programmable Logic Controller Artisan Technology Group - Quality Instrumentation ... Guaranteed | (888) 88-SOURCE | www.artisantg.com...
Page 3 • SAFETY PRECAUTIONS • (Always read these cautions before using the product) Before using this product, please read this manual and the related manuals introduced in this manual, and pay full attention to safety to handle the product correctly. Please store this manual in a safe place and make it accessible when required. Always forward a copy of the manual to the end user.
Page 4 This manual confers no industrial property rights or any rights of any other kind, nor does it confer any patent licenses. Mitsubishi Electric Corporation cannot be held responsible for any problems involving industrial property rights which may occur as a result of using the contents noted in this manual.
Page 5: Table Of Contents
INTRODUCTION Thank you for purchasing the Mitsubishi MELSEC-Q Series (Q mode) and MELSEC-QnA Series of Programmable Logic Controllers. Before using the product, please read this manual carefully to develop full familiarity with the functions and performance of the Programmable Logic Controller Q Series (Q mode)/QnA Series you have purchased, so as to ensure correct use.
Page 6 2.5.12 Special function instructions......................2 - 39 2.5.13 Data control instructions ........................ 2 - 41 2.5.14 Switching instructions ........................2 - 42 2.5.15 Clock instructions .......................... 2 - 43 2.5.16 Peripheral device instructions ....................... 2 - 44 2.5.17 Program instructions........................2 - 45 2.5.18 Other instructions...........................
Page 7 5.3.5 Setting devices (except for annunciators) (SET) ................5 - 28 5.3.6 Resetting devices (except for annunciators) (RST)................ 5 - 30 5.3.7 Setting and resetting the annunciators (SET F, RST F) ..............5 - 32 5.3.8 Leading edge and trailing edge output (PLS, PLF)................. 5 - 34 5.3.9 Bit device output reverse (FF) ......................
Page 8 6.3.7 Conversion from BIN 16 and 32-bit data to Gray code (GRY, GRYP, DGRY, DGRYP) ....6 - 67 6.3.8 Conversion of Gray code to BIN 16 and 32-bit data (GBIN, GBINP, DGBIN, DGBINP) ....6 - 69 6.3.9 Complement of 2 of BIN 16- and 32-bit data (sign reversal) (NEG, NEGP, DNEG, DNEGP) ..6 - 71 6.3.10 Sign reversal for floating decimal point data (ENEG, ENEGP) ............
Page 9 7.2 Rotation Instruction..........................7 - 30 7.2.1 Right rotation of 16-bit data (ROR, RORP, RCR, RCRP) .............. 7 - 30 7.2.2 Left rotation of 16-bit data (ROL, ROLP, RCL, RCLP) ..............7 - 32 7.2.3 Right rotation of 32-bit data (DROR, DRORP, DRCR, DRCRP)............ 7 - 34 7.2.4 Left rotation of 32-bit data (DROL, DROLP, DRCL, DRCLP) ............
Page 10 7.8.2 Writing 1-/2-word data to intelligent function module/special function module (TO, TOP, DTO, DTOP)........................ 7 - 137 7.9 Display Instructions ..........................7 - 140 7.9.1 Print ASCII code instruction (PR) ....................7 - 140 7.9.2 Print comment instruction (PRC)....................7 - 143 7.9.3 ASCII code LED display instruction (LED) ..................
Page 11 7.12.5 COS operation on floating decimal point data (ACOS, ACOSP)..........7 - 243 7.12.6 TAN operation on floating decimal point data (ATAN, ATANP)..........7 - 245 7.12.7 Conversion from floating decimal point angle to radian (RAD, RADP) ........7 - 247 7.12.8 Conversion from floating decimal point radian to angle (DEG, DEGP)........
Page 12 8. INSTRUCTIONS FOR DATA LINK 8 - 1 to 8 - 103 8.1 Network Refresh Instruction........................8 - 6 8.1.1 Network refresh (ZCOM)......................... 8 - 6 8.2 Instructions Dedicated to QnA Links...................... 8 - 12 8.2.1 Reading word device data from another station (READ)..............8 - 12 8.2.2 Reading word device data from another station (SREAD) .............
Page 13 11. ERROR CODES 11- 1 to 11 - 46 11.1 How to Read Error Codes ........................11 - 1 11.2 Error Code List ........................... 11 - 2 11.2.1 Error Code List of Basic model QCPU..................11 - 2 11.2.2 Error Code List of High Performance model QCPU/QnACPU........... 11 - 10 11.2.3 Error Code List of Process CPU ....................
Page 14 Manuals The following table lists the manuals related to the Q/QnACPU. Please order the one you need. Related Manuals Manual Number Manual Name (Model Code) Basic model QCPU (Q mode) User's Manual (Hardware design, Maintenance and Inspection) SH-080187 Describes the specifications of the CPU module, power supply module, base unit, and extension cables. (13JR43) (Sold separately) Basic model QCPU (Q mode) User's Manual (Functions Explanation, Programming...
Page 15 Manual Number Manual Name (Model Code) Q4ARCPU User's Manual IB-66685 Describes the Q4ARCPU features, functions, and usage. Also describes the specification and usage of the bus switching module, system management module, power supply module, memory card, and base unit. (13J852) (Sold separately) QnACPU Programming Manual (Fundamentals) IB-66614...
Page 16 MEMO A - 14 A - 14 Artisan Technology Group - Quality Instrumentation ... Guaranteed | (888) 88-SOURCE | www.artisantg.com...
Page 17: General Description
1 GENERAL DESCRIPTION MELSEC-Q/QnA 1. GENERAL DESCRIPTION This manual describes the common instructions for QCPU, QnACPU, and Q2AS(H)CPU(S1) that are required when programming with a QCPU, QnACPU, and Q2AS(H)CPU(S1). Common instructions are all instructions except those used for special function modules such as AJ71QC24, AJ71PT32-S3, etc.;...
Page 18 1 GENERAL DESCRIPTION MELSEC-Q/QnA (2) Q00JCPU, Q00CPU, Q01CPU Basic model QCPU (Q mode) Describes the functions, User's Manual executable programs, (Functions I/O processing, and Explanation, device names of Programming Basic model QCPU. fundamentals) This manual QCPU (Q mode)/ QnACPU Programming Manual (Common Instructions)
Page 19 1 GENERAL DESCRIPTION MELSEC-Q/QnA (4) Q2ACPU, Q3ACPU, Q4ACPU, Q4ARCPU, Q2AS(H)CPU QnACPU Describes the executable programs, I/O processing, Programming and device names of QnACPU. Manual (Fundamentals) This manual QCPU (Q mode)/ QCPU (Q mode)/ QnACPU QnACPU QnACPU QnACPU QCPU (Q mode)/ Programming Programming Programming...
Page 20: Abbreviation And Generic Name
1 GENERAL DESCRIPTION MELSEC-Q/QnA 1.2 Abbreviation and Generic Name The module names are abbreviated as follows Module Type Name Abbreviation Abbreviation in Tables Generic Name Q00JCPU PLC CPU Q00CPU PLC CPU Q01CPU PLC CPU Q02CPU PLC CPU Q02HCPU PLC CPU QCPU ——...
Page 21: Instruction Tables
2 INSTRUCTION TABLES MELSEC-Q/QnA 2. INSTRUCTION TABLES 2.1 Types of Instructions The major types of CPU module instructions consist of sequence instructions, basic instructions, application instructions, data link instructions, QCPU instructions and redundant system instructions. These types of instructions are listed in Table 2.1 below. Table 2.1 Types of Instructions Reference Types of Instructions...
Page 22: How To Read Instruction Tables
2 INSTRUCTION TABLES MELSEC-Q/QnA 2.2 How to Read Instruction Tables The instruction tables found from Section 2.3 to 2.6 have been made according to the following format: Table 2.2 How to Read Instruction Tables Execution Category Symbol Processing Details Condition (D)+(S) 6-16 BIN 16-bit...
Page 23 2 INSTRUCTION TABLES MELSEC-Q/QnA ...Shows symbol diagram on the ladder S1 S2 Indicates destination Indicates destination Indicates source Indicates source Indicates instruction symbol Indicates instruction symbol Fig. 2.1 Shows Symbol Diagram on the Ladder Destination ....Indicates where data will be sent after operation Source ......
Page 24: Sequence Instructions
2 INSTRUCTION TABLES MELSEC-Q/QnA 2.3 Sequence Instructions 2.3.1 Contact Instruction Table 2.3 Contact Instructions Execution Category Symbol Processing Details Condition • Starts logic operation (Starts a contact logic operation) • Starts logical NOT operation (Starts b contact logic operation) • Logical product (a contact series connection) •...
Page 25: Connection Instructions
2 INSTRUCTION TABLES MELSEC-Q/QnA 2.3.2 Connection instructions Table 2.4 Connection Instructions Execution Category Symbol Processing Details Condition • AND between logical blocks (Series connection between logical blocks) • OR between logical blocks (Series connection between logical blocks) • Memory storage of operation results •...
Page 26: Output Instructions
2 INSTRUCTION TABLES MELSEC-Q/QnA 2.3.3 Output instructions Table 2.5 Output Instructions Execution Category Symbol Processing Details Condition • Device output 5-18 5-28 • Set device 5-32 5-30 • Reset device 5-32 • Generates 1 cycle program pulse at Output leading edge of input signal 5-34 •...
Page 27: Master Control Instructions
2 INSTRUCTION TABLES MELSEC-Q/QnA 2.3.5 Master control instructions Table 2.7 Master Control Instructions Execution Category Symbol Processing Details Condition • Starts master control Master 5-42 control • Resets master control 2.3.6 Termination instruction Table 2.8 Termination Instructions Execution Category Symbol Processing Details Condition FEND...
Page 28: Basic Instructions
2 INSTRUCTION TABLES MELSEC-Q/QnA 2.4 Basic Instructions 2.4.1 Comparison operation instruction Table 2.10 Comparison Operation Instruction Execution Category Symbol Processing Details Condition • Conductive status when (S1) = (S2) S1 S2 • Non-conductive status when (S1) (S2) AND= S1 S2 S1 S2 •...
Page 29 2 INSTRUCTION TABLES MELSEC-Q/QnA Table 2.10 Comparison Operation Instructions (Continued) Execution Category Symbol Processing Details Condition • Conductive status when LDD= S1 S2 (S1+1, S1) = (S2+1, S2) • Non-Conductive status when ANDD= S1 S2 (S1+1, S1) (S2+1, S2) ORD= S1 S2 •...
Page 30 2 INSTRUCTION TABLES MELSEC-Q/QnA REMARK 1 : The number of steps may vary depending on the device and type of CPU module being used. Component Nomber of basic steps (1) When using the following devices only • Word device : Internal device (except for file register ZR) •...
Page 31 2 INSTRUCTION TABLES MELSEC-Q/QnA Table 2.10 Comparison Operation Instructions (Continued) Execution Category Symbol Processing Details Condition • Conductive status when LDE= S1 S2 (S1+1, S1) = (S2+1, S2) • Non-Conductive status when ANDE= S1 S2 (S1+1, S1) (S2+1, S2) ORE= S1 S2 •...
Page 32 2 INSTRUCTION TABLES MELSEC-Q/QnA Table 2.10 Comparison Operation Instructions (Continued) Execution Category Symbol Processing Details Condition • Compares character string S1 and LD$= S1 S2 character string S2 one character at a time. AND$= S1 S2 • Conductive status when (character string S1) = (character string S2) •...
Page 33 2 INSTRUCTION TABLES MELSEC-Q/QnA Table 2.10 Comparison Operation Instructions (Continued) Execution Category Symbol Processing Details Condition • Compares n points of data from S1 BKCMP= BKCMP S1 S2 D with n points of data from S2 in 1-word units, and stores the results of the <...
Page 34: Arithmetic Operation Instructions
2 INSTRUCTION TABLES MELSEC-Q/QnA 2.4.2 Arithmetic operation instructions Table 2.11 Arithmetic Operation Instructions Execution Category Symbol Processing Details Condition • (D)+(S) 6-16 • (S1)+(S2) S1 S2 D 6-18 BIN 16-bit addition S1 S2 D • (D) - (S) − subtraction operations 6-16 −...
Page 35 2 INSTRUCTION TABLES MELSEC-Q/QnA REMARKS 1:The number of steps may vary depending on the device and type of CPU module being used. Component Nomber of basic steps (1) When using the following devices only • Word device : Internal device (except for file register ZR) Note 1) •...
Page 36 2 INSTRUCTION TABLES MELSEC-Q/QnA Table 2.11 Arithmetic Operation Instructions (Continued) Execution Category Symbol Processing Details Condition • (D)+(S) 6-28 • (S1)+(S2) S1 S2 D BCD 4- 6-30 digit S1 S2 D addition • (D)-(S) − subtraction 6-28 operations − • (S1)-(S2) −...
Page 37 2 INSTRUCTION TABLES MELSEC-Q/QnA Table 2.11 Arithmetic Operation Instructions (Continued) Execution Category Symbol Processing Details Condition • (D+1, D)+(S+1, S) (D+1, D) 6-40 • (S1+1, S1)+(S2+1, S2) (D+1, D) S1 S2 D Floating 6-42 decimal point data S1 S2 D addition •...
Page 38 2 INSTRUCTION TABLES MELSEC-Q/QnA Table 2.11 Arithmetic Operation Instructions (Continued) Execution Category Symbol Processing Details Condition • (D)+1 6-53 INCP INCP • (D+1, D)+1 (D+1, D) DINC DINC 6-55 DINCP DINCP BIN data increment • (D)-1 6-53 DECP DECP • (D+1, D)-1 (D+1, D) DDEC DDEC...
Page 39: Data Conversion Instructions
2 INSTRUCTION TABLES MELSEC-Q/QnA 2.4.3 Data conversion instructions Table 2.12 Data Conversion Instructions Execution Category Symbol Processing Details Condition BCD conversion 6-57 BIN (0 to 9999) BCDP BCDP BCD con- BCD conversion versions DBCD DBCD (S+1, S) (D+1, D) 6-57 BIN (0 to 99999999) DBCDP DBCDP...
Page 40 2 INSTRUCTION TABLES MELSEC-Q/QnA Table 2.12 Data Conversion Instructions (Continued) Execution Category Symbol Processing Details Condition Conversion to BIN data GBIN GBIN 6-69 Gray code Conversion GBINP GBINP (-32768 to 32767) from gray code to Conversion to BIN data DGBIN DGBIN (S+1, S) (D+1, D)
Page 41: Data Transfer Instructions
2 INSTRUCTION TABLES MELSEC-Q/QnA 2.4.4 Data transfer instructions Table 2.13 Data Transfer Instructions Execution Category Symbol Processing Details Condition 16-bit data 6-78 transfer MOVP MOVP DMOV DMOV (D+1, D) (S+1, S) 32-bit data 6-78 transfer DMOVP DMOVP Floating (S+1, S) (D+1, D) EMOV EMOV...
Page 42 2 INSTRUCTION TABLES MELSEC-Q/QnA REMARK 1:The number of steps may vary depending on the device and type of CPU module being used. Component Nomber of basic steps (1) When using the following devices only • Word device : Internal device (except for file register ZR) •...
Page 43: Program Branch Instruction
2 INSTRUCTION TABLES MELSEC-Q/QnA 2.4.5 Program branch instruction Table 2.14 Program Branch Instruction Execution Category Symbol Processing Details Condition • Jumps to Pn when input conditions are 6-96 • Jumps to Pn from the scan after the 6-96 meeting of input condition Jump •...
Page 44: Other Convenient Instructions
2 INSTRUCTION TABLES MELSEC-Q/QnA 2.4.8 Other convenient instructions Table 2.17 Other Convenient Instructions Execution Category Symbol Processing Details Condition (S)+0 Down (S)+1 UDCNT1 6-113 UDCNT1 Current Cn value 1 2 3 4 6 7 6 5 3 2 1 0 -1 -2 -3 -2 -1 0 Cn contact point Up/Down Counter...
Page 45: Application Instructions
2 INSTRUCTION TABLES MELSEC-Q/QnA 2.5 Application Instructions 2.5.1 Logical operation instructions Table 2.18 Logical Operation Instructions Execution Category Symbol Processing Details Condition WAND WAND WANDP WANDP (S1) (S2) WAND WAND S1 S2 D WANDP WANDP S1 S2 D DAND DAND (S+1, S) (D+1, D) (D+1, D)
Page 46 2 INSTRUCTION TABLES MELSEC-Q/QnA Table 2.18 Logical Operation Instructions (Continued) Execution Category Symbol Processing Details Condition DXOR DXOR (S+1, S) (D+1, D) (D+1, D) 7-16 DXORP DXORP DXOR DXOR S1 S2 D (S1+1, S1) (S2+1, S2) (D+1, D) Exclusive 7-18 DXORP DXORP S1 S2 D...
Page 47: Rotation Instructions
2 INSTRUCTION TABLES MELSEC-Q/QnA 2:The number of steps may vary depending on the device and type of CPU module being used. Component Nomber of basic steps (1) When using the following devices only • Word device : Internal device (except for file register ZR) Note 1) •...
Page 48: Shift Instructions
2 INSTRUCTION TABLES MELSEC-Q/QnA 2.5.3 Shift instructions Table 2.20 Shift Instructions Execution Category Symbol Processing Details Condition 7-38 SM700 SFRP SFRP 0 to 0 n-bit shift 7-38 SM700 SFLP SFLP 0 to 0 BSFR BSFR 7-40 BSFRP BSFRP SM700 1-bit shift BSFL BSFL 7-40...
Page 49: Data Processing Instructions
2 INSTRUCTION TABLES MELSEC-Q/QnA Table 2.21 Bit processing Instructions (Continued) Execution Category Symbol Processing Details Condition (S1) TEST TEST S1 S2 D 7-46 Bit designated by (S2) TESTP TESTP S1 S2 D Bit tests (S1) DTEST DTEST S1 S2 D 7-46 Bit designated by (S2) DTESTP...
Page 50: Data Processing Instructions
2 INSTRUCTION TABLES MELSEC-Q/QnA Table 2.22 Data Processing Instructions (Continued) Execution Category Symbol Processing Details Condition b3 to b0 7-segment 7-60 7SEG decode SEGP SEGP • Separates 16-bit data designated by (S) into 4-bit units, and stores at the lower 4 bits of n points from (D).
Page 51 2 INSTRUCTION TABLES MELSEC-Q/QnA Table 2.22 Data Processing Instructions (Continued) Execution Category Symbol Processing Details Condition • Sorts data of n-points from device SORT S1 n S2 D1 designated by (S1) in 16-bit units. • S2: Number of comparisons made (n x (n-1)/2 scans required) during one run SORT...
Page 52: Structure Creation Instructions
2 INSTRUCTION TABLES MELSEC-Q/QnA 2.5.6 Structure creation instructions Table 2.23 Structure Creation Instructions Execution Category Symbol Processing Details Condition • Executes n times between FOR and NEXT 7-87 NEXT NEXT Number of repeats • Forcibly ends the execution of the FOR BREAK BREAK to NEXT cycle and jumps pointer to Pn.
Page 53: Table Operation Instructions
2 INSTRUCTION TABLES MELSEC-Q/QnA 2.5.7 Table operation instructions Table 2.24 Table Operation Instructions Execution Category Symbol Processing Details Condition Pointer Pointer +1 FIFW FIFW 7-125 Pointer +1 FIFWP FIFWP device Pointer -1 Pointer FIFR FIFR 7-127 FIFRP FIFRP Pointer -1 Pointer FPOP FPOP...
Page 54: Buffer Memory Access Instructions
2 INSTRUCTION TABLES MELSEC-Q/QnA 2.5.8 Buffer memory access instructions Table 2.25 Buffer Memory Access Instructions Execution Category Symbol Processing Details Condition • Reads data in 16-bit units from special FROM FROM n1 n2 D function module 7-134 FROMP FROMP n1 n2 D Data read •...
Page 55: Debugging And Failure Diagnosis Instructions
2 INSTRUCTION TABLES MELSEC-Q/QnA 2.5.10 Debugging and failure diagnosis instructions Table 2.27 Debugging and Failure Diagnosis Instructions Execution Category Symbol Processing Details Condition • CHK instruction is executed when CHKST is executable. CHKST CHKST • Jumps to the step following the CHK instruction when CHKST is in a non- executable status 7-155...
Page 56: Character String Processing Instructions
2 INSTRUCTION TABLES MELSEC-Q/QnA 2.5.11 Character string processing instructions Table 2.28 Character String Processing Instructions Execution Category Symbol Processing Details Condition • Converts 1-word BIN value designated BINDA BINDA by (S) to a 5-digit, decimal ASCII value, 7-173 and stores it at the word device designated by (D).
Page 57 2 INSTRUCTION TABLES MELSEC-Q/QnA Table 2.28 Character String Processing Instructions (Continued) Execution Category Symbol Processing Details Condition • Converts a 4-digit, decimal ASCII value DABCD DABCD designated by (S) to a 1-word BCD 7-187 value, and stores it at a word device DABCDP Decimal DABCDP S D...
Page 58 2 INSTRUCTION TABLES MELSEC-Q/QnA Table 2.28 Character String Processing Instructions (Continued) Execution Category Processing Details Symbol Condition • Converts 1-word BIN values of the device Hexadeci- number and later designated by (S) to mal BIN to ASCII, and stores only n characters of 7-218 ASCII them at the device number designated by...
Page 59: Special Function Instructions
2 INSTRUCTION TABLES MELSEC-Q/QnA 2.5.12 Special function instructions Table 2.29 Special Function Instructions Execution Category Symbol Processing Details Condition Sin (S+1, S) (D+1, D) 7-235 SINP SINP Cos (S+1, S) (D+1, D) 7-237 COSP COSP Tan (S+1, S) (D+1, D) Trigono- 7-239 metric...
Page 60 2 INSTRUCTION TABLES MELSEC-Q/QnA Table 2.29 Special Function Instructions (Continued) Execution Category Symbol Processing Details Condition (D)+0 Integer part BSQR BSQR Decimal fraction part 7-259 BSQRP BSQRP Square root (S+1, S) (D)+0 Integer part BDSQR BDSQR Decimal fraction part 7-259 BDSQRP BDSQRP S D Sin (S)
Page 61: Data Control Instructions
2 INSTRUCTION TABLES MELSEC-Q/QnA 2.5.13 Data control instructions Table 2.30 Data Control Instructions Execution Category Symbol Processing Details Condition • When (S3) < (S1) LIMIT LIMIT S1 S2 ....Store value of (S1) at (D) • When (S1) (S3) (S2) 7-274 ....
Page 62: Switching Instructions
2 INSTRUCTION TABLES MELSEC-Q/QnA 2.5.14 Switching instructions Table 2.31 Switching Instructions Execution Category Symbol Processing Details Condition Block • Converts extension file register block RSET RSET number number to number designated by (S). 7-283 designa- RSETP RSETP tions QDRSE • Sets file names used as file registers. QDRSET File Name 7-285...
Page 63: Clock Instructions
2 INSTRUCTION TABLES MELSEC-Q/QnA 2.5.15 Clock instructions Table 2.32 Clock Instructions Execution Category Symbol Processing Details Condition (Clock device) (D)+0 Year DATERD DATERD D Month Hour 7-289 Minute Sec. DATERDP DATERDP D +6 Day of week Read/write clock data (D)+0 Year (Clock device) DATEWR DATEWR S...
Page 64: Peripheral Device Instructions
2 INSTRUCTION TABLES MELSEC-Q/QnA 2.5.16 Peripheral device instructions Table 2.33 Peripheral Device Instructions Execution Category Symbol Processing Details Condition • Stores message designated by (S) at QnACPU. Input/ 7-303 This message is displayed at the output to peripheral peripheral device devices •...
Page 65: Other Instructions
2 INSTRUCTION TABLES MELSEC-Q/QnA 2.5.18 Other instructions Table 2.35 Other Instructions Execution Category Symbol Processing Details Condition • Resets watchdog timer during sequence program WDT reset 7-315 WDTP WDTP Timing n1 scan n2 scan DUTY DUTY n1 n2 D 7-317 clock SM420 to SM424, SM430 to SM434 Lower 8 bits...
Page 66: Instructions For Data Link
2 INSTRUCTION TABLES MELSEC-Q/QnA 2.5.19 Instructions for data link Table 2.36 Instructions for Data Link Execution Category Symbol Processing Details Condition J.ZCOM JP.ZCOM Jn Network ZCOM Refreshes the designated network. refresh G.ZCOM Un GP.ZCOM Un J.READ G.READ READ 8-12 QnA link JP.READ instruction: GP.READ...
Page 67 2 INSTRUCTION TABLES MELSEC-Q/QnA Table 2.36 Instructions for Data Link (Continued) Execution Category Symbol Processing Details Condition QnA link instruction: JP.ZNFR Reading Reads data from the special data from special ZNFR function modules at remote I/O 8-64 function stations. modules at GP.ZNFR remote I/O stations...
Page 68: Qcpu Instructions
2 INSTRUCTION TABLES MELSEC-Q/QnA 2.5.20 QCPU instructions Table 2.37 QCPU Instructions Execution Category Symbol Processing Details Condition • Reads the module information stored in UNIRD UNIRD n1 the area starting from the I/O No. Reading designated by (n) by the points module designated by (n2), and stores it in the information UNIRDP...
Page 69: Redundant System Instructions (For Q4Arcpu)
2 INSTRUCTION TABLES MELSEC-Q/QnA 2.5.21 Redundant system instructions (For Q4ARCPU) Table 2.38 Redundant system instructions (For Q4ARCPU) Execution Category Symbol Processing Details Condition Operation • Designates the operation mode at (S1) mode whether to clear the Q4ARCPU devices setting S.STMODE S.STMODE S1 S2 before startup or not to clear them 10-2...
Page 70: Configuration Of Instructions
3 CONFIGURATION OF INSTRUCTIONS MELSEC-Q/QnA 3. CONFIGURATION OF INSTRUCTIONS 3.1 Configuration of Instructions Most CPU module instructions consist of an instruction part and a device part. • Instruction part..Indicates the function of the instruction • Device part ..Indicates the data that is to be used with the instruction. The device part is classified into source data, destination data, and number of devices.
Page 71: Designating Data
3 CONFIGURATION OF INSTRUCTIONS MELSEC-Q/QnA (3) Number of devices and number of transfers (n) (a) The number of devices and number of transfers designate the numbers of devices and transfers used by instructions involving multiple devices. Example: Block transfer instruction BMOV Designates the number of transfers used by a BMOV instruction...
Page 72: Using Word (16 Bits) Data
3 CONFIGURATION OF INSTRUCTIONS MELSEC-Q/QnA (b) Word device bit designation is done by designating ” Word Device Bit No. ” . (Designation of bit numbers is done in hexadecimal.) For example, bit 5 (b5) of D0 is designated as D0.5, and bit 10 (b10) of D0 is designated as D0.A.
Page 73 3 CONFIGURATION OF INSTRUCTIONS MELSEC-Q/QnA XC XB X8 X7 X4 X3 K1 designation range (4 points) K2 designation range (8 points) K3 designation range (12 points) K4 designation range (16 points) Fig 3.1 Digit Designation Setting Range for 16-Bit Instruction (b) In cases where digit designation has been made at the source , the numeric values shown in Table 3.1 are those which can be dealt with as source data.
Page 74: Using Double Word Data (32 Bits)
3 CONFIGURATION OF INSTRUCTIONS MELSEC-Q/QnA (2) When using word devices Word devices are designated in 1-point (16 bits) units. MOV K100 1 D0 point (16 bits) is word device POINTS (1) When digit designation processing is conducted, a random value can be used for the bit device initial device number.
Page 75 3 CONFIGURATION OF INSTRUCTIONS MELSEC-Q/QnA X1F X1C X1B X18 X17 X14 X13 X10 XF XC XB X8 X7 X4 X3 K1 designation range (4 points) K2 designation range (8 points) K3 designation range (12 points) K4 designation range (16 points) K5 designation range (20 points) K6 designation range...
Page 76 3 CONFIGURATION OF INSTRUCTIONS MELSEC-Q/QnA (c) In cases where digit designation is made at the destination , the number of points designated are used as the destination. Bit devices after the number of points designated as digits do not change. Ladder Example Processing H78123456...
Page 77: Using Real Number Data
3 CONFIGURATION OF INSTRUCTIONS MELSEC-Q/QnA 3.2.4 Using real number data Real number data is 32-bit floating decimal point data used with basic instructions and application instructions. Only word devices are capable of storing real number data. Instructions which deal with real numbers designate devices which are used for the lower 16 bits of data.
Page 78: Using Character String Data
3 CONFIGURATION OF INSTRUCTIONS MELSEC-Q/QnA 3.2.5 Using character string data Character string data is character data used by basic instructions and application instructions. It encompasses all data from the designated character to the NULL code (00 (1) When designated character is the NULL code. One word is used to store the NULL code.
Page 79: Index Modification
3 CONFIGURATION OF INSTRUCTIONS MELSEC-Q/QnA 3.3 Index Modification (1) Index modification (a) Index modification is an indirect setting made by using an index register. When an index modification is used in a sequence program, the device to be used will become the device number designated directly plus the contents of the index register.
Page 80 3 CONFIGURATION OF INSTRUCTIONS MELSEC-Q/QnA (2) Devices which can be index-modified With the exception of the restrictions noted below, index modification can be used with devices used with contacts, coils, basic instructions, and application instructions. (a) Devices which cannot use index modification Device Meaning K, H...
Page 81 3 CONFIGURATION OF INSTRUCTIONS MELSEC-Q/QnA (c) Other 1) Bit data Device numbers can be index modified when performing digit designation. However, index modification is not possible by digit designation. BIN K4X0Z2 Setting that enables device number index modification If Z2 = 3, then X (0+3) = X3. BIN K4Z3X0 Setting that cannot enable digit designation index...
Page 82: Indirect Designation
3 CONFIGURATION OF INSTRUCTIONS MELSEC-Q/QnA 3.4 Indirect Designation (1) Indirect Designation (a) Indirect designation is a way of using a word device to designate a device address that will be used in a sequence program. This method can be used when the index register is insufficient. (b) The device which designates the designated device address is designated by "@+(word device number)".
Page 83 3 CONFIGURATION OF INSTRUCTIONS MELSEC-Q/QnA (2) Devices Capable of Indirect Designation The CPU module devices that can be designated indirectly is shown in Table 3.3. Table 3.3 List of Devices Capable of Indirect Designation Capable/Incapable of Example of Indirect Device Type Indirect Designation Designation Bit devices...
Page 84: Subset Processing
3 CONFIGURATION OF INSTRUCTIONS MELSEC-Q/QnA 3.5 Subset Processing Subset processing is used to place limits on bit devices used by basic instructions and application instructions in order to increase processing speed. However, the instruction symbol does not change. To shorten scans, run instructions under the conditions indicated below. (1) Conditions which each device must meet for subset processing (a) When using word data Device...
Page 85: Cautions On Programming (Operation Errors)
3 CONFIGURATION OF INSTRUCTIONS MELSEC-Q/QnA 3.6 Cautions on Programming (Operation Errors) Operation errors are returned in the following cases when executing basic instructions and application instructions with CPU module: • An error listed on the explanatory page for the individual instruction occurred. •...
Page 86 3 CONFIGURATION OF INSTRUCTIONS MELSEC-Q/QnA Device range checks are also conducted when index modification is performed. However, if index modification has been conducted, there will be no error returned if the initial device number exceeds the relevant device range. BMOV K100 D12285Z1 K2 D12287 and D12288 have been indicated here, but because D12288 does not exist, an operation error is returned.
Page 87 3 CONFIGURATION OF INSTRUCTIONS MELSEC-Q/QnA (3) If internal user device allocation is changed by parameter device allocation, such allocations are made in the device order indicated below: If the allocation of the device used is less than 28.75 k words, the area following the device used will be empty.
Page 88: Conditions For Execution Of Instructions
3 CONFIGURATION OF INSTRUCTIONS MELSEC-Q/QnA 3.7 Conditions for Execution of Instructions The following four types of execution conditions exist for the execution of CPU module sequence instructions, basic instructions, and application instructions: • Non-conditional execution....Instructions executed without regard to the ON/OFF status of the device Example: LD X0, OUT Y10 •...
Page 89: Counting Step Number
3 CONFIGURATION OF INSTRUCTIONS MELSEC-Q/QnA 3.8 Counting Step Number The number of steps in CPU module sequence instructions, basic instructions, and application instructions differs depending on whether indirect setting of the device used is possible or not. The basic number of steps for basic instructions and application instructions is calculated by adding the device number and 1.
Page 90: Operation When Out, Set/Rst, Or Pls/Plf Instructions Use The Same Device
3 CONFIGURATION OF INSTRUCTIONS MELSEC-Q/QnA 3.9 Operation when OUT, SET/RST, or PLS/PLF Instructions Use the Same Device The following describes the operation for executing multiple instructions of OUT, SET/RST, or PLS/PLF that use the same device in one scan. (1) OUT instructions using the same device Do not program more than one OUT instruction using the same device in one scan.
Page 91 3 CONFIGURATION OF INSTRUCTIONS MELSEC-Q/QnA (2) SET/RST instructions using the same device (a) The SET instruction turns ON the specified device when the SET command is ON and does not do anything when the SET command is OFF. For this reason, when two or more SET instructions use the same device in one scan, the specified device will be ON if any one of the SET commands is ON.
Page 92 3 CONFIGURATION OF INSTRUCTIONS MELSEC-Q/QnA (3) PLS instructions using the same device The PLS instruction turns ON the specified device when the PLS command turns ON from OFF. It turns OFF the specified device at any other time (OFF OFF, ON ON, and ON OFF).
Page 93 3 CONFIGURATION OF INSTRUCTIONS MELSEC-Q/QnA (4) PLF instructions using the same device The PLF instruction turns ON the specified device when the PLF command turns ON from OFF. It turns OFF the specified device at any other time (OFF OFF, OFF ON, and ON ON).
Page 94 4 HOW TO READ INSTRUCTIONS MELSEC-Q/QnA 4. HOW TO READ INSTRUCTIONS The description of instructions that are contained in the following chapters are presented in the following format. Code used to write instruction (instruction symbol). Section number and general category of instructions being discussed. Devices which can be used by the instruction in question are indicated with circle.
Page 95 4 HOW TO READ INSTRUCTIONS MELSEC-Q/QnA : Refer to the User's Manual (Functions Explanation, Programming Fundamentals) of the used CPU or QnA Programming Manual for details of each device. : When T, ST and C are used for other than the instructions below, only word data can be used. (Bit data cannot be used .) [Instructions that can be used with bit data] LD, LDI, AND, ANI, OR, ORI, LDP, LDF, ANDP, ANDF, ORP, ORF, OUT, RST...
Page 96 4 HOW TO READ INSTRUCTIONS MELSEC-Q/QnA Discusses the data set for each instruction and the data type. Data Type Meaning Bit data or first number in bit data BIN 16 bits BIN 16-bit data or first number in word device BIN 32 bits BIN 32-bit data or first number in double word device BCD 4 digits...
Page 97: Sequence Instructions
5 SEQUENCE INSTRUCTIONS MELSEC-Q/QnA 5. SEQUENCE INSTRUCTIONS Sequence instructions include instructions for relay control ladders and the like. They are divided into the following categories: Instruction Meaning Reference Contact instruction Operation start, series connection, parallel connection Chapter 5.1 Ladder block connection, creation of pulses from operation Connection Instruction Chapter 5.2 results, store/read operation results...
Page 98: Contact Instructions
5 SEQUENCE INSTRUCTIONS MELSEC-Q/QnA QCPU Q4AR PLC CPU Process CPU Basic High Performanc e 5.1 Contact Instructions 5.1.1 Operation start, series connection, parallel connection (LD, LDI, AND, ANI, OR, ORI) Usable Devices Internal Devices MELSECNET/10(H) Special Index Other (System, User) File Direct J \ Function...
Page 99 5 SEQUENCE INSTRUCTIONS MELSEC-Q/QnA AND, ANI (1) AND is the A contact series connection instruction, and ANI is the B contact series connection instruction. They read the ON/OFF data of the designated bit device (if a bit designation has been made for a word device, the 1/0 status of the designated bit is read), perform an AND operation on that data and the operation result to that point, and take this value as the operation result.
Page 100 5 SEQUENCE INSTRUCTIONS MELSEC-Q/QnA [Operation Errors] (1) There are no operation errors with LD, LDI, AND, ANI, OR, or ORI instructions. [Program Example] (1) A program using LD, AND, OR, and ORI instructions. [Ladder Mode] [List Mode] Steps Instruction Device ···Word device bit designa-...
Page 101: Pulse Operation Start, Pulse Series Connection, Pulse Parallel Connection (Ldp, Ldf, Andp, Andf, Orp, Orf)
5 SEQUENCE INSTRUCTIONS MELSEC-Q/QnA QCPU PLC CPU Q4AR Process CPU Basic High Performance 5.1.2 Pulse operation start, pulse series connection, pulse parallel connection (LDP, LDF, ANDP, ANDF, ORP, ORF) Usable Devices Internal Devices MELSECNET/10(H) Special Index Other (System, User) File Direct J \ Function Constant...
Page 102 5 SEQUENCE INSTRUCTIONS MELSEC-Q/QnA (2) LDF is the trailing edge pulse operation start instruction, and is ON only at the trailing edge of the designated bit device (when it goes from ON to OFF). If a word device has been designated, it is ON only when the designated bit changes from 1 to ANDP, ANDF (1) ANDP is a leading edge pulse series connection instruction, and ANDF is a trailing edge pulse series connection instruction.
Page 103: Connection Instructions
5 SEQUENCE INSTRUCTIONS MELSEC-Q/QnA QCPU PLC CPU Q4AR Process CPU Basic High Performance 5.2 Connection Instructions 5.2.1 Ladder block series connections and parallel connections (ANB, ORB) Usable Devices Internal Devices MELSECNET/10(H) Special Index (System, User) File Direct J \ Function Constant Data Register...
Page 104 5 SEQUENCE INSTRUCTIONS MELSEC-Q/QnA (2) ORB is used to perform parallel connections for ladder blocks with two or more contacts. For ladder blocks with only one contact, use OR or ORI; there is no need for ORB in such cases. [Ladder Mode] [List Mode] AND X1...
Page 105: Operation Results Push, Read, Pop (Mps, Mrd, Mpp)
5 SEQUENCE INSTRUCTIONS MELSEC-Q/QnA QCPU PLC CPU Q4AR Process CPU Basic High Performance 5.2.2 Operation results push, read, pop (MPS, MRD, MPP) Usable Devices Internal Devices MELSECNET/10(H) Special Index (System, User) File Direct J \ Function Constant Data Register Other Register Module K, H...
Page 106 5 SEQUENCE INSTRUCTIONS MELSEC-Q/QnA POINTS (1) The following shows ladders both using and not using the MPS, MRD, and MPP instructions. Ladder Using the MPS, MRD and MPP Instruction. Ladder not Using MPS, MRD, and MPP Instructions. (2) The MPS and MPP instructions must be used the same number of times. Failure to observe this will not correctly display the ladder in the ladder mode of the peripheral device.
Page 107 5 SEQUENCE INSTRUCTIONS MELSEC-Q/QnA [Operation Errors] (1) There are no errors associated with the MPS, MRD, or MPP instructions. [Program Example] (1) A program using the MPS, MRD, and MPP instructions. [Ladder Mode] [List Mode] Instruction Device Steps 5 - 11 5 - 11 Artisan Technology Group - Quality Instrumentation ...
Page 108 5 SEQUENCE INSTRUCTIONS MELSEC-Q/QnA (2) A program using MPS and MPP instructions successively. [Ladder Mode] [List Mode] Instruction Device Steps 5 - 12 5 - 12 Artisan Technology Group - Quality Instrumentation ... Guaranteed | (888) 88-SOURCE | www.artisantg.com...
Page 109: Operation Results Inversion (Inv)
5 SEQUENCE INSTRUCTIONS MELSEC-Q/QnA QCPU PLC CPU Q4AR Process CPU Basic High Performance 5.2.3 Operation results inversion (INV) Usable Devices Internal Devices MELSECNET/10(H) Special Index Other (System, User) File Direct J \ Function Constant Data Register Register Module K, H Word Word U \G...
Page 110: Operation Result Pulse Conversion (Mep, Mef)
5 SEQUENCE INSTRUCTIONS MELSEC-Q/QnA QCPU PLC CPU Q4AR Process CPU Basic High Performance 5.2.4 Operation result pulse conversion (MEP, MEF) Usable Devices Internal Devices MELSECNET/10(H) Special Index Other (System, User) File Direct J \ Function Constant Data Register Register Module K, H Word Word...
Page 111 5 SEQUENCE INSTRUCTIONS MELSEC-Q/QnA POINTS (1) The MEP and MEF instructions will occasionally not function properly when pulse conversion is conducted for a contact that has been indexed by a sub-routine program or by the FOR to NEXT instructions. If pulse conversion is to be conducted for a contact that has been indexed by a sub-routine program or by the FOR to NEXT instructions, use the EGP/EGF instructions.
Page 112: Pulse Conversion Of Edge Relay Operation Results (Egp, Egf)
5 SEQUENCE INSTRUCTIONS MELSEC-Q/QnA QCPU PLC CPU Q4AR Process CPU Basic High Performance 5.2.5 Pulse conversion of edge relay operation results (EGP, EGF) Usable Devices Internal Devices MELSECNET/10(H) Special Index Other (System, User) File Direct J \ Function Constant Data Register Register Module...
Page 113 5 SEQUENCE INSTRUCTIONS MELSEC-Q/QnA [Operation Errors] (1) There are no operation errors associated with the EGP or EGF instructions. [Program Example] (1) A program containing a subroutine program using an EGP instruction [Ladder Mode] [List Mode] Steps Instruction Device [Operation] END processing Turns OFF as X0 remains ON.
Page 114: Out Instructions
5 SEQUENCE INSTRUCTIONS MELSEC-Q/QnA QCPU PLC CPU Q4AR Process CPU Basic High Performance 5.3 Out Instructions 5.3.1 Out instructions (excluding timers, counters, and annunciators) (OUT) Usable Devices Internal Devices MELSECNET/10(H) Special Index Other (System, User) File Direct J \ Function Constant Data Register...
Page 115 5 SEQUENCE INSTRUCTIONS MELSEC-Q/QnA [Program Example] (1) When bit device is in use [Ladder Mode] [List Mode] Instruction Device Steps (2) When bit designation has been made for word device [Ladder Mode] [List Mode] Instruction Device Steps REMARK The number of basic steps for OUT instructions is as follows: •...
Page 116: Timers (Out T, Outh T)
5 SEQUENCE INSTRUCTIONS MELSEC-Q/QnA QCPU PLC CPU Q4AR Process CPU Basic High Performance 5.3.2 Timers (OUT T, OUTH T) Usable Devices Internal Devices MELSECNET/10(H) Special Index (System, User) File Direct J \ Function Constant Data Register Other Register Module Word Word U \G (Only T)
Page 117 5 SEQUENCE INSTRUCTIONS MELSEC-Q/QnA [Set Data] Set Data Meaning Data Type Timer number Set value Value set for timer BIN 16 bits POINT 3: The value setting for the timer cannot be designated indirectly. Indirect designation not possible @ D0 See Section 3.4 for further information on indirect designations.
Page 118 5 SEQUENCE INSTRUCTIONS MELSEC-Q/QnA REMARKS (1) The default value for the low speed timer and low speed retentive timer time limit is 100 ms. The time limit for the low speed timer and low speed retentive timer can be set in the parameter mode "PLC system settings"...
Page 119 5 SEQUENCE INSTRUCTIONS MELSEC-Q/QnA [Program Example] (1) The following program turns Y10 and Y14 ON 10 seconds after X0 has gone ON. [Ladder Mode] [List Mode] Instruction Device Steps (2) The following program uses the BCD data at X10 to 1F as the timer's set value. [Ladder Mode] Converts BCD data at X10 to 1F to BIN and stores at D10...
Page 120: Counters (Out C)
5 SEQUENCE INSTRUCTIONS MELSEC-Q/QnA QCPU PLC CPU Q4AR Process CPU Basic High Performance 5.3.3 Counters (OUT C) Usable Devices Internal Devices MELSECNET/10(H) Special Index Other (System, User) File Direct J \ Function Constant Data Register Register Module Word Word U \G (Only C) (Other value...
Page 121 5 SEQUENCE INSTRUCTIONS MELSEC-Q/QnA (2) No count is conducted with the operation results at ON. (There is no need to perform pulse conversion on count input.) (3) After the count up status is reached, there is no change in the count value or the contacts until the RST instruction is executed.
Page 122: Annunciator Output (Out F)
5 SEQUENCE INSTRUCTIONS MELSEC-Q/QnA QCPU PLC CPU Q4AR Process CPU Basic High Performance 5.3.4 Annunciator output (OUT F) Usable Devices Internal Devices MELSECNET/10(H) Special Index (System, User) File Direct J \ Function Constant Data Register Other Register Module K, H Word Word U \G...
Page 123 5 SEQUENCE INSTRUCTIONS MELSEC-Q/QnA (4) The following responses occur when the annunciator is turned OFF by the OUT instruction. [With Q3A, Q4A, or Q4ARCPU] • The coil goes OFF, but there are no changes in the LED display device on the front of the CPU module, the status of the "USER"...
Page 124: Setting Devices (Except For Annunciators) (Set)
5 SEQUENCE INSTRUCTIONS MELSEC-Q/QnA QCPU PLC CPU Q4AR Process CPU Basic High Performance 5.3.5 Setting devices (except for annunciators) (SET) Usable Devices Internal Devices MELSECNET/10(H) Special Index Other (System, User) File Direct J \ Function Constant Data Register Register Module K, H Word Word...
Page 125 5 SEQUENCE INSTRUCTIONS MELSEC-Q/QnA [Operation Errors] (1) There are no operation errors associated with the SET instruction. [Program Example] (1) The following program sets Y8B (ON) when X8 goes ON, and resets Y8B (OFF) when X9 goes ON. [Ladder Mode] [List Mode] Instruction Device...
Page 126: Resetting Devices (Except For Annunciators) (Rst)
5 SEQUENCE INSTRUCTIONS MELSEC-Q/QnA QCPU PLC CPU Q4AR Process CPU Basic High Performance 5.3.6 Resetting devices (except for annunciators) (RST) Usable Devices Internal Devices MELSECNET/10(H) Special Index Other (System, User) File Direct J \ Function Constant Data Register Register Module K, H Word Word...
Page 127 5 SEQUENCE INSTRUCTIONS MELSEC-Q/QnA b) For word processing • Internal device (word to be specified by bit device) • Index resister • Other than above [Program Example] (1) The following program sets the value of the data register to 0. [Ladder Mode] When X0 goes ON, the contents of X10 to 1F are stored at D8...
Page 128: Setting And Resetting The Annunciators (Set F, Rst F)
5 SEQUENCE INSTRUCTIONS MELSEC-Q/QnA QCPU PLC CPU Q4AR Process CPU Basic High Performance 5.3.7 Setting and resetting the annunciators (SET F, RST F) Usable Devices Internal Devices MELSECNET/10(H) Special Index Other (System, User) File Direct J \ Function Constant Data Register Register Module...
Page 129 5 SEQUENCE INSTRUCTIONS MELSEC-Q/QnA (2) The table below shows which CPU module features either the LED display device on front of the CPU module or "USER" LED Type of LED CPU module Type Name LED display device Q3A, Q4A, Q4AR "USER LED"...
Page 130: Leading Edge And Trailing Edge Output (Pls, Plf)
5 SEQUENCE INSTRUCTIONS MELSEC-Q/QnA QCPU PLC CPU Q4AR Process CPU Basic High Performance 5.3.8 Leading edge and trailing edge output (PLS, PLF) Usable Devices Internal Devices MELSECNET/10(H) Special Index Other (System, User) File Direct J \ Function Constant Data Register Register Module K, H...
Page 131 5 SEQUENCE INSTRUCTIONS MELSEC-Q/QnA (1) When turned from ON to OFF, the PLF command turns ON the specified device, and other than when turned from ON to OFF (i.e. from OFF to OFF, from OFF to ON or from ON to ON), it turns OFF the specified device.
Page 132: Bit Device Output Reverse (Ff)
5 SEQUENCE INSTRUCTIONS MELSEC-Q/QnA QCPU PLC CPU Q4AR Process CPU Basic High Performance 5.3.9 Bit device output reverse (FF) Usable Devices Internal Devices MELSECNET/10(H) Special Index Other (System, User) File Direct J \ Function Constant Data Register Register Module K, H Word Word U \G...
Page 133 5 SEQUENCE INSTRUCTIONS MELSEC-Q/QnA (2) The following program reverses b10 (bit 10) of D10 when X0 goes ON. [Ladder Mode] [List Mode] Device Steps Instruction [Timing Chart] b10 of D10 5 - 37 5 - 37 Artisan Technology Group - Quality Instrumentation ... Guaranteed | (888) 88-SOURCE | www.artisantg.com...
Page 134: Pulse Conversion Of Direct Output (Delta, Deltap)
5 SEQUENCE INSTRUCTIONS MELSEC-Q/QnA QCPU PLC CPU Q4AR Process CPU Basic High Performance 5.3.10 Pulse conversion of direct output (DELTA, DELTAP) Usable Devices Internal Devices MELSECNET/10(H) Special Index Other (System, User) File Direct J \ Function Constant Data Register Register Module K, H Word...
Page 135 5 SEQUENCE INSTRUCTIONS MELSEC-Q/QnA [Operation Errors] (1) In the following cases an operation error occurs, the error flag (SM0) turns ON, and an error code is stored at SD0. • A direct access output number designated by has exceeded the CPU output range. (Error code: 4101) [Program Example] (1) The following program presets CH1 of the AD61 mounted at slot 0 of the main base unit, when...
Page 136: Shift Instruction
5 SEQUENCE INSTRUCTIONS MELSEC-Q/QnA QCPU PLC CPU Q4AR Process CPU Basic High Performance 5.4 Shift Instruction 5.4.1 Bit device shift (SFT, SFTP) Usable Devices Internal Devices MELSECNET/10(H) Special Index Other (System, User) File Direct J \ Function Constant Data Register Register Module K, H...
Page 137 5 SEQUENCE INSTRUCTIONS MELSEC-Q/QnA (2) When word device bit designation is used (a) Shifts to a bit in the device designated by the 1/0 status of the bit immediately prior to the one designated, and turns the prior bit to 0. For example, if D0.5 (bit 5 [b5] of D0) has been designated by the SFT instruction, when the SFT instruction is executed, it will shift the 1/0 status of b4 of D0 to b5, and turn b4 to 0.
Page 138: Master Control Instructions
5 SEQUENCE INSTRUCTIONS MELSEC-Q/QnA QCPU PLC CPU Q4AR Process CPU Basic High Performance 5.5 Master Control Instructions 5.5.1 Setting and resetting the master control (MC, MCR) Usable Devices Internal Devices MELSECNET/10(H) Special Index Other (System, User) File Direct J \ Function Constant Data...
Page 139 5 SEQUENCE INSTRUCTIONS MELSEC-Q/QnA REMARK : When programming in the ladder mode of a peripheral device, it is not necessary to input contacts on the vertical bus. These will be automatically displayed when the "conversion" operation is conducted after the creation of the ladder and then “read”...
Page 140 5 SEQUENCE INSTRUCTIONS MELSEC-Q/QnA [Program Example] The master control instruction can be used in nesting. The different master control regions are distinguished by nesting (N). Nesting can be performed from N0 to N14. The use of nesting enables the creation of ladders which successively limit the execution condition of the program.
Page 141 5 SEQUENCE INSTRUCTIONS MELSEC-Q/QnA Cautions when Using Nesting Architecture (1) Nesting can be used up to 15 times (N0 to N14) When using nesting, nests should be inserted from the lower to higher nesting number (N) with the MC instruction, and from the higher to the lower order with the MCR instruction. If this order is reversed, there will be no nesting architecture, and the QnACPU will not be capable of performing correct operations.
Page 142: Termination Instructions
5 SEQUENCE INSTRUCTIONS MELSEC-Q/QnA QCPU PLC CPU Q4AR Process CPU Basic High Performance 5.6 Termination Instructions 5.6.1 End main routine program (FEND) Usable Devices Internal Devices MELSECNET/10(H) Special Index (System, User) File Direct J \ Function Data Register Constant Other Register Module Word...
Page 143 5 SEQUENCE INSTRUCTIONS MELSEC-Q/QnA • A FEND instruction is executed during an interrupt program, and before the execution of an IRET instruction. (Error code: 4221) • A FEND instruction is executed between the CHKCIR and CHKEND instructions. (Error code: 4230) •...
Page 144: End Sequence Program (End)
5 SEQUENCE INSTRUCTIONS MELSEC-Q/QnA QCPU PLC CPU Q4AR Process CPU Basic High Performance 5.6.2 End sequence program (END) Usable Devices Internal Devices MELSECNET/10(H) Special Index Other (System, User) File Direct J \ Function Constant Data Register Register Module K, H Word Word U \G...
Page 145 5 SEQUENCE INSTRUCTIONS MELSEC-Q/QnA (4) The use of the END and FEND instructions is broken down as follows for main routine programs, subroutine programs, and interrupt programs: Main routine program FEND (FEND instruction is necessary.) Subroutine program Main sequence program area Interrupt program (END instruction is necessary.) [Operation Errors]...
Page 146: Other Instructions
5 SEQUENCE INSTRUCTIONS MELSEC-Q/QnA QCPU PLC CPU Q4AR Process CPU Basic High Performance 5.7 Other Instructions 5.7.1 Sequence program stop (STOP) Usable Devices Internal Devices MELSECNET/10(H) Special Index Other (System, User) File Direct J \ Function Constant Data Register Register Module K, H Word...
Page 147 5 SEQUENCE INSTRUCTIONS MELSEC-Q/QnA [Program Example] (1) The following program stops the CPU module when X8 goes ON [Ladder Mode] Causes programmable controller to stop when X8 goes ON. Sequence program [List Mode] Device Steps Instruction 5 - 51 5 - 51 Artisan Technology Group - Quality Instrumentation ...
Page 148: No Operation (Nop, Noplf
5 SEQUENCE INSTRUCTIONS MELSEC-Q/QnA QCPU PLC CPU Q4AR Process CPU Basic High Performance 5.7.2 No operation (NOP, NOPLF, PAGE n) Usable Devices Internal Devices MELSECNET/10(H) Special Index (System, User) File Direct J \ Function Constant Data Register Other Register Module K, H Word Word...
Page 149 5 SEQUENCE INSTRUCTIONS MELSEC-Q/QnA PAGE n (1) This is a no operation instruction that has no impact on any operations up to that point. (2) Causes processing from step 0 of the designated nth page of the program following the PAGE n instruction.
Page 150 5 SEQUENCE INSTRUCTIONS MELSEC-Q/QnA Before change [List Mode] [Ladder Mode] 0 X0 Steps Instruction Device Changed to LD T3 Changed to NOP After change [List Mode] [Ladder Mode] Steps Instruction Device NOPLF [List Mode] [Ladder Mode] Steps Instruction Device NOPLF NOPLF 5 - 54 5 - 54...
Page 151 5 SEQUENCE INSTRUCTIONS MELSEC-Q/QnA • Printing the ladder will result in the following: X000 NOPLF Page change forced when NOPLF is inserted between two ladder blocks. —1— X001 X001 • Printing an instruction list with the NOPLF instruction will result in the following: X000 NOPLF Changes pages after printing NOPLF...
Page 152: Basic Instructions
6 BASIC INSTRUCTIONS MELSEC-Q/QnA 6. BASIC INSTRUCTIONS The following types of basic instructions are available. Instruction Meaning Reference Section Comparison operation Compare data to data Chapter 6.1 instruction Arithmetic operation Adds, subtracts multiplies, divides, increments, or Chapter 6.2 instructions decrements data with other data Data conversion instruction Converts data types Chapter 6.3...
Page 153: Comparison Operation Instruction
6 BASIC INSTRUCTIONS MELSEC-Q/QnA QCPU PLC CPU Q4AR Process CPU Basic High Performance 6.1 Comparison Operation Instruction 6.1.1 BIN 16-bit data comparisons (=, < >, >, <=, <, >=) Usable Devices Internal Devices MELSECNET/10(H) Special Index (System, User) File Direct J \ Function Constant Data...
Page 154 6 BASIC INSTRUCTIONS MELSEC-Q/QnA [Operation Errors] (1) There are no operation errors associated with the =, <>, >, <=, <, or >= instructions. [Program Example] (1) The following program compares the data at X0 to XF with the data at D3, and turns Y33 ON if the data is identical.
Page 155 6 BASIC INSTRUCTIONS MELSEC-Q/QnA QCPU PLC CPU Q4AR Process CPU Basic High Performance 6.1.2 BIN 32-bit data comparisons (D = , D < > , D > , D <= ,D < , D >= ) Usable Devices Internal Devices MELSECNET/10(H) Special Index...
Page 156 6 BASIC INSTRUCTIONS MELSEC-Q/QnA [Operation Errors] (1) There are no operation errors associated with the =, <>, >, <=, <, or >= instructions. [Program Example] (1) The following program compares the data at X0 to XF with the data at D3, and turns Y33 ON if the data is identical.
Page 157 6 BASIC INSTRUCTIONS MELSEC-Q/QnA QCPU PLC CPU Q4AR Process CPU Basic High Performance 6.1.3 Floating decimal point data comparisons (E = , E < > , E>, E <= , E < , E >= ) Usable Devices Internal Devices MELSECNET/10(H) Special Index...
Page 158 6 BASIC INSTRUCTIONS MELSEC-Q/QnA [Operation Errors] (1) There are no operation errors associated with the E=, E< >, E>, E<=, E<, or, E>= instructions. [Program Example] (1) The following program compares floating decimal point real number data at D0 and D1 to floating decimal point real number data at D3 and D4.
Page 159: Character String Data Comparisons ($=, $< >, $>, $<=, $<, $>=)
6 BASIC INSTRUCTIONS MELSEC-Q/QnA QCPU PLC CPU Q4AR Process CPU Basic High Performance 6.1.4 Character string data comparisons ($ = , $< > , $ > , $ <= , $ < , $ >= ) Usable Devices Internal Devices MELSECNET/10(H) Special Index...
Page 160 6 BASIC INSTRUCTIONS MELSEC-Q/QnA (b) If the character strings are different, the character string with the larger character code will be the larger. b15- - - -b8 b7- - - - b0 b15- - - -b8 b7- - - - b0 "ABCDF"...
Page 161 6 BASIC INSTRUCTIONS MELSEC-Q/QnA [Operation Errors] (1) In the following cases an operation error occurs, the error flag (SM0) turns ON, and an error code is stored at SD0. • The code “00H” or non-matching does not exist within the relevant device range following the device number designated by .
Page 162 6 BASIC INSTRUCTIONS MELSEC-Q/QnA (3) The following program compares the character string stored following D10 with the character string stored following D100. [Ladder Mode] [List Mode] Steps Instruction Device (4) The following program compares the character string stored following D10 with the character string "12345."...
Page 163: Bin Block Data Comparisons (Bkcmp, Bkcmpp)
6 BASIC INSTRUCTIONS MELSEC-Q/QnA QCPU PLC CPU Q4AR Process CPU Basic High Performance 6.1.5 BIN block data comparisons (BKCMP, BKCMP P) Usable Devices Internal Devices MELSECNET/10(H) Special Index (System, User) File Direct J \ Function Constant Data Register Other Register Module K, H Word...
Page 164 6 BASIC INSTRUCTIONS MELSEC-Q/QnA (2) The comparison operation is conducted in 16-bit units. (3) The constant designated by can be between -32768 and 32767 (BIN 16-bit data). Operation Results 32000 (BIN) 4321 (BIN) 32000 (BIN) 32000 (BIN) +(n-2) 1234 (BIN) +(n-2) +(n-1) 5678...
Page 165 6 BASIC INSTRUCTIONS MELSEC-Q/QnA [Program Example] (1) The following program performs a comparison operation when X20 goes ON, comparing the data for the number of points from D100 equivalent to the value stored in D0 with the data the number of points from R0 equivalent to the value stored in D0, and stores the result from M10 onward.
Page 166 6 BASIC INSTRUCTIONS MELSEC-Q/QnA (3) When X20 goes ON, compares the data 3 points from D10 with the data 3 points from D30, and stores the result from M100 onward. The following program transfers the character string "ALL ON" to D100 onward when all devices from M100 onward have reached the 1 "ON"...
Page 167: Arithmetic Operation Instructions
6 BASIC INSTRUCTIONS MELSEC-Q/QnA QCPU PLC CPU Q4AR Process CPU Basic High Performance 6.2 Arithmetic Operation Instructions 6.2.1 BIN 16-bit addition and subtraction operations (+, +P, -, -P) Usable Devices Internal Devices MELSECNET/10(H) Special Index (System, User) File Direct J \ Function Constant Data...
Page 168 6 BASIC INSTRUCTIONS MELSEC-Q/QnA (4) The following will happen when an underflow or overflow is generated in an operation result: The carry flag in this case does not go ON. • K32767 K-32767..A negative value is generated if b15 is 1. (H7FFF) (H0002) (H8001)
Page 169 6 BASIC INSTRUCTIONS MELSEC-Q/QnA Usable Devices Internal Devices MELSECNET/10(H) Special Index (System, User) File Direct J \ Function Constant Data Register Other Register Module K, H Word Word U \G indicates the signs +/− [Instruction Symbol] [Execution Condition] Command +, - Command +P, -P [Set Data]...
Page 170 6 BASIC INSTRUCTIONS MELSEC-Q/QnA (1) Subtracts 16-bit BIN data designated by from 16-bit BIN data designated by and stores the result of the subtraction at the device designated by b15- - - - - - - - -b0 b15- - - - - - - - -b0 b15- - - - - - - - -b0 5678 (BIN) 1234 (BIN)
Page 171: Bin 32-Bit Addition And Subtraction Operations (D+, D+P, D-, D-P)
6 BASIC INSTRUCTIONS MELSEC-Q/QnA QCPU PLC CPU Q4AR Process CPU Basic High Performance 6.2.2 BIN 32-bit addition and subtraction operations (D+, D+P, D-, D-P) Usable Devices Internal Devices MELSECNET/10(H) Special Index (System, User) File Direct J \ Function Constant Data Register Other Register...
Page 172 6 BASIC INSTRUCTIONS MELSEC-Q/QnA (4) The following will happen when an underflow or overflow is generated in an operation result: The carry flag in this case does not go ON. • K2147483647 K-2147483647..Because b31 is 1, (H2) (H80000001) (H7FFFFFFF) the value is negative. •...
Page 173 6 BASIC INSTRUCTIONS MELSEC-Q/QnA Usable Devices Internal Devices MELSECNET/10(H) Special Index (System, User) File Direct J \ Function Constant Data Register Other Register Module K, H Word Word U \G [Instruction Symbol] [Execution Condition] indicates the signs D+/D- Command D+, D- Command D+P, D-P [Set Data]...
Page 174 6 BASIC INSTRUCTIONS MELSEC-Q/QnA (1) Subtracts 32-bit BIN data designated by from 32-bit BIN data designated by and stores the result of the subtraction at the device designated by b31- -b16 b15- -b0 b31- -b16 b15- -b0 b31- -b16 b15- -b0 567890 (BIN) 123456 (BIN) 444434 (BIN)
Page 175: Bin 16-Bit Multiplication And Division Operations ( , P, /, /P)
6 BASIC INSTRUCTIONS MELSEC-Q/QnA QCPU PLC CPU Q4AR Process CPU Basic High Performance 6.2.3 BIN 16-bit multiplication and division operations ( , P, /, /P) Usable Devices Internal Devices MELSECNET/10(H) Special Index (System, User) File Direct J \ Function Constant Data Register Other...
Page 176 6 BASIC INSTRUCTIONS MELSEC-Q/QnA (1) Divides BIN 16-bit data designated by and BIN 16-bit data designated by , and stores the result in the device designated by Quotient Remainder b15- - - - - - - - - b0 b15- - - - - - - - - b0 b15- - - - b0 b15- - - - b0 5678 (BIN)
Page 177: Bin 32-Bit Multiplication And Division Operations (D , D P, D/, D/P)
6 BASIC INSTRUCTIONS MELSEC-Q/QnA QCPU PLC CPU Q4AR Process CPU Basic High Performance 6.2.4 BIN 32-bit multiplication and division operations (D , D P, D/, D/P) Usable Devices Internal Devices MELSECNET/10(H) Special Index (System, User) File Direct J \ Function Constant Data Register...
Page 178 6 BASIC INSTRUCTIONS MELSEC-Q/QnA (4) Judgment whether values for , and are positive or negative are made on the basis of the most significant bit (b31 for , and b63 for • 0 ..Positive • 1 ..Negative (1) Divides BIN 32-bit data designated by and BIN 32-bit data designated by , and stores the result in the device designated by...
Page 179: Bcd 4-Digit Addition And Subtraction Operations (B+, B+P, B-, B-P)
6 BASIC INSTRUCTIONS MELSEC-Q/QnA QCPU PLC CPU Q4AR Process CPU Basic High Performance 6.2.5 BCD 4-digit addition and subtraction operations (B+, B+P, B-, B-P) Usable Devices Internal Devices MELSECNET/10(H) Special Index (System, User) File Direct J \ Function Constant Data Register Other Register...
Page 180 6 BASIC INSTRUCTIONS MELSEC-Q/QnA (2) The values for can be between 0 to 9999 (BCD 4-digit). (3) The following will result if an underflow is generated by the subtraction operation: The carry flag in this case does not go ON. [Operation Errors] (1) In the following cases an operation error occurs, the error flag (SM0) turns ON, and an error code is stored at SD0.
Page 181 6 BASIC INSTRUCTIONS MELSEC-Q/QnA Usable Devices Internal Devices MELSECNET/10(H) Special Index (System, User) File Direct J \ Function Constant Data Register Other Register Module K, H Word Word U \G [Instruction Symbol] [Execution Condition] indicates the signs B+ or B- Command B+,B- Command...
Page 182 6 BASIC INSTRUCTIONS MELSEC-Q/QnA (2) The values for , and can be between 0 to 9999 (BCD 4-digit data). (3) The following will result if an underflow is generated by the subtraction operation: The carry flag in this case does not go ON. [Operation Errors] (1) In the following cases an operation error occurs, the error flag (SM0) turns ON, and an error code is stored at SD0.
Page 183: Bcd 8-Digit Addition And Subtraction Operations (Db+, Db+P, Db-, Db-P)
6 BASIC INSTRUCTIONS MELSEC-Q/QnA QCPU PLC CPU Q4AR Process CPU Basic High Performance 6.2.6 BCD 8-digit addition and subtraction operations (DB+, DB+P, DB-, DB-P) Usable Devices Internal Devices MELSECNET/10(H) Special Index (System, User) File Direct J \ Function Constant Data Register Other Register...
Page 184 6 BASIC INSTRUCTIONS MELSEC-Q/QnA (2) The values for can be between 0 to 99999999 (BCD 8-digit). (3) The following will result if an underflow is generated by the subtraction operation: The carry flag in this case does not go ON. 3 4 5 6 7 8 3 4 5 6 7 9 9 9 9 9 9 9...
Page 185 6 BASIC INSTRUCTIONS MELSEC-Q/QnA Usable Devices Internal Devices MELSECNET/10(H) Special Index (System, User) File Direct J \ Function Constant Data Register Other Register Module K, H Word Word U \G [Instruction Symbol] [Execution Condition] indicates the signs DB+ or DB- Command DB - Command...
Page 186 6 BASIC INSTRUCTIONS MELSEC-Q/QnA DB - (1) Subtracts the BCD 8-digit data designated by and the BCD 8-digit data designated by and stores the result of the subtraction at the device designated by (Upper 4 digits)(Lower 4 digits) (Upper 4 digits)(Lower 4 digits) (Upper 4 digits)(Lower 4 digits) 7 8 9 1 2 3 2 3 4 5 6 7...
Page 187: Bcd 4-Digit Multiplication And Division Operations (B , B P, B/, B/P)
6 BASIC INSTRUCTIONS MELSEC-Q/QnA QCPU PLC CPU Q4AR Process CPU Basic High Performance 6.2.7 BCD 4-digit multiplication and division operations (B , B P, B/, B/P) Usable Devices Internal Devices MELSECNET/10(H) Special Index (System, User) File Direct J \ Function Constant Data Register...
Page 188 6 BASIC INSTRUCTIONS MELSEC-Q/QnA (2) Uses 32 bits to store the result of the division as quotient and remainder Quotient (BCD 4 digits) ....Stored at the lower 16 bits Remainder (BCD 4 digits) ....Stored at the upper 16 bits (3) If has been designated as a bit device, the remainder of the operation will not be stored.
Page 189: Bcd 8-Digit Multiplication And Division Operations (Db , Db P, Db/, Db/P)
6 BASIC INSTRUCTIONS MELSEC-Q/QnA QCPU PLC CPU Q4AR Process CPU Basic High Performance 6.2.8 BCD 8-digit multiplication and division operations (DB , DB P, DB/, DB/P) Usable Devices Internal Devices MELSECNET/10(H) Special Index (System, User) File Direct J \ Function Constant Data Register...
Page 190 6 BASIC INSTRUCTIONS MELSEC-Q/QnA (1) Divides 8-digit BCD data designated by and 8-digit BCD data designated by , and stores the result in the device designated by Digits higher than those which were designated will be read as 0. Quotient (Upper 4 digits) (Lower 4 digits) Remain-...
Page 191: Addition And Subtraction Of Floating Decimal Point Data (E+, E+P, E-, E-P)
6 BASIC INSTRUCTIONS MELSEC-Q/QnA QCPU PLC CPU Q4AR Process CPU Basic High Performance 6.2.9 Addition and subtraction of floating decimal point data (E+, E+P, E-, E-P) Usable Devices Internal Devices MELSECNET/10(H) Special Index (System, User) File Direct J \ Function Constant Data Register...
Page 192 6 BASIC INSTRUCTIONS MELSEC-Q/QnA (1) Subtracts a floating decimal point type real number designated by and a floating decimal point type real number designated by , and stores the result at a device designated by Floating decimal point Floating decimal point Floating decimal point type real number type real number...
Page 193 6 BASIC INSTRUCTIONS MELSEC-Q/QnA Usable Devices Internal Devices MELSECNET/10(H) Special Index (System, User) File Direct J \ Function Constant Data Register Other Register Module Word Word U \G [Instruction Symbol] [Execution Condition] indicates the signs E+ or E- Command E+, E- Command E+P, E-P [Set Data]...
Page 194 6 BASIC INSTRUCTIONS MELSEC-Q/QnA (1) Subtracts the floating decimal point type real number designated by from the floating decimal point type real number designated by , and stores the result at the device designated by Floating decimal point Floating decimal point Floating decimal point type real number type real number...
Page 195: Multiplication And Division Of Floating Decimal Point Data (E , E P, E/, E/P)
6 BASIC INSTRUCTIONS MELSEC-Q/QnA QCPU PLC CPU Q4AR Process CPU Basic High Performance 6.2.10 Multiplication and division of floating decimal point data (E , E P, E/, E/P) Usable Devices Internal Devices MELSECNET/10(H) Special Index Other (System, User) File Direct J \ Function Constant Data...
Page 196 6 BASIC INSTRUCTIONS MELSEC-Q/QnA (1) Divides floating decimal point type real numbers designated by by floating decimal point type real numbers designated by , and stores the result in the device designated by Floating decimal point Floating decimal point Floating decimal point type real number type real number type real number...
Page 197: Block Addition And Subtraction (Bk+, Bk+P, Bk-, Bk-P)
6 BASIC INSTRUCTIONS MELSEC-Q/QnA QCPU PLC CPU Q4AR Process CPU Basic High Performance 6.2.11 Block addition and subtraction (BK+, BK+P, BK-, BK-P) Usable Devices Internal Devices MELSECNET/10(H) Special Index (System, User) File Direct J \ Function Constant Data Register Other Register Module K, H...
Page 198 6 BASIC INSTRUCTIONS MELSEC-Q/QnA (3) The constant designated by can be between -32768 to 32767 (BIN 16 bits). b15 - - - - - - - b0 b15 - - - - - - - b0 1234 (BIN) 5555 (BIN) 4567 (BIN) 8888...
Page 199 6 BASIC INSTRUCTIONS MELSEC-Q/QnA [Program Example] (1) When X20 is ON, the program performs additions of the following data: • The data in the number (value stored in D0) of devices starting from D100 • The data in the number (value stored in D0) of devices starting from R100 Then the program stores the addition results at the number (value stored in D0) of devices starting from D200.
Page 200: Linking Character Strings ($+, $+P)
6 BASIC INSTRUCTIONS MELSEC-Q/QnA QCPU PLC CPU Q4AR Process CPU Basic High Performance 6.2.12 Linking character strings ($+, $+P) Usable Devices Internal Devices MELSECNET/10(H) Special Index (System, User) File Direct J \ Function Constant Data Register Other Register Module Word Word U \G [Instruction Symbol] [Execution Condition]...
Page 201 6 BASIC INSTRUCTIONS MELSEC-Q/QnA [Operation Errors] (1) In the following cases an operation error occurs, the error flag (SM0) turns ON, and an error code is stored at SD. • The entire character string linked from the device number designated by to the final device number of the relevant device cannot be stored.
Page 202 6 BASIC INSTRUCTIONS MELSEC-Q/QnA Usable Devices Internal Devices MELSECNET/10(H) Special Index (System, User) File Direct J \ Function Constant Data Register Other Register Module Word Word U \G [Instruction Symbol] [Execution Condition] Command Command [Set Data] Set Data Meaning Data Type Head number of device holding linked data Head number of device holding data which has been linked Character string...
Page 203 6 BASIC INSTRUCTIONS MELSEC-Q/QnA [Operation Errors] (1) In the following cases an operation error occurs and the error flag goes ON. • The entire character string linked from the device number designated by to the final device number of the relevant device cannot be stored. •...
Page 204: Incrementing And Decrementing 16-Bit Bin Data (Inc, Incp, Dec, Decp)
6 BASIC INSTRUCTIONS MELSEC-Q/QnA QCPU PLC CPU Q4AR Process CPU Basic High Performance 6.2.13 Incrementing and decrementing 16-bit BIN data (INC, INCP, DEC, DECP) Usable Devices Internal Devices MELSECNET/10(H) Special Index (System, User) File Direct J \ Function Constant Data Register Other Register...
Page 205 6 BASIC INSTRUCTIONS MELSEC-Q/QnA [Program Example] (1) The present value stored in counter C0 to C20 is output to Y30 to Y3F as BCD data when X8 is on. (When present value is less than 9999) [Ladder Mode] Outputs the present value of C (D+Z1) to Y30 to Y3F as BCD.
Page 206: Incrementing And Decrementing 32-Bit Bin Data (Dinc, Dincp, Ddec, Ddecp)
6 BASIC INSTRUCTIONS MELSEC-Q/QnA QCPU PLC CPU Q4AR Process CPU Basic High Performance 6.2.14 Incrementing and decrementing 32-bit BIN data (DINC, DINCP, DDEC, DDECP) Usable Devices Internal Devices MELSECNET/10(H) Special Index (System, User) File Direct J \ Function Constant Data Register Other Register...
Page 207 6 BASIC INSTRUCTIONS MELSEC-Q/QnA [Program Example] (1) The following program adds 1 to the data at D0 and D1 when X0 is ON. [Ladder Mode] [List Mode] Steps Instruction Device (2) The following program adds 1 to the data set at X10 to X27 when X0 goes ON, and stores the result at D3 and D4.
Page 208: Data Conversion Instructions
6 BASIC INSTRUCTIONS MELSEC-Q/QnA QCPU PLC CPU Q4AR Process CPU Basic High Performance 6.3 Data Conversion Instructions 6.3.1 Conversion from BIN data to 4-digit and 8-digit BCD (BCD, BCDP, DBCD, DBCDP) Usable Devices Internal Devices MELSECNET/10(H) Special Index (System, User) File Direct J \ Function...
Page 209 6 BASIC INSTRUCTIONS MELSEC-Q/QnA [Operation Errors] (1) In the following cases an operation error occurs, the error flag (SM0) turns ON, and an error code is stored at SD0. • The data at was not in the 0 to 9999 range when the BCD instruction was issued. (Error code: 4100) •...
Page 210: Conversion From Bcd 4-Digit And 8-Digit Data To Bin Data (Bin, Binp, Dbin, Dbinp)
6 BASIC INSTRUCTIONS MELSEC-Q/QnA QCPU PLC CPU Q4AR Process CPU Basic High Performance 6.3.2 Conversion from BCD 4-digit and 8-digit data to BIN data (BIN, BINP, DBIN, DBINP) Usable Devices Internal Devices MELSECNET/10(H) Special Index Other (System, User) File Direct J \ Function Constant Data...
Page 211 6 BASIC INSTRUCTIONS MELSEC-Q/QnA [Operation Errors] (1) In the following cases, an operation error occurs, the error flag (SM0) turns ON, an error code is stored in SD0, and the instruction is not executed. • When values other than 0 to 9 are designated to any digits of [When QCPU is used] When QCPU is used, the error above can be suppressed by turning ON SM722.
Page 212: Conversion From Bin 16 And 32-Bit Data To Floating Decimal Point (Flt, Fltp, Dflt, Dfltp)
6 BASIC INSTRUCTIONS MELSEC-Q/QnA QCPU PLC CPU Q4AR Process CPU Basic High Performance 6.3.3 Conversion from BIN 16 and 32-bit data to floating decimal point (FLT, FLTP, DFLT, DFLTP) Usable Devices Internal Devices MELSECNET/10(H) Special Index (System, User) File Direct J \ Function Constant Data...
Page 213 6 BASIC INSTRUCTIONS MELSEC-Q/QnA (3) Due to the fact that floating decimal point type real numbers are processed by simple 32-bit processing, the number of significant digits is 24 bits if the display is binary and approximately 7 digits if the display is decimal. For this reason, if the integer exceeds the range of -16777216 to 16777215 (24-bit BIN value), errors can be generated in the conversion value.
Page 214: Conversion From Floating Decimal Point Data To Bin 16- And 32-Bit Data (Int, Intp, Dint, Dintp)
6 BASIC INSTRUCTIONS MELSEC-Q/QnA QCPU PLC CPU Q4AR Process CPU Basic High Performance 6.3.4 Conversion from floating decimal point data to BIN 16- and 32-bit data (INT, INTP, DINT, DINTP) Usable Devices Internal Devices MELSECNET/10(H) Special Index (System, User) File Direct J \ Function Constant...
Page 215 6 BASIC INSTRUCTIONS MELSEC-Q/QnA (2) The range of floating decimal point type real numbers that can be designated at +1 or from -2147483648 to 2147483647. (3) The integer value stored at +1 and is stored as BIN 32 bits. (4) After conversion, the first digit after the decimal point of the real number is rounded off. [Operation Errors] (1) In the following cases an operation error occurs, the error flag (SM0) turns ON, and an error code is stored at SD0.
Page 216: Conversion From Bin 16-Bit To Bin 32-Bit Data (Dbl, Dblp)
6 BASIC INSTRUCTIONS MELSEC-Q/QnA QCPU PLC CPU Q4AR Process CPU Basic High Performance 6.3.5 Conversion from BIN 16-bit to BIN 32-bit data (DBL, DBLP) Usable Devices Internal Devices MELSECNET/10(H) Special Index (System, User) File Direct J \ Function Constant Data Register Other Register...
Page 217: Conversion From Bin 32-Bit To Bin 16-Bit Data (Word, Wordp)
6 BASIC INSTRUCTIONS MELSEC-Q/QnA QCPU PLC CPU Q4AR Process CPU Basic High Performance 6.3.6 Conversion from BIN 32-bit to BIN 16-bit data (WORD, WORDP) Usable Devices Internal Devices MELSECNET/10(H) Special Index (System, User) File Direct J \ Function Constant Data Register Other Register...
Page 218: Conversion From Bin 16 And 32-Bit Data To Gray Code (Gry, Gryp, Dgry, Dgryp)
6 BASIC INSTRUCTIONS MELSEC-Q/QnA QCPU PLC CPU Q4AR Process CPU Basic High Performance 6.3.7 Conversion from BIN 16 and 32-bit data to Gray code (GRY, GRYP, DGRY, DGRYP) Usable Devices Internal Devices MELSECNET/10(H) Special Index (System, User) File Direct J \ Function Constant Data...
Page 219 6 BASIC INSTRUCTIONS MELSEC-Q/QnA [Operation Errors] (1) In the following cases an operation error occurs, the error flag (SM0) turns ON, and an error code is stored at SD0. • The data at is a negative number. [Program Example] (1) The following program converts the BIN data at D100 to Gray code when X10 is ON, and stores result at D200.
Page 220: Conversion Of Gray Code To Bin 16 And 32-Bit Data (Gbin, Gbinp, Dgbin, Dgbinp)
6 BASIC INSTRUCTIONS MELSEC-Q/QnA QCPU PLC CPU Q4AR Process CPU Basic High Performance 6.3.8 Conversion of Gray code to BIN 16 and 32-bit data (GBIN, GBINP, DGBIN, DGBINP) Usable Devices Internal Devices MELSECNET/10(H) Special Index (System, User) File Direct J \ Function Constant Data...
Page 221 6 BASIC INSTRUCTIONS MELSEC-Q/QnA [Operation Errors] (1) In the following cases an operation error occurs, the error flag (SM0) turns ON, and an error code is stored at SD0. • Data at when GBIN instruction was issued is outside the 0 to 32767 range. •...
Page 222: Complement Of 2 Of Bin 16- And 32-Bit Data (Sign Reversal) (Neg, Negp, Dneg, Dnegp)
6 BASIC INSTRUCTIONS MELSEC-Q/QnA QCPU PLC CPU Q4AR Process CPU Basic High Performance 6.3.9 Complement of 2 of BIN 16- and 32-bit data (sign reversal) (NEG, NEGP, DNEG, DNEGP) Usable Devices Internal Devices MELSECNET/10(H) Special Index (System, User) File Direct J \ Function Constant Data...
Page 223 6 BASIC INSTRUCTIONS MELSEC-Q/QnA DNEG (1) Reverses the sign of the 32-bit device designated by and stores at the device designated by 32 Bit b31- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -b0 .....
Page 224: Sign Reversal For Floating Decimal Point Data (Eneg, Enegp)
6 BASIC INSTRUCTIONS MELSEC-Q/QnA QCPU PLC CPU Q4AR Process CPU Basic High Performance 6.3.10 Sign reversal for floating decimal point data (ENEG, ENEGP) Usable Devices Internal Devices MELSECNET/10(H) Special Index (System, User) File Direct J \ Function Constant Data Register Other Register Module...
Page 225: Conversion From Block Bin 16-Bit Data To Bcd 4-Digit Data (Bkbcd, Bkbcdp)
6 BASIC INSTRUCTIONS MELSEC-Q/QnA QCPU PLC CPU Q4AR Process CPU Basic High Performance 6.3.11 Conversion from block BIN 16-bit data to BCD 4-digit data (BKBCD, BKBCDP) Usable Devices Internal Devices MELSECNET/10(H) Special Index (System, User) File Direct J \ Function Constant Data Register...
Page 226 6 BASIC INSTRUCTIONS MELSEC-Q/QnA [Operation Errors] (1) In the following cases an operation error occurs, the error flag (SM0) turns ON, and an error code is stored at SD0. • The range n-points from the device at exceeds the relevant device. (Error code: 4101) •...
Page 227: Conversion From Block Bcd 4-Digit Data To Block Bin 16-Bit Data (Bkbin, Bkbinp)
6 BASIC INSTRUCTIONS MELSEC-Q/QnA QCPU PLC CPU Q4AR Process CPU Basic High Performance 6.3.12 Conversion from block BCD 4-digit data to block BIN 16-bit data (BKBIN, BKBINP) Usable Devices Internal Devices MELSECNET/10(H) Special Index (System, User) File Direct J \ Function Constant Data...
Page 228 6 BASIC INSTRUCTIONS MELSEC-Q/QnA [Operation Errors] (1) In the following cases an operation error occurs, the error flag (SM0) turns ON, and an error code is stored at SD0. • The range n-points from the device exceeds the relevant device. •...
Page 229: Data Transfer Instructions
6 BASIC INSTRUCTIONS MELSEC-Q/QnA QCPU PLC CPU Q4AR Process CPU Basic High Performance 6.4 Data Transfer Instructions 6.4.1 16-bit and 32-bit data transfers (MOV, MOVP, DMOV, DMOVP) Usable Devices Internal Devices MELSECNET/10(H) Special Index (System, User) File Direct J \ Function Constant Data...
Page 230 6 BASIC INSTRUCTIONS MELSEC-Q/QnA [Operation Errors] (1) There are no operation errors associated with the MOV(P) or DMOV(P) instructions. [Program Example] (1) The following program stores input data from X0 to XB at D8. [Ladder Mode] [List Mode] Steps Instruction Device (2) The following program stores the constant K155 at D8 when X8 goes ON.
Page 231: Floating Decimal Point Data Transfers (Emov, Emovp)
6 BASIC INSTRUCTIONS MELSEC-Q/QnA QCPU PLC CPU Q4AR Process CPU Basic High Performance 6.4.2 Floating decimal point data transfers (EMOV, EMOVP) Usable Devices Internal Devices MELSECNET/10(H) Special Index (System, User) File Direct J \ Function Constant Data Register Other Register Module Word Word...
Page 232 6 BASIC INSTRUCTIONS MELSEC-Q/QnA [Program Example] (1) The following program stores the real numbers at D10 and D11 at D0 and D1. [Ladder Mode] [List Mode] Instruction Device Steps 36.475 36.475 (2) The following program stores the real number -1.23 at D10 and D11 when X8 is ON. [Ladder Mode] [List Mode] Steps...
Page 233: Character String Transfers ($Mov, $Movp)
6 BASIC INSTRUCTIONS MELSEC-Q/QnA QCPU PLC CPU Q4AR Process CPU Basic High Performance 6.4.3 Character string transfers ($MOV, $MOVP) Usable Devices Internal Devices MELSECNET/10(H) Special Index (System, User) File Direct J \ Function Constant Data Register Other Register Module Word Word U \G [Instruction Symbol] [Execution Condition]...
Page 234 6 BASIC INSTRUCTIONS MELSEC-Q/QnA (2) Processing will be performed without error even in cases where the range for the devices storing the character data to be transferred ( +n) overlaps with the range of the devices which will store the character string data after it has been transferred ( +n).
Page 235: 16-Bit And 32-Bit Negation Transfers (Cml, Cmlp, Dcml, Dcmlp)
6 BASIC INSTRUCTIONS MELSEC-Q/QnA QCPU PLC CPU Q4AR Process CPU Basic High Performance 6.4.4 16-bit and 32-bit negation transfers (CML, CMLP, DCML, DCMLP) Usable Devices Internal Devices MELSECNET/10(H) Special Index (System, User) File Direct J \ Function Constant Data Register Other Register Module...
Page 236 6 BASIC INSTRUCTIONS MELSEC-Q/QnA [Operation Errors] (1) There are no operation errors associated with the CML(P) or DCML(P) instructions. [Program Example] (1) The following program inverts the data from X0 to X7, and transfers result to D0. [Ladder Mode] [List Mode] Steps Instruction Device...
Page 237 6 BASIC INSTRUCTIONS MELSEC-Q/QnA (4) The following program inverts the data at X0 to X1F, and transfers results to D0 and D1. [Ladder Mode] [List Mode] Device Instruction Steps When the number of bits at is less than the number of bits at X8 X7 These bits are all read as 0 0 1 0 0...
Page 238: Block 16-Bit Data Transfers (Bmov, Bmovp)
6 BASIC INSTRUCTIONS MELSEC-Q/QnA QCPU PLC CPU Q4AR Process CPU Basic High Performance 6.4.5 Block 16-bit data transfers (BMOV, BMOVP) Usable Devices Internal Devices MELSECNET/10(H) Special Index (System, User) File Direct J \ Function Constant Data Register Other Register Module K, H Word Word...
Page 239 6 BASIC INSTRUCTIONS MELSEC-Q/QnA (4) If bit device has been designated for , then should always have the same number of digits. (5) Only either of can be designated for the MELSECNET/10(H) direct device and intelligent function module/special function module device. [Operation Errors] (1) In the following cases an operation error occurs, the error flag (SM0) turns ON, and an error code is stored at SD0.
Page 240: Identical 16-Bit Data Block Transfers (Fmov, Fmovp)
6 BASIC INSTRUCTIONS MELSEC-Q/QnA QCPU PLC CPU Q4AR Process CPU Basic High Performance 6.4.6 Identical 16-bit data block transfers (FMOV, FMOVP) Usable Devices Internal Devices MELSECNET/10(H) Special Index (System, User) File Direct J \ Function Constant Data Register Other Register Module K, H Word...
Page 241 6 BASIC INSTRUCTIONS MELSEC-Q/QnA [Operation Errors] (1) In the following cases an operation error occurs, the error flag (SM0) turns ON, and an error code is stored at SD0. • The device range n-points from exceeds the device range. (Error code: 4101) •...
Page 242: Bit And 32-Bit Data Exchanges (Xch, Xchp, Dxch, Dxchp)
6 BASIC INSTRUCTIONS MELSEC-Q/QnA QCPU PLC CPU Q4AR Process CPU Basic High Performance 6.4.7 16-bit and 32-bit data exchanges (XCH, XCHP, DXCH, DXCHP) Usable Devices Internal Devices MELSECNET/10(H) Special Index (System, User) File Direct J \ Function Constant Data Register Other Register Module...
Page 243 6 BASIC INSTRUCTIONS MELSEC-Q/QnA [Operation Errors] (1) There are no errors associated with the XCH (P) and DXCH (P) instructions. [Program Example] (1) The following program exchanges the present value of T0 with the contents of D0 when X8 goes ON. [Ladder Mode] [List Mode] Instruction...
Page 244: Block 16-Bit Data Exchanges (Bxch, Bxchp)
6 BASIC INSTRUCTIONS MELSEC-Q/QnA QCPU PLC CPU Q4AR Process CPU Basic High Performance 6.4.8 Block 16-bit data exchanges (BXCH, BXCHP) Usable Devices Internal Devices MELSECNET/10(H) Special Index (System, User) File Direct J \ Function Constant Data Register Other Register Module K, H Word Word...
Page 245 6 BASIC INSTRUCTIONS MELSEC-Q/QnA [Operation Errors] (1) In the following cases an operation error occurs, the error flag (SM0) turns ON, and an error code is stored at SD0. • The range n-points from the devices exceeds relevant device. (Error code: 4101) •...
Page 246: Upper And Lower Byte Exchanges (Swap, Swapp)
6 BASIC INSTRUCTIONS MELSEC-Q/QnA QCPU PLC CPU Q4AR Process CPU Basic High Performance 6.4.9 Upper and lower byte exchanges (SWAP, SWAPP) Usable Devices Internal Devices MELSECNET/10(H) Special Index (System, User) File Direct J \ Function Constant Data Register Other Register Module K, H Word...
Page 247: Program Branch Instruction
6 BASIC INSTRUCTIONS MELSEC-Q/QnA QCPU PLC CPU Q4AR Process CPU Basic High Performance 6.5 Program Branch Instruction 6.5.1 Pointer branch instructions (CJ, SCJ, JMP) Usable Devices Internal Devices MELSECNET/10(H) Special Index Other (System, User) File Direct J \ Function Constant Data Register Register...
Page 248 6 BASIC INSTRUCTIONS MELSEC-Q/QnA (2) Executes next step in program when jump command is OFF or when it goes from ON to OFF. Jump command OFF Executed each 1 scan scan (1) Unconditionally executes program of designated pointer number within the same program file. POINTS Note the following points when using the jump instruction.
Page 249 6 BASIC INSTRUCTIONS MELSEC-Q/QnA [Operation Errors] (1) In the following cases an operation is returned, the error flag (SM0) goes ON, and the error code is stored at SD0. • The pointer number designated does not come prior to the END instruction. (Error code: 4210) •...
Page 250: Jump To End (Goend)
6 BASIC INSTRUCTIONS MELSEC-Q/QnA QCPU PLC CPU Q4AR Process CPU Basic High Performance 6.5.2 Jump to END (GOEND) Usable Devices Internal Devices MELSECNET/10(H) Special Index (System, User) File Direct J \ Function Constant Data Register Other Register Module K, H Word Word U \G...
Page 251: Program Execution Control Instructions
6 BASIC INSTRUCTIONS MELSEC-Q/QnA QCPU PLC CPU Q4AR Process CPU Basic High Performance 6.6 Program Execution Control Instructions 6.6.1 Interrupt disable/enable instructions, interrupt program mask (DI, EI, IMASK) (1) When Basic model QCPU is used Usable Devices Internal Devices MELSECNET/10(H) Special Index (System, User)
Page 252 6 BASIC INSTRUCTIONS MELSEC-Q/QnA IMASK (1) Enables/disables the execution of the interrupt program marked by the designated interrupt pointer by using the bit pattern of 8 points from the device designated by • 1 (ON) ..Interrupt program execution enabled • 0 (OFF)..Interrupt program execution disabled (2) The interrupt pointer numbers corresponding to the individual bits are as shown below: b14 b13 b12 b11 b10 b9 I15 I14...
Page 253 6 BASIC INSTRUCTIONS MELSEC-Q/QnA [Operation Errors] (1) There are no operation errors associated with the DI and EI instructions. (2) There are no operation errors associated with the IMASK instruction. [Program Example] (1) The following program is designed to enable the execution of only the interrupt programs having the interrupt pointer numbers I1 and I3 while X0 is ON.
Page 254 6 BASIC INSTRUCTIONS MELSEC-Q/QnA (2) When the High Performance model QCPU/Process CPU is used Usable Devices Internal Devices MELSECNET/10(H) Special Index (System, User) File Direct J \ Function Constant Data Register Other Register Module K, H Word Word U \G [Instruction Symbol] [Execution Condition] Sequence program IMASK...
Page 255 6 BASIC INSTRUCTIONS MELSEC-Q/QnA IMASK (1) Enables/disables the execution of the interrupt program marked by the designated interrupt pointer by using the bit pattern of 16 points from the device designated by • 1 (ON) ..Interrupt program execution enabled • 0 (OFF)..Interrupt program execution disabled (2) The interrupt pointer numbers corresponding to the individual bits are as shown below: b14 b13 b12 b11 b10 b9 I15 I14...
Page 256 6 BASIC INSTRUCTIONS MELSEC-Q/QnA [Operation Errors] (1) There are no operation errors associated with the DI and EI instructions. (2) There are no operation errors associated with the IMASK instruction. [Program Example] (1) The following program creates an execution enabled state for the interrupt program marked by the interrupt pointer number when X0 is ON.
Page 257 6 BASIC INSTRUCTIONS MELSEC-Q/QnA (3) When QnACPU is used Usable Devices Internal Devices MELSECNET/10(H) Special Index (System, User) File Direct J \ Function Constant Data Register Other Register Module K, H Word Word U \G [Instruction Symbol] [Execution Condition] Sequence program IMASK IMASK [Set Data]...
Page 258 6 BASIC INSTRUCTIONS MELSEC-Q/QnA IMASK (1) Enables or disables the execution of the interrupt program marked by the designated interrupt pointer by use of the bit pattern in the three points from the device designated by • 1 (ON) ..Interrupt program execution enabled •...
Page 259 6 BASIC INSTRUCTIONS MELSEC-Q/QnA [Operation Errors] (1) There are no operation errors associated with the DI and EI instructions. (2) There are no operation errors associated with the IMASK instruction. [Program Example] (1) The following program creates an execution enabled state for the interrupt program marked by the interrupt pointer number when X0 is ON.
Page 260: Recovery From Interrupt Programs (Iret)
6 BASIC INSTRUCTIONS MELSEC-Q/QnA QCPU PLC CPU Q4AR Process CPU Basic High Performance 6.6.2 Recovery from interrupt programs (IRET) Usable Devices Internal Devices MELSECNET/10(H) Special Index (System, User) File Direct J \ Function Constant Data Register Other Register Module K, H Word Word U \G...
Page 261 6 BASIC INSTRUCTIONS MELSEC-Q/QnA [Program Example] (1) The following program adds 1 to D0 if M0 is ON when the number 3 interrupt is generated. [Ladder Mode] [List Mode] Instruction Device Steps 6 - 110 6 - 110 Artisan Technology Group - Quality Instrumentation ... Guaranteed | (888) 88-SOURCE | www.artisantg.com...
Page 262: I/O Refresh Instructions
6 BASIC INSTRUCTIONS MELSEC-Q/QnA QCPU PLC CPU Q4AR Process CPU Basic High Performance 6.7 I/O Refresh Instructions 6.7.1 I/O Refresh (RFS, RFSP) Usable Devices Internal Devices MELSECNET/10(H) Special Index (System, User) File Direct J \ Function Constant Data Register Other Register Module K, H...
Page 263 6 BASIC INSTRUCTIONS MELSEC-Q/QnA (3) Use direct access inputs (DX) or direct access outputs (DY) to refresh inputs (X) or outputs (Y) in 1-point units. [Program based on the RFS instruction] Command Refreshes X0 Command Refreshes Y20 [Program based on DX and DY] DY20 Direct access input Direct access output...
Page 264: Other Convenient Instructions
6 BASIC INSTRUCTIONS MELSEC-Q/QnA QCPU PLC CPU Q4AR Process CPU Basic High Performance 6.8 Other Convenient Instructions 6.8.1 Count 1-phase input up or down (UDCNT1) Usable Devices Internal Devices MELSECNET/10(H) Special Index (System, User) File Direct J \ Function Constant Data Register Other...
Page 265 6 BASIC INSTRUCTIONS MELSEC-Q/QnA The count processing performed on the present value is as shown below: -32768 -32767 32766 32767 When counting up When counting down (4) Count processing based on the UDCNT1 instruction starts the count when the count command goes from OFF to ON, and suspends the count when it goes from ON to OFF.
Page 266: Counter 2-Phase Input Up Or Down (Udcnt2)
6 BASIC INSTRUCTIONS MELSEC-Q/QnA QCPU PLC CPU Q4AR Process CPU Basic High Performance 6.8.2 Counter 2-phase input up or down (UDCNT2) Usable Devices Internal Devices MELSECNET/10(H) Special Index (System, User) File Direct J \ Function Constant Data Register Other Register Module K, H Word...
Page 267 6 BASIC INSTRUCTIONS MELSEC-Q/QnA The count processing performed on the present value is as shown below: -32768 -32767 32766 32767 When counting up When counting down (4) Count processing conducted according to the UDCNT2 instruction begins when the count command goes from OFF to ON, and is suspended when it goes from ON to OFF. When the count command goes from OFF to ON once again, the count is restarted from the value in effect when it was suspended.
Page 268: Teaching Timer (Ttmr)
6 BASIC INSTRUCTIONS MELSEC-Q/QnA QCPU PLC CPU Q4AR Process CPU Basic High Performance 6.8.3 Teaching timer (TTMR) Usable Devices Internal Devices MELSECNET/10(H) Special Index (System, User) File Direct J \ Function Constant Data Register Other Register Module K, H Word Word U \G [Instruction Symbol] [Execution Condition]...
Page 269 6 BASIC INSTRUCTIONS MELSEC-Q/QnA POINTS (1) Time measurements are conducted when the TTMR instruction is executed. Using the JMP or similar instruction to jump the TTMR instruction will make it impossible to get an accurate measurement. (2) Do not change the multiplier designated by n while the TTMR instruction is being executed. Changing this multiplier will result in an inaccurate value being returned.
Page 270: Special Function Timer (Stmr)
6 BASIC INSTRUCTIONS MELSEC-Q/QnA QCPU PLC CPU Q4AR Process CPU Basic High Performance 6.8.4 Special function timer (STMR) Usable Devices Internal Devices MELSECNET/10(H) Special Index (System, User) File Direct J \ Function Constant Data Register Other Register Module K, H Word Word U \G...
Page 271 6 BASIC INSTRUCTIONS MELSEC-Q/QnA (2) The timer coil designated by goes ON at the leading edge of the command for the STMR instruction, and begins the measurement of the present value. • The timer coil measures to the point where the value reaches the set value designated by n, then enters a time up state and goes OFF.
Page 272 6 BASIC INSTRUCTIONS MELSEC-Q/QnA [Program Example] (1) The following program turns Y0 and Y1 ON and OFF once each second (flicker) when X20 is ON. (Uses the 100ms timer) [Ladder Mode] [List Mode] Device Steps Instruction M1,Y0 M2,Y1 6 - 121 6 - 121 Artisan Technology Group - Quality Instrumentation ...
Page 273: Rotary Table Near Path Rotation Control (Rotc)
6 BASIC INSTRUCTIONS MELSEC-Q/QnA QCPU PLC CPU Q4AR Process CPU Basic High Performance 6.8.5 Rotary table near path rotation control (ROTC) Usable Devices Internal Devices MELSECNET/10(H) Special Index (System, User) File Direct J \ Function Data Register Constant Other Register Module Word Word...
Page 274 6 BASIC INSTRUCTIONS MELSEC-Q/QnA The direction of rotation is judged by whether the B phase pulse is at its leading or trailing edge when the A phase pulse is ON: • When the B phase is at the leading edge : Forward rotation (clockwise rotation) •...
Page 275: Ramp Signal (Ramp)
6 BASIC INSTRUCTIONS MELSEC-Q/QnA QCPU PLC CPU Q4AR Process CPU Basic High Performance 6.8.6 Ramp signal (RAMP) Usable Devices Internal Devices MELSECNET/10(H) Special Index (System, User) File Direct J \ Function Constant Data Register Other Register Module K, H Word Word U \G [Instruction Symbol] [Execution Condition]...
Page 276 6 BASIC INSTRUCTIONS MELSEC-Q/QnA (2) For n3, designate the number of scans required to move data from n1 to n2. No processing is performed when n3 = 0. (3) The system uses +1 to store the number of times the instruction has been executed. (4) When the move is completed to the final value, the completion device designated by +0 will go ON.
Page 277: Pulse Density Measurement (Spd)
6 BASIC INSTRUCTIONS MELSEC-Q/QnA QCPU PLC CPU Q4AR Process CPU Basic High Performance 6.8.7 Pulse density measurement (SPD) Usable Devices Internal Devices MELSECNET/10(H) Special Index (System, User) File Direct J \ Function Data Register Constant Other Register Module Word Word U \G (X only) : Local devices and the file registers set for individual programs cannot be used.
Page 278 6 BASIC INSTRUCTIONS MELSEC-Q/QnA POINTS (1) The SPD instruction registers the data from the argument device in the CPU module work area, and the actual count operation is conducted during a system interrupt. (The device data registered to the work area of the CPU module are cleared when the command input is turned OFF or when the CPU module is STOPped and then RUN.) Therefore, to count the pulses, it is necessary to provide their ON and OFF time as long as the interrupt time of the CPU module or longer.
Page 279: Fixed Cycle Pulse Output (Plsy)
6 BASIC INSTRUCTIONS MELSEC-Q/QnA QCPU PLC CPU Q4AR Process CPU Basic High Performance 6.8.8 Fixed cycle pulse output (PLSY) Usable Devices Internal Devices MELSECNET/10(H) Special Index (System, User) File Direct J \ Function Data Register Constant Other Register Module Word Word U \G : Only output (Y) can be used...
Page 280 6 BASIC INSTRUCTIONS MELSEC-Q/QnA POINT (1) The PLSY instruction registers the argument device data in the CPU module work area, and the actual output operation is processed during system interrupts. (The device data registered to the work area of the CPU module are cleared when the command input is turned OFF or when the CPU module is STOPped and then RUN.) Therefore, to count the pulses, it is necessary to provide their ON and OFF time as long as the interrupt time of the CPU module or longer.
Page 281: Pulse Width Modulation (Pwm)
6 BASIC INSTRUCTIONS MELSEC-Q/QnA QCPU PLC CPU Q4AR Process CPU Basic High Performance 6.8.9 Pulse width modulation (PWM) Usable Devices Internal Devices MELSECNET/10(H) Special Index (System, User) File Direct J \ Function Data Register Constant Other Register Module Word Word U \G : Only output (Y) can be used [Instruction Symbol] [Execution Condition]...
Page 282 6 BASIC INSTRUCTIONS MELSEC-Q/QnA [Operation Errors] (1) There are no operation errors associated with the PWM instruction. POINT (1) The PWM instruction registers the designated device data to the work area of the CPU module. The actual output operation is processed as the interruption by the CPU module. (The device data registered to the work area of the CPU module is cleared when the command input is turned OFF or when the CPU module is STOPped and then RUN.) The interrupt time of individual CPU module is shown below:...
Page 283: Matrix Input (Mtr)
6 BASIC INSTRUCTIONS MELSEC-Q/QnA QCPU PLC CPU Q4AR Process CPU Basic High Performance 6.8.10 Matrix input (MTR) Usable Devices Internal Devices MELSECNET/10(H) Special Index (System, User) File Direct J \ Function Data Register Constant Other Register Module Word Word U \G [Instruction Symbol] [Execution Condition] Command [Set Data]...
Page 284 6 BASIC INSTRUCTIONS MELSEC-Q/QnA (8) No processing is performed in the following cases. • The device number designated by , or is not divisible by 16. • The device designated by is outside the actual input range. • The device designated by is outside the actual output range.
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Melsec qnacpu Melsec q mode Melsec q series

Mitsubishi MELSEC QCPU Programming Manual

1 General Description

2 Instruction Tables

3 Configuration of Instructions

4 How to Read Instructions

5 Sequence Instructions

6 Basic Instructions

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