Control; Setting The Fpga Mode Select Pins; Related Resources - Xilinx MIcroBlaze Development Spartan-3E 1600E Kit User Manual

R

Control

Figure 11-4
I/O pin assignment and the I/O standard used.

Setting the FPGA Mode Select Pins

Set the FPGA configuration mode pins for either BPI Up or BPI down mode, as shown in
Table
Table 11-4: Selecting BPI-Up or BPI-Down Configuration Modes (Header J30 in
Chapter 4, "FPGA Configuration

Related Resources

MicroBlaze Development Kit Spartan-3E 1600 Edition User Guide
UG257 (v1.1) December 5, 2007
provides the UCF constraints for the StrataFlash control pins, including the
NET "SF_BYTE" LOC = "C17" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
NET "SF_CE0" LOC = "D16" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
NET "SF_OE" LOC = "C18" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
NET "SF_STS" LOC = "B18" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
NET "SF_WE" LOC = "D17" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
Figure 11-4: UCF Location Constraints for StrataFlash Control Pins
11-4. See
Configuration Mode Pins
Mode M2:M1:M0
BPI Up 0:1:0
BPI Down 0:1:1
Intel J3 StrataFlash Data Sheet
http://www.intel.com/design/flcomp/products/j3/techdocs.htm#datasheets
Application Note 827, Intel StrataFlash
Design Guide
http://www.intel.com/design/flcomp/applnots/307257.htm
Setting the FPGA Mode Select Pins
Options", Figure 4-2)
FPGA Configuration Image in
StrataFlash
FPGA starts at address 0 and
increments through address space.
The CPLD controls address lines
A[24:20] during BPI configuration.
FPGA starts at address 0xFF_FFFF
and decrements through address
space. The CPLD controls address
lines A[24:20] during BPI
configuration.
®
Memory (J3) to Xilinx Spartan-3E FPGA
UG257_11_04_060706
Jumper Settings
M0
M1
M2
J30
M0
M1
M2
J30
89
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