Programmable Counter Array; Figure 24.1. Pca Block Diagram - Silicon Laboratories C8051F12 Series Manual

C8051F120/1/2/3/4/5/6/7 C8051F130/1/2/3

24. Programmable Counter Array

The Programmable Counter Array (PCA0) provides enhanced timer functionality while requiring less CPU
intervention than the standard 8051 counter/timers. PCA0 consists of a dedicated 16-bit counter/timer and
six 16-bit capture/compare modules. Each capture/compare module has its own associated I/O line
(CEXn) which is routed through the Crossbar to Port I/O when enabled (See
through 3 and the Priority Crossbar Decoder" on page 238
mable timebase that can select between six inputs as its source: system clock, system clock divided by
four, system clock divided by twelve, the external oscillator clock source divided by 8, Timer 0 overflow, or
an external clock signal on the ECI line. Each capture/compare module may be configured to operate inde-
pendently in one of six modes: Edge-Triggered Capture, Software Timer, High-Speed Output, Frequency
Output, 8-Bit PWM, or 16-Bit PWM (each is described in
trolled through the system controller's Special Function Registers. The basic PCA block diagram is shown
in Figure 24.1.
SYSCLK/12
SYSCLK/4
Timer 0 Overflow
ECI
SYSCLK
External Clock/8
Capture/Compare
Module 0
PCA
16-Bit Counter/Timer
CLOCK
MUX
Capture/Compare Capture/Compare
Module 1 Module 2
Crossbar
Port I/O

Figure 24.1. PCA Block Diagram

). The counter/timer is driven by a program-
Section 24.2 ). The PCA is configured and con-
Capture/Compare Capture/Compare
Module 3 Module 4
Rev. 1.4
Section "18.1. Ports 0
Capture/Compare
Module 5
325