Sfr Definition 18.8. P1Mdout: Port1 Output Mode; Sfr Definition 18.9. P2: Port2 Data - Silicon Laboratories C8051F12 Series Manual

C8051F120/1/2/3/4/5/6/7 C8051F130/1/2/3

SFR Definition 18.8. P1MDOUT: Port1 Output Mode

R/W R/W
Bit7 Bit6
Bits7–0: P1MDOUT.[7:0]: Port1 Output Mode Bits.
0: Port Pin output mode is configured as Open-Drain.
1: Port Pin output mode is configured as Push-Pull.
Note: SDA, SCL, and RX0 (when UART0 is in Mode 0) and RX1 (when UART1 is in Mode 0) are
always configured as Open-Drain when they appear on Port pins.
R/W R/W
P2.7 P2.6
Bit7 Bit6
Bits7–0: P2.[7:0]: Port2 Output Latch Bits.
(Write - Output appears on I/O pins per XBR0, XBR1, and XBR2 Registers)
0: Logic Low Output.
1: Logic High Output (open if corresponding P2MDOUT.n bit = 0).
(Read - Regardless of XBR0, XBR1, and XBR2 Register settings).
0: P2.n pin is logic low.
1: P2.n pin is logic high.
Note: P2.[7:0] can be driven by the External Data Memory Interface (as Address[15:8] in Multiplexed
mode, or as Address[7:0] in Non-multiplexed mode). See
Memory Interface and On-Chip XRAM" on page 219
External Memory Interface.
250
R/W R/W R/W
Bit5 Bit4 Bit3

SFR Definition 18.9. P2: Port2 Data

R/W R/W R/W
P2.5 P2.4 P2.3
Bit5 Bit4 Bit3
Rev. 1.4
R/W R/W R/W
Bit2 Bit1 Bit0
SFR Address:
SFR Page:
R/W R/W R/W
P2.2 P2.1 P2.0
Bit2 Bit1 Bit0
Address:
SFR Page:
Section "17. External Data
for more information about the
Reset Value
00000000
0xA5
F
Reset Value
11111111
Bit
Addressable
SFR
0xA0
All Pages